From d23471776ed8863adf0762e55dcfbce79c248607 Mon Sep 17 00:00:00 2001
From: Anish Nair <Anish.Nair@arm.com>
Date: Fri, 11 Sep 2026 11:44:37 +0000
Subject: [PATCH] fix (baremetal/sbsa): create dependent info tables for PMU,
 RAS and CXL

 This covers SRAT for PMU/RAS, PCIe for PMU/CXL, IOVIRT for CXL, and
    adds the missing CXL table cleanup.

Change-Id: I9904239a68791215b5d6b9f489d8f4f3a36fb20b
---
 apps/baremetal/sbsa_main.c | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/apps/baremetal/sbsa_main.c b/apps/baremetal/sbsa_main.c
index 70a2816e..6c180abe 100644
--- a/apps/baremetal/sbsa_main.c
+++ b/apps/baremetal/sbsa_main.c
@@ -60,20 +60,27 @@ freeAcsMeM(void)
         val_cache_free_info_table();
         val_mpam_free_info_table();
         val_hmat_free_info_table();
-        val_srat_free_info_table();
         val_pcc_free_info_table();
     }
 
+    if (acs_is_module_enabled(MPAM)         ||
+        acs_is_module_enabled(PMU)          ||
+        acs_is_module_enabled(RAS))
+       val_srat_free_info_table();
+
     if (acs_is_module_enabled(PCIE)        ||
         acs_is_module_enabled(GIC)         ||
         acs_is_module_enabled(GPU)         ||
-        acs_is_module_enabled(SMMU))
+        acs_is_module_enabled(SMMU)        ||
+        acs_is_module_enabled(PMU)         ||
+        acs_is_module_enabled(CXL))
        val_pcie_free_info_table();
 
    if (acs_is_module_enabled(SMMU)         ||
        acs_is_module_enabled(GIC)          ||
        acs_is_module_enabled(MEM_MAP)      ||
        acs_is_module_enabled(GPU)          ||
+       acs_is_module_enabled(CXL)          ||
        acs_is_module_enabled(PCIE))
        val_iovirt_free_info_table();
 
@@ -94,6 +101,9 @@ freeAcsMeM(void)
        val_ras_free_info_table();
    }
 
+   if (acs_is_module_enabled(CXL))
+       val_cxl_free_info_table();
+
    val_free_shared_mem();
 }
 
@@ -253,19 +263,26 @@ ShellAppMainsbsa()
         createPccInfoTable();
         createMpamInfoTable();
         createHmatInfoTable();
-        createSratInfoTable();
     }
 
+    if (acs_is_module_enabled(MPAM)         ||
+        acs_is_module_enabled(PMU)          ||
+        acs_is_module_enabled(RAS))
+        createSratInfoTable();
+
     if (acs_is_module_enabled(PCIE)       ||
         acs_is_module_enabled(GIC)        ||
         acs_is_module_enabled(GPU)        ||
-        acs_is_module_enabled(SMMU))
+        acs_is_module_enabled(SMMU)       ||
+        acs_is_module_enabled(PMU)        ||
+        acs_is_module_enabled(CXL))
         createPcieInfoTable();
 
     if (acs_is_module_enabled(GIC)        ||
         acs_is_module_enabled(PCIE)       ||
         acs_is_module_enabled(MEM_MAP)    ||
         acs_is_module_enabled(GPU)        ||
+        acs_is_module_enabled(CXL)        ||
         acs_is_module_enabled(SMMU))
         createIoVirtInfoTable();