diff --git a/apps/uefi/Bsa.inf b/apps/uefi/Bsa.inf index 1efe12b5..ea4f8cab 100644 --- a/apps/uefi/Bsa.inf +++ b/apps/uefi/Bsa.inf @@ -217,11 +217,11 @@ ../../test_pool/smmu/i017.c ../../test_pool/smmu/i018.c ../../test_pool/smmu/i019.c - ../../test_pool/smmu/i020.c ../../test_pool/smmu/i021.c ../../test_pool/smmu/i022.c ../../test_pool/smmu/i024.c ../../test_pool/smmu/i025.c + ../../test_pool/smmu/i026.c ../../test_pool/memory_map/m005.c ../../test_pool/pcie/p004.c ../../test_pool/pcie/p005.c diff --git a/apps/uefi/Sbsa.inf b/apps/uefi/Sbsa.inf index d1ce6738..c99681f2 100644 --- a/apps/uefi/Sbsa.inf +++ b/apps/uefi/Sbsa.inf @@ -218,11 +218,11 @@ ../../test_pool/smmu/i017.c ../../test_pool/smmu/i018.c ../../test_pool/smmu/i019.c - ../../test_pool/smmu/i020.c ../../test_pool/smmu/i021.c ../../test_pool/smmu/i022.c ../../test_pool/smmu/i024.c ../../test_pool/smmu/i025.c + ../../test_pool/smmu/i026.c ../../test_pool/memory_map/m005.c ../../test_pool/pcie/p004.c ../../test_pool/pcie/p005.c diff --git a/apps/uefi/SbsaNist.inf b/apps/uefi/SbsaNist.inf index 799c9834..42b490f0 100644 --- a/apps/uefi/SbsaNist.inf +++ b/apps/uefi/SbsaNist.inf @@ -83,6 +83,7 @@ ../../test_pool/gic/g016.c ../../test_pool/timer/t006.c ../../test_pool/watchdog/w003.c + ../../test_pool/smmu/i007.c ../../test_pool/smmu/i008.c ../../test_pool/smmu/i009.c ../../test_pool/smmu/i010.c @@ -94,11 +95,11 @@ ../../test_pool/smmu/i017.c ../../test_pool/smmu/i018.c ../../test_pool/smmu/i019.c - ../../test_pool/smmu/i020.c ../../test_pool/smmu/i021.c ../../test_pool/smmu/i022.c ../../test_pool/smmu/i024.c ../../test_pool/smmu/i025.c + ../../test_pool/smmu/i026.c ../../test_pool/memory_map/m001.c ../../test_pool/memory_map/m005.c ../../test_pool/pcie/p001.c diff --git a/apps/uefi/Vbsa.inf b/apps/uefi/Vbsa.inf index f46b2d34..c58f745b 100644 --- a/apps/uefi/Vbsa.inf +++ b/apps/uefi/Vbsa.inf @@ -220,11 +220,11 @@ ../../test_pool/smmu/i017.c ../../test_pool/smmu/i018.c ../../test_pool/smmu/i019.c - ../../test_pool/smmu/i020.c ../../test_pool/smmu/i021.c ../../test_pool/smmu/i022.c ../../test_pool/smmu/i024.c ../../test_pool/smmu/i025.c + ../../test_pool/smmu/i026.c ../../test_pool/memory_map/m005.c ../../test_pool/pcie/p004.c ../../test_pool/pcie/p005.c diff --git a/apps/uefi/pc_bsa.inf b/apps/uefi/pc_bsa.inf index 861ab881..101782b4 100644 --- a/apps/uefi/pc_bsa.inf +++ b/apps/uefi/pc_bsa.inf @@ -218,11 +218,11 @@ ../../test_pool/smmu/i017.c ../../test_pool/smmu/i018.c ../../test_pool/smmu/i019.c - ../../test_pool/smmu/i020.c ../../test_pool/smmu/i021.c ../../test_pool/smmu/i022.c ../../test_pool/smmu/i024.c ../../test_pool/smmu/i025.c + ../../test_pool/smmu/i026.c ../../test_pool/memory_map/m005.c ../../test_pool/pcie/p004.c ../../test_pool/pcie/p005.c diff --git a/apps/uefi/xbsa_acpi.inf b/apps/uefi/xbsa_acpi.inf index 78d8c4c9..36ed3778 100644 --- a/apps/uefi/xbsa_acpi.inf +++ b/apps/uefi/xbsa_acpi.inf @@ -214,11 +214,11 @@ ../../test_pool/smmu/i017.c ../../test_pool/smmu/i018.c ../../test_pool/smmu/i019.c - ../../test_pool/smmu/i020.c ../../test_pool/smmu/i021.c ../../test_pool/smmu/i022.c ../../test_pool/smmu/i024.c ../../test_pool/smmu/i025.c + ../../test_pool/smmu/i026.c ../../test_pool/memory_map/m005.c ../../test_pool/pcie/p004.c ../../test_pool/pcie/p005.c diff --git a/docs/bsa/arm_bsa_testcase_checklist.md b/docs/bsa/arm_bsa_testcase_checklist.md index eac735e8..272355c1 100644 --- a/docs/bsa/arm_bsa_testcase_checklist.md +++ b/docs/bsa/arm_bsa_testcase_checklist.md @@ -681,7 +681,7 @@ The checklist provides information about: - + ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence. diff --git a/docs/pc_bsa/arm_pc-bsa_testcase_checklist.md b/docs/pc_bsa/arm_pc-bsa_testcase_checklist.md index 4599c02c..df6fbe02 100644 --- a/docs/pc_bsa/arm_pc-bsa_testcase_checklist.md +++ b/docs/pc_bsa/arm_pc-bsa_testcase_checklist.md @@ -236,15 +236,23 @@ The checklist provides information about: No - 320 - Check SMMU Coherent Access Support - 1 - P_L1SM_04 + 307 + SMMU_01: SMMUv3 Integration compliance + 1 + P_L1SM_04 Yes Yes Yes No + + Not Covered + SMMU_02: ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence. + No + + + + 322 Check if all DMA reqs behind SMMU diff --git a/docs/sbsa/arm_sbsa_testcase_checklist.md b/docs/sbsa/arm_sbsa_testcase_checklist.md index deaed947..a047c3af 100644 --- a/docs/sbsa/arm_sbsa_testcase_checklist.md +++ b/docs/sbsa/arm_sbsa_testcase_checklist.md @@ -314,17 +314,27 @@ The checklist provides information about: - L4 - S_L4SM_03 - S_L4SM_03 - 320 - Check SMMU Coherent Access Support + L4 + S_L4SM_03 + SMMU_01 + 307 + SMMUv3 Integration compliance Yes Yes No + + SMMU_02 + Not Covered + + + + + ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence. + + L4 S_L4PCI_1 diff --git a/test_pool/smmu/i007.c b/test_pool/smmu/i007.c index 2004f768..a6686903 100644 --- a/test_pool/smmu/i007.c +++ b/test_pool/smmu/i007.c @@ -34,13 +34,6 @@ payload() index = val_pe_get_index_mpid(val_pe_get_mpid()); - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - if (data == 0) { - val_print(WARN, "\n PCIe Subsystem not discovered "); - val_set_status(index, RESULT_SKIP(1)); - return; - } - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { diff --git a/test_pool/smmu/i020.c b/test_pool/smmu/i020.c deleted file mode 100644 index 96e86ec6..00000000 --- a/test_pool/smmu/i020.c +++ /dev/null @@ -1,86 +0,0 @@ -/** @file - * Copyright (c) 2020-2026, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "acs_val.h" -#include "val_interface.h" -#include "acs_smmu.h" -#include "acs_pcie.h" - -#define TEST_NUM (ACS_SMMU_TEST_NUM_BASE + 20) -#ifdef PC_BSA -#define TEST_RULE "P_L1SM_04" -#else -#define TEST_RULE "S_L4SM_03" -#endif -#define TEST_DESC "Check SMMU Coherent Access Support " - -static -void -payload(void) -{ - - uint64_t data; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(ERROR, "\n No SMMU Controllers are discovered "); - val_set_status(index, RESULT_SKIP(02)); - return; - } - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(WARN, "\n Not valid for SMMU v2 "); - val_set_status(index, RESULT_SKIP(03)); - return; - } - - data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 4, 4); - - /* Check If SMMU_IDR0.COHACC == 1*/ - if (data != 1) { - val_set_status(index, RESULT_FAIL(01)); - return; - } - } - - val_set_status(index, RESULT_PASS); -} - -uint32_t -i020_entry(uint32_t num_pe) -{ - - uint32_t status = ACS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); - if (status != ACS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - - val_report_status(0, ACS_END(TEST_NUM), TEST_RULE); - - return status; -} diff --git a/test_pool/smmu/i026.c b/test_pool/smmu/i026.c new file mode 100644 index 00000000..fb3d6cd8 --- /dev/null +++ b/test_pool/smmu/i026.c @@ -0,0 +1,100 @@ +/** @file + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "acs_val.h" +#include "acs_pe.h" +#include "val_interface.h" +#include "acs_smmu.h" + +#define TEST_NUM (ACS_SMMU_TEST_NUM_BASE + 32) +#define TEST_RULE "SMMU_02" +#define TEST_DESC "Check SMMU stall flow support " + +#define SMMU_STALL_MODEL_TERMINATE 0x1 + +static +void +payload() +{ + uint32_t index; + uint32_t num_smmu; + uint32_t smmu_index; + uint32_t stall_model; + uint32_t relevant_smmu = 0; + uint32_t stall_supported = 0; + + index = val_pe_get_index_mpid(val_pe_get_mpid()); + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(DEBUG, "\n No SMMU Controllers are discovered"); + val_set_status(index, RESULT_SKIP(1)); + return; + } + + for (smmu_index = 0; smmu_index < num_smmu; smmu_index++) { + /* IDR0.STALL_MODEL is defined for SMMUv3 controllers. */ + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, smmu_index) < 3) { + val_print(DEBUG, "\n SMMU %x is not an SMMUv3 controller", smmu_index); + continue; + } + + relevant_smmu++; + stall_model = VAL_EXTRACT_BITS( + val_smmu_read_cfg(SMMUv3_IDR0, smmu_index), 24, 25); + + val_print(DEBUG, "\n SMMU %x IDR0.STALL_MODEL = 0x%x", + smmu_index, stall_model); + + if (stall_model != SMMU_STALL_MODEL_TERMINATE) + stall_supported = 1; + } + + if (relevant_smmu == 0) { + val_print(DEBUG, "\n SMMU_02 not applicable: No SMMUv3 controllers"); + val_set_status(index, RESULT_SKIP(2)); + return; + } + + if (!stall_supported) { + val_print(INFO, "\n SMMU_02 not applicable: Stall model is not supported"); + val_set_status(index, RESULT_SKIP(3)); + return; + } + + val_print(WARN, "\n Stall supported - integration/DV evidence required"); + val_set_status(index, RESULT_WARNING(1)); +} + +uint32_t +i032_entry(uint32_t num_pe) +{ + uint32_t status = ACS_STATUS_FAIL; + + num_pe = 1; // This test is run on a single processor + + val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe); + + if (status != ACS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, ACS_END(TEST_NUM), TEST_RULE); + + return status; +} diff --git a/tools/cmake/infra/bsa_test.txt b/tools/cmake/infra/bsa_test.txt index a86592cb..1c3140a3 100644 --- a/tools/cmake/infra/bsa_test.txt +++ b/tools/cmake/infra/bsa_test.txt @@ -84,6 +84,7 @@ i017.c i018.c i019.c i025.c +i026.c p001.c p002.c p003.c diff --git a/tools/cmake/infra/pc_bsa_test.txt b/tools/cmake/infra/pc_bsa_test.txt index 7fcbdea6..38813e78 100644 --- a/tools/cmake/infra/pc_bsa_test.txt +++ b/tools/cmake/infra/pc_bsa_test.txt @@ -45,9 +45,9 @@ i005.c i006.c i007.c i008.c -i020.c i022.c i025.c +i026.c m001.c m002.c m003.c diff --git a/tools/cmake/infra/sbsa_test.txt b/tools/cmake/infra/sbsa_test.txt index f10dd5cb..d00ba952 100644 --- a/tools/cmake/infra/sbsa_test.txt +++ b/tools/cmake/infra/sbsa_test.txt @@ -56,12 +56,12 @@ i016.c i017.c i018.c i019.c -i020.c i021.c i022.c i023.c i024.c i025.c +i026.c m005.c p001.c p002.c diff --git a/val/include/acs_smmu.h b/val/include/acs_smmu.h index dd50e339..0288d538 100644 --- a/val/include/acs_smmu.h +++ b/val/include/acs_smmu.h @@ -78,7 +78,6 @@ uint32_t i016_entry(uint32_t num_pe); uint32_t i017_entry(uint32_t num_pe); uint32_t i018_entry(uint32_t num_pe); uint32_t i019_entry(uint32_t num_pe); -uint32_t i020_entry(uint32_t num_pe); uint32_t i021_entry(uint32_t num_pe); uint32_t i022_entry(uint32_t num_pe); uint32_t i023_entry(uint32_t num_pe); @@ -90,5 +89,6 @@ uint32_t i028_entry(uint32_t num_pe); uint32_t i029_entry(uint32_t num_pe); uint32_t i030_entry(uint32_t num_pe); uint32_t i031_entry(uint32_t num_pe); +uint32_t i032_entry(uint32_t num_pe); #endif diff --git a/val/include/rule_based_execution_enum.h b/val/include/rule_based_execution_enum.h index 53d1bfa6..794747b8 100644 --- a/val/include/rule_based_execution_enum.h +++ b/val/include/rule_based_execution_enum.h @@ -757,7 +757,6 @@ typedef enum { I024_ENTRY, I008_ENTRY, I025_ENTRY, - I020_ENTRY, I009_ENTRY, I026_ENTRY, I013_ENTRY, @@ -768,6 +767,7 @@ typedef enum { I027_ENTRY, I028_ENTRY, I031_ENTRY, + I032_ENTRY, T001_ENTRY, T002_ENTRY, T003_ENTRY, diff --git a/val/src/pc_bsa_execute_test.c b/val/src/pc_bsa_execute_test.c index 7dc1e595..6d2eac6d 100644 --- a/val/src/pc_bsa_execute_test.c +++ b/val/src/pc_bsa_execute_test.c @@ -179,7 +179,8 @@ val_pcbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe) return ACS_STATUS_FAIL; } - status |= i020_entry(num_pe); + status |= i007_entry(num_pe); + status |= i032_entry(num_pe); status |= i022_entry(num_pe); } diff --git a/val/src/rule_metadata.c b/val/src/rule_metadata.c index 73e76558..c68e98e5 100644 --- a/val/src/rule_metadata.c +++ b/val/src/rule_metadata.c @@ -1321,6 +1321,14 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = { .flag = BASE_RULE, .test_num = ACS_SMMU_TEST_NUM_BASE + 7, }, + [SMMU_02] = { + .test_entry_id = I032_ENTRY, + .module_id = SMMU, + .rule_desc = "Check SMMU stall flow support", + .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI, + .flag = BASE_RULE, + .test_num = ACS_SMMU_TEST_NUM_BASE + 32, + }, [S_L4SM_01] = { .test_entry_id = I008_ENTRY, .module_id = SMMU, @@ -1338,12 +1346,11 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = { .test_num = ACS_SMMU_TEST_NUM_BASE + 25, }, [S_L4SM_03] = { - .test_entry_id = I020_ENTRY, + .test_entry_id = NULL_ENTRY, .module_id = SMMU, - .rule_desc = "Check SMMU Coherent Access Support", + .rule_desc = "Check integration of SMMU", .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI, - .flag = BASE_RULE, - .test_num = ACS_SMMU_TEST_NUM_BASE + 20, + .flag = ALIAS_RULE, }, [S_L5SM_01] = { .test_entry_id = I009_ENTRY, @@ -2580,12 +2587,11 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = { .test_num = ACS_SMMU_TEST_NUM_BASE + 25, }, [P_L1SM_04] = { - .test_entry_id = I020_ENTRY, + .test_entry_id = NULL_ENTRY, .module_id = SMMU, - .rule_desc = "Check SMMU Coherent Access Support", + .rule_desc = "Check integration of SMMU", .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI, - .flag = BASE_RULE, - .test_num = ACS_SMMU_TEST_NUM_BASE + 20, + .flag = ALIAS_RULE, }, [P_L1SM_05] = { .test_entry_id = I022_ENTRY, @@ -3196,9 +3202,6 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = { [B_SMMU_25] = { .module_id = SMMU, }, - [SMMU_02] = { - .module_id = SMMU, - }, [S_L3SM_01] = { .module_id = SMMU, }, @@ -3668,7 +3671,6 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = { [I017_ENTRY] = i017_entry, [I018_ENTRY] = i018_entry, [I019_ENTRY] = i019_entry, - [I020_ENTRY] = i020_entry, [I021_ENTRY] = i021_entry, [I022_ENTRY] = i022_entry, [I024_ENTRY] = i024_entry, // used in wrapper @@ -3679,6 +3681,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = { [I029_ENTRY] = i029_entry, [I030_ENTRY] = i030_entry, [I031_ENTRY] = i031_entry, + [I032_ENTRY] = i032_entry, [INTERFACE010_ENTRY] = interface010_entry, [INTERFACE011_ENTRY] = interface011_entry, [ITS001_ENTRY] = its001_entry, @@ -4011,10 +4014,10 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = { [I006_ENTRY] = i006_entry, [I007_ENTRY] = i007_entry, [I008_ENTRY] = i008_entry, - [I020_ENTRY] = i020_entry, [I022_ENTRY] = i022_entry, [I025_ENTRY] = i025_entry, [I029_ENTRY] = i029_entry, + [I032_ENTRY] = i032_entry, [T001_ENTRY] = t001_entry, [T002_ENTRY] = t002_entry, [T003_ENTRY] = t003_entry, @@ -4217,7 +4220,6 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = { [I024_ENTRY] = i024_entry, // used in wrapper [I025_ENTRY] = i025_entry, [I014_ENTRY] = i014_entry, - [I020_ENTRY] = i020_entry, [I021_ENTRY] = i021_entry, [I027_ENTRY] = i027_entry, [I023_ENTRY] = i023_entry, @@ -4448,6 +4450,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = { [I005_ENTRY] = i005_entry, [I029_ENTRY] = i029_entry, [I007_ENTRY] = i007_entry, + [I032_ENTRY] = i032_entry, [P042_ENTRY] = p042_entry, [P030_ENTRY] = p030_entry, // used in wrapper. [P032_ENTRY] = p032_entry, // used in wrapper. @@ -4807,6 +4810,9 @@ const RULE_ID_e s_l5sm_04_rule_list[] = {B_SMMU_09, B_SMMU_20, RULE_ID_SENTINE const RULE_ID_e s_l6sm_04_rule_list[] = {B_SMMU_03, B_SMMU_04, B_SMMU_05, B_SMMU_13, B_SMMU_14, B_SMMU_23, RULE_ID_SENTINEL}; +const RULE_ID_e p_l1sm_04_s_l4sm_03_rule_list[] = { + SMMU_01, SMMU_02, RULE_ID_SENTINEL}; + /* PCBSA alias lists */ /* P_L2WD_01 */ const RULE_ID_e p_l2wd_01_rule_list[] = {B_WD_01, B_WD_02, B_WD_03, B_WD_04, B_WD_05, @@ -4904,12 +4910,13 @@ const alias_rule_map_t alias_rule_map[] = { {XDGKZ, xdgkz_rule_list}, {S_L5SM_04, s_l5sm_04_rule_list}, {S_L6SM_04, s_l6sm_04_rule_list}, + {S_L4SM_03, p_l1sm_04_s_l4sm_03_rule_list}, /* PCBSA alias rules */ {P_L1_01, bsa_l1_rule_list}, {P_L2WD_01, p_l2wd_01_rule_list}, {P_L1MM_01, p_l1mm_01_rule_list}, - + {P_L1SM_04, p_l1sm_04_s_l4sm_03_rule_list}, /* VBSA alias rules */ {V_L1PE_01, v_l1pe_01_rule_list}, {V_L1MM_01, v_l1mm_01_rule_list}, diff --git a/val/src/sbsa_execute_test.c b/val/src/sbsa_execute_test.c index 054c2a8b..5fa7905d 100644 --- a/val/src/sbsa_execute_test.c +++ b/val/src/sbsa_execute_test.c @@ -488,7 +488,8 @@ val_sbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe) return ACS_STATUS_FAIL; } - status |= i020_entry(num_pe); + status |= i007_entry(num_pe); + status |= i032_entry(num_pe); } if (((level > 4) && (g_sbsa_only_level == 0)) || (g_sbsa_only_level == 5)) {