Explicitly expose ports of a subcircuit

[sequoiap]

Should we force the user to explicitly expose the ports of a subcircuit, rather than ordering them automatically simply by insertion order? This would allow users to also customize definition order of ports, maybe allowing for some sort of "interface" connection function that connects channels across to each other.

[cjcarver]

I do like the simplicity of just a simple rule like insertion order, but I think I the ability to customize the order of ports is better. I'm not sure how this "interface" function would work out, though.

Say I had an MZI circuit with four ports: 2 inputs and 2 outputs so the ordering of the ports are o(0), o(1), o(2), o(3).

def mzi_factory(dl=1):
    ckt = Circuit()
    c1 = Coupler()
    c2 = Coupler()
    wg = Waveguide(length=dl)
    ckt.connect(c1.o(2), c2.o(0))
    ckt.connect(c1.o(1), wg.o(0))
    ckt.connect(c2.o(1), wg.o(1))
    return ckt

What if I wanted to order the s_parameters arbitrarily to a specific order o(1), o(3), o(2), o(0) for example?

I'm thinking this would just be some function like expose (we could change the name to something better like "interface" or something). ckt.expose([1,3,2,0]) This would then order the parameters in the way we want, and if indices or ports were omitted it would just add a Terminator to those ports.

What do you think?

[sequoiap]

I would almost prefer an explicit expose rather than one that relies on the implicit insertion order, something like:

ckt.expose([c1.o(0), c1.o(1), c2.o(3), c2.o(4)])

# or

ckt.expose(c1.o(0))
ckt.expose(c1.o(1))
...

(We can support both simultaneously.)

Doing something like ckt.expose([1,3,2,0]) requires you to go back and look through the circuit to know what's going on and which ports those are. Doing something like the snippet above immediately tells you which ports are from which components, and in which order.

Thoughts?