Look at https://lizerengeorge.com/posts/2025/04/vlsi-design-chain-2/ for an example on how to use OpenTimer from the OpenRoad project to perform static timing analysis on a verilog design.
Look at https://lizerengeorge.com/posts/2025/04/vlsi-design-chain-2/ for an example on how to use OpenTimer from the OpenRoad project to perform static timing analysis on a verilog design.