Clock tracing through gf180mcu clkbuf cells rejects power-pin inputs as multi-input drivers

[robtaylor]

Summary

After #64 made power-pin names (VDD / VSS / VNW / VPW / DVDD / DVSS / etc.) resolve to Direction::I via the new short-circuit in GF180MCULeafPins::direction_of, the AIG clock-tracing path enumerates all input pins of a clock-buffer cell and treats anything with > 1 input as "multi-input ⇒ clock-gating detected, give up." Power pins now count as inputs by that rule, so every clkbuf in the design (4+ ports: I, VDD, VSS, plus VPW/VNW on 9t cells) trips the check.

Surfaces on any post-P&R GF180MCU netlist with a real clock tree — not specific to designs that include SRAM, IO pads, or anything else that #64 was reaching for.

Repro

jacquard sim against any post-P&R gf180mcu-project-template netlist (LibreLane 3.0 default flow). Panic emerges at AIG construction time, after clock tracing starts:

[INFO]  Starting clock tracing for 76783 cells...
[INFO]    Processing seq cell 1 (gf180mcu_fd_sc_mcu9t5v0__dffsnq_1): _26303_
[INFO]      Tracing clock pin 216583 for cell 70492...
[ERROR]   input pin VDD unexpected for ck element gf180mcu_fd_sc_mcu9t5v0__clkbuf_8

thread 'main' panicked at src/aig.rs:1919:21:
Tracing clock pin of cell _26303_ error: there is a multi-input cell driving
clkbuf_leaf_98_clk_PAD2CORE_regs:VDD that clocks this sequential element.
Clock gating need to be manually patched atm.

The clkbuf's signal path is genuinely single-input (I → Z); the spurious extra "inputs" are VDD/VSS, which the clock-tracing pass should treat as inert.

Where the gap is

src/aig.rs:560-595 (the clock-buffer / inverter recognition block under PdkVariant::Gf180Mcu) correctly identifies gf180mcu_fd_sc_mcu9t5v0__clkbuf_8 as is_buf = true. The downstream pin-enumeration loop (around src/aig.rs:1912-1925) then walks the cell's input pins and finds VDD / VSS / VPW / VNW alongside I, exceeds the single-input expectation, and panics with the "multi-input cell driving …" message.

is_filler_cell already handles a similar problem for filler / corner / endcap cells by short-circuiting before the pin-direction lookup. The clock-tracing path needs the same pattern, applied to the pin enumeration side rather than the pin-direction-resolution side.

Suggested fix

In src/aig.rs, the buffer / inverter input-pin enumeration loop should skip pin names matching the power-pin set used in #64's short-circuit:

const POWER_PIN_NAMES: &[&str] = &[
    "VDD", "VSS", "VNW", "VPW", "VPB", "VNB",
    "VPWR", "VGND", "DVDD", "DVSS", "AVDD", "AVSS",
];

The same list is already implicit in GF180MCULeafPins::direction_of from #64 — pulling it into a pub const in gf180mcu_pdk.rs (or a generic is_power_pin(name: &str) -> bool helper) gives one source of truth.

The skip applies only when the cell is classified as a clock-path buffer / inverter / IO-pad-buffer (is_buf / is_inv / is_io_pad_buf); standard-cell input enumeration elsewhere in the AIG path shouldn't change behaviour, because the existing pin tables for standard cells didn't include power pins until #64 — and #64's short-circuit only handles direction resolution, not enumeration semantics.

Expected diff scope: ~5-10 lines in src/aig.rs + one shared helper in gf180mcu_pdk.rs. SKY130 is unaffected (no power-pin shortcut, doesn't trip on the same pattern), but the same shape of helper would be cleaner if applied uniformly across PdkVariants.

Compatibility

• Real intentional clock gating (where multiple genuine signal inputs converge into a clock net) still trips the existing check — the proposed skip is name-keyed, only excluding power-pin names. Behavioural equivalence for in-scope clock-gating detection.
• AIGPDK / SKY130 paths unchanged.
• GF180MCU: power-pin + wired-filler shortcuts for real post-P&R netlists #64's regression tests stay green — they test direction resolution, not clock tracing.

Adjacent

Exposed only after #68's --cell-library cleared an earlier panic at the SRAM-macro stage, letting clock tracing run for the first time on a real post-P&R chip_top. But the bug itself is purely the #64 + clock-tracing interaction — would have hit any post-P&R gf180mcu-project-template netlist regardless of whether it includes SRAM, IO bidir pads, or any other recently-enabled cell family.

Workaround: none today. Blocks post-P&R jacquard sim against any real GF180MCU chip_top with a clock tree (effectively every project-template flow output).

Environment

• Jacquard main post-GF180MCU: power-pin + wired-filler shortcuts for real post-P&R netlists #64 (commit 9281e57) and PR #68 head (7f3a3ea) — same panic.
• cargo run -r --bin jacquard -- sim (release build, default features).
• Real chip_top.pnl.v output from librelane@3.0 against gf180mcu-project-template@1.4.0.