@@ -3,7 +3,8 @@ Chip Configurator
33
44The `ChipFlow Configurator <https://configurator.chipflow.io >`_ is a web-based tool for
55designing and visualizing custom chip layouts. It provides an intuitive interface
6- for configuring IP blocks, pin assignments, and bus connections.
6+ for configuring IP blocks, pin assignments, and bus connections - then generates
7+ a complete development environment for you to build and simulate your design.
78
89.. image :: _screenshots/01-main-view.png
910 :alt: ChipFlow Configurator main view
@@ -25,14 +26,11 @@ Getting Started
2526 :alt: Template selector dropdown
2627 :width: 100%
2728
28- 3. **Explore the Chip Layout **
29+ 3. **Configure Your Design **
2930
30- The main view shows your chip layout with:
31-
32- - **Analog IP blocks ** positioned around the perimeter (shell)
33- - **Digital IP blocks ** in the center (core)
34- - **Pin assignments ** shown on the edges
35- - **Bus connections ** between IP blocks
31+ - Enable or disable IP blocks using the sidebar controls
32+ - View pin assignments on the chip edges
33+ - See bus connections between components
3634
37354. **Navigate the View **
3836
@@ -43,6 +41,58 @@ Getting Started
4341 :alt: Zoomed out view showing full chip
4442 :width: 100%
4543
44+ 5. **Generate Your Design **
45+
46+ When you're happy with your configuration, click the **Generate Design ** button.
47+ This will:
48+
49+ - Create a GitHub repository with your design
50+ - Launch a GitHub Codespace with everything pre-configured
51+ - Open a welcome page with next steps
52+
53+ Working in Your Codespace
54+ -------------------------
55+
56+ After clicking "Generate Design", you'll be taken to a GitHub Codespace with your
57+ chip design ready to build and simulate. The welcome page shows your design summary
58+ and provides the commands you need.
59+
60+ Build Your Design
61+ ^^^^^^^^^^^^^^^^^
62+
63+ Generate Verilog and compile the simulation:
64+
65+ .. code-block :: bash
66+
67+ chipflow sim build
68+
69+ Run Simulation
70+ ^^^^^^^^^^^^^^
71+
72+ Execute the simulation and see results:
73+
74+ .. code-block :: bash
75+
76+ chipflow sim run
77+
78+ Submit for Fabrication
79+ ^^^^^^^^^^^^^^^^^^^^^^
80+
81+ When your design is ready, submit it for silicon fabrication:
82+
83+ .. code-block :: bash
84+
85+ chipflow silicon submit
86+
87+ Next Steps in the Codespace
88+ ^^^^^^^^^^^^^^^^^^^^^^^^^^^
89+
90+ 1. **Build your design ** - Run ``chipflow sim build `` to generate Verilog and compile
91+ 2. **Run simulation ** - Execute ``chipflow sim run `` to test your design
92+ 3. **Explore results ** - Check generated Verilog, waveforms, and test output
93+ 4. **Iterate and refine ** - Modify your design and rebuild as needed
94+ 5. **Submit for fabrication ** - Run ``chipflow silicon submit `` when ready
95+
4696Key Features
4797------------
4898
@@ -67,22 +117,15 @@ Visual Bus Routing
67117- Toggle bus visibility in the sidebar
68118- See which blocks share common buses
69119
70- Export Designs
71- ^^^^^^^^^^^^^^
72-
73- Export your complete chip design as a JSON file containing:
74-
75- - Full configuration settings
76- - IP block positions and parameters
77- - Pin allocation details
78- - Bus connection information
120+ One-Click Development Environment
121+ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
79122
80- Click the **Export Design ** button in the sidebar to download your design.
123+ - Generates a complete GitHub repository
124+ - Pre-configured Codespace with all tools installed
125+ - Ready to build, simulate, and submit your design
81126
82- Next Steps
83- ----------
127+ Resources
128+ ---------
84129
85- - Explore different chip templates to see various configurations
86- - Try enabling/disabling IP blocks to see how pin allocation changes
87- - Export a design and examine the JSON structure
88- - Check out the :doc: `/chipflow-lib/index ` to learn how to use your design in code
130+ - `ChipFlow Documentation <https://docs.chipflow.io >`_ - Complete guides and API reference
131+ - `Report Issues <https://github.com/ChipFlow/chipflow-central/issues >`_ - Found a problem? Let us know
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