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Update configurator docs: Export Design -> Generate Design
- Replace "Export Design" with "Generate Design" workflow - Add documentation for GitHub Codespace environment - Document chipflow commands: sim build, sim run, silicon submit - Add "Working in Your Codespace" section with step-by-step guide 🤖 Generated with [Claude Code](https://claude.com/claude-code) Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
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docs/source/configurator/index.rst

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@@ -3,7 +3,8 @@ Chip Configurator
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The `ChipFlow Configurator <https://configurator.chipflow.io>`_ is a web-based tool for
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designing and visualizing custom chip layouts. It provides an intuitive interface
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for configuring IP blocks, pin assignments, and bus connections.
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for configuring IP blocks, pin assignments, and bus connections - then generates
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a complete development environment for you to build and simulate your design.
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.. image:: _screenshots/01-main-view.png
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:alt: ChipFlow Configurator main view
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:alt: Template selector dropdown
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:width: 100%
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3. **Explore the Chip Layout**
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3. **Configure Your Design**
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The main view shows your chip layout with:
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- **Analog IP blocks** positioned around the perimeter (shell)
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- **Digital IP blocks** in the center (core)
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- **Pin assignments** shown on the edges
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- **Bus connections** between IP blocks
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- Enable or disable IP blocks using the sidebar controls
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- View pin assignments on the chip edges
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- See bus connections between components
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4. **Navigate the View**
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:alt: Zoomed out view showing full chip
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:width: 100%
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5. **Generate Your Design**
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When you're happy with your configuration, click the **Generate Design** button.
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This will:
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- Create a GitHub repository with your design
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- Launch a GitHub Codespace with everything pre-configured
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- Open a welcome page with next steps
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Working in Your Codespace
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-------------------------
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After clicking "Generate Design", you'll be taken to a GitHub Codespace with your
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chip design ready to build and simulate. The welcome page shows your design summary
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and provides the commands you need.
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Build Your Design
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^^^^^^^^^^^^^^^^^
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Generate Verilog and compile the simulation:
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.. code-block:: bash
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chipflow sim build
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Run Simulation
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^^^^^^^^^^^^^^
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Execute the simulation and see results:
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.. code-block:: bash
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chipflow sim run
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Submit for Fabrication
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^^^^^^^^^^^^^^^^^^^^^^
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When your design is ready, submit it for silicon fabrication:
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.. code-block:: bash
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chipflow silicon submit
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Next Steps in the Codespace
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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1. **Build your design** - Run ``chipflow sim build`` to generate Verilog and compile
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2. **Run simulation** - Execute ``chipflow sim run`` to test your design
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3. **Explore results** - Check generated Verilog, waveforms, and test output
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4. **Iterate and refine** - Modify your design and rebuild as needed
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5. **Submit for fabrication** - Run ``chipflow silicon submit`` when ready
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Key Features
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------------
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- Toggle bus visibility in the sidebar
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- See which blocks share common buses
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Export Designs
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^^^^^^^^^^^^^^
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Export your complete chip design as a JSON file containing:
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- Full configuration settings
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- IP block positions and parameters
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- Pin allocation details
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- Bus connection information
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One-Click Development Environment
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Click the **Export Design** button in the sidebar to download your design.
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- Generates a complete GitHub repository
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- Pre-configured Codespace with all tools installed
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- Ready to build, simulate, and submit your design
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Next Steps
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----------
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Resources
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---------
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- Explore different chip templates to see various configurations
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- Try enabling/disabling IP blocks to see how pin allocation changes
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- Export a design and examine the JSON structure
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- Check out the :doc:`/chipflow-lib/index` to learn how to use your design in code
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- `ChipFlow Documentation <https://docs.chipflow.io>`_ - Complete guides and API reference
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- `Report Issues <https://github.com/ChipFlow/chipflow-central/issues>`_ - Found a problem? Let us know

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