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‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/common/index.rst.txt‎

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chipflow.common
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===============
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.. py:module:: chipflow.common
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.. autoapi-nested-parse::
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Common utilities for ChipFlow.
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‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/config_models/index.rst.txt‎

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‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/index.rst.txt‎

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/chipflow-lib/autoapi/chipflow/auth/index
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/chipflow-lib/autoapi/chipflow/auth_command/index
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/chipflow-lib/autoapi/chipflow/common/index
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/chipflow-lib/autoapi/chipflow/config/index
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/chipflow-lib/autoapi/chipflow/config_models/index
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/chipflow-lib/autoapi/chipflow/packages/index
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/chipflow-lib/autoapi/chipflow/packaging/index
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/chipflow-lib/autoapi/chipflow/platform/index
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/chipflow-lib/autoapi/chipflow/platforms/index
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/chipflow-lib/autoapi/chipflow/steps/index
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/chipflow-lib/autoapi/chipflow/utils/index
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‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/packages/index.rst.txt‎

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chipflow.packages
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=================
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.. py:module:: chipflow.packages
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.. autoapi-nested-parse::
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Package definitions for ChipFlow platforms.
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This module contains package type definitions for supported IC packages.
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‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/platform/index.rst.txt‎

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Options for an IO pad/pin.
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Attributes:
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invert: Polarity inversion. If the value is a simple :class:`bool`, it specifies inversion for
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the entire port. If the value is an iterable of :class:`bool`, the iterable must have the
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same length as the width of ``io``, and the inversion is specified for individual wires.
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individual_oe: controls whether each output wire is associated with an individual Output Enable bit
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or if a single OE bit will be used for entire port. The default value is False (indicating that a
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single OE bit controls the entire port).
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power_domain: The name of the I/O power domain. NB there is only one of these, so IO with
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multiple power domains must be split up.
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clock_domain: the name of the I/O's clock domain (see ``amaranth.hdl.ClockDomain``). NB there
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is only one of these, so IO with multiple clocks must be split up.
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invert: Polarity inversion. If the value is a simple ``bool``, it specifies
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inversion for the entire port. If the value is an iterable of ``bool``,
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the iterable must have the same length as the width of ``io``, and the
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inversion is specified for individual wires.
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individual_oe: Controls whether each output wire is associated with an
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individual Output Enable bit or if a single OE bit will be used for
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entire port. The default value is False (indicating that a single OE
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bit controls the entire port).
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power_domain: The name of the I/O power domain. NB there is only one of
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these, so IO with multiple power domains must be split up.
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clock_domain: The name of the I/O's clock domain (see
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``amaranth.hdl.ClockDomain``). NB there is only one of these, so IO
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with multiple clocks must be split up.
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buffer_in: Should the IO pad have an input buffer?
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buffer_out: Should the IO pad have an output buffer?
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sky130_drive_mode: Drive mode for output buffer on sky130.

‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/platform/io/annotate/index.rst.txt‎

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.. py:function:: submodule_metadata(fragment, component_name, recursive=False)
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Generator that finds `component_name` in `fragment` and
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then yields the ``wiring.Component``s of that component's submodule, along with their names and metadata
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Generator that finds ``component_name`` in ``fragment`` and yields metadata.
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Can only be run once for a given component (or its children)
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Yields the ``wiring.Component`` instances of that component's submodule, along
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with their names and metadata.
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If recursive = True, then name is a tuple of the heirarchy of names
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otherwise, name is the string name of the first level component
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Can only be run once for a given component (or its children).
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Args:
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fragment: The fragment to search in.
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component_name: The name of the component to find.
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recursive: If True, name is a tuple of the hierarchy of names. Otherwise,
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name is the string name of the first level component.
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Yields:
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Tuple of (component, name, metadata) for each submodule.
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‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/platform/io/index.rst.txt‎

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Options for an IO pad/pin.
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Attributes:
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invert: Polarity inversion. If the value is a simple :class:`bool`, it specifies inversion for
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the entire port. If the value is an iterable of :class:`bool`, the iterable must have the
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same length as the width of ``io``, and the inversion is specified for individual wires.
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individual_oe: controls whether each output wire is associated with an individual Output Enable bit
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or if a single OE bit will be used for entire port. The default value is False (indicating that a
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single OE bit controls the entire port).
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power_domain: The name of the I/O power domain. NB there is only one of these, so IO with
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multiple power domains must be split up.
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clock_domain: the name of the I/O's clock domain (see ``amaranth.hdl.ClockDomain``). NB there
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is only one of these, so IO with multiple clocks must be split up.
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invert: Polarity inversion. If the value is a simple ``bool``, it specifies
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inversion for the entire port. If the value is an iterable of ``bool``,
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the iterable must have the same length as the width of ``io``, and the
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inversion is specified for individual wires.
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individual_oe: Controls whether each output wire is associated with an
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individual Output Enable bit or if a single OE bit will be used for
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entire port. The default value is False (indicating that a single OE
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bit controls the entire port).
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power_domain: The name of the I/O power domain. NB there is only one of
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these, so IO with multiple power domains must be split up.
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clock_domain: The name of the I/O's clock domain (see
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``amaranth.hdl.ClockDomain``). NB there is only one of these, so IO
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with multiple clocks must be split up.
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buffer_in: Should the IO pad have an input buffer?
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buffer_out: Should the IO pad have an output buffer?
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sky130_drive_mode: Drive mode for output buffer on sky130.
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.. py:function:: submodule_metadata(fragment, component_name, recursive=False)
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Generator that finds `component_name` in `fragment` and
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then yields the ``wiring.Component``s of that component's submodule, along with their names and metadata
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Generator that finds ``component_name`` in ``fragment`` and yields metadata.
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Can only be run once for a given component (or its children)
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Yields the ``wiring.Component`` instances of that component's submodule, along
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with their names and metadata.
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If recursive = True, then name is a tuple of the heirarchy of names
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otherwise, name is the string name of the first level component
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Can only be run once for a given component (or its children).
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Args:
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fragment: The fragment to search in.
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component_name: The name of the component to find.
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recursive: If True, name is a tuple of the hierarchy of names. Otherwise,
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name is the string name of the first level component.
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Yields:
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Tuple of (component, name, metadata) for each submodule.
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‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/platform/io/iosignature/index.rst.txt‎

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Options for an IO pad/pin.
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Attributes:
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invert: Polarity inversion. If the value is a simple :class:`bool`, it specifies inversion for
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the entire port. If the value is an iterable of :class:`bool`, the iterable must have the
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same length as the width of ``io``, and the inversion is specified for individual wires.
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individual_oe: controls whether each output wire is associated with an individual Output Enable bit
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or if a single OE bit will be used for entire port. The default value is False (indicating that a
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single OE bit controls the entire port).
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power_domain: The name of the I/O power domain. NB there is only one of these, so IO with
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multiple power domains must be split up.
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clock_domain: the name of the I/O's clock domain (see ``amaranth.hdl.ClockDomain``). NB there
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is only one of these, so IO with multiple clocks must be split up.
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invert: Polarity inversion. If the value is a simple ``bool``, it specifies
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inversion for the entire port. If the value is an iterable of ``bool``,
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the iterable must have the same length as the width of ``io``, and the
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inversion is specified for individual wires.
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individual_oe: Controls whether each output wire is associated with an
60+
individual Output Enable bit or if a single OE bit will be used for
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entire port. The default value is False (indicating that a single OE
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bit controls the entire port).
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power_domain: The name of the I/O power domain. NB there is only one of
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these, so IO with multiple power domains must be split up.
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clock_domain: The name of the I/O's clock domain (see
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``amaranth.hdl.ClockDomain``). NB there is only one of these, so IO
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with multiple clocks must be split up.
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buffer_in: Should the IO pad have an input buffer?
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buffer_out: Should the IO pad have an output buffer?
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sky130_drive_mode: Drive mode for output buffer on sky130.

‎pr-preview/pr-15/_sources/chipflow-lib/autoapi/chipflow/platform/io/signatures/index.rst.txt‎

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Bases: :py:obj:`typing_extensions.TypedDict`
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dict() -> new empty dictionary
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dict(mapping) -> new dictionary initialized from a mapping object's
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(key, value) pairs
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dict(iterable) -> new dictionary initialized as if via:
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d = {}
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for k, v in iterable:
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d[k] = v
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dict(**kwargs) -> new dictionary initialized with the name=value pairs
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in the keyword argument list. For example: dict(one=1, two=2)
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Simulation interface metadata for ChipFlow components.
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Attributes:
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uid: Unique identifier for the interface.
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parameters: List of (name, value) tuples for interface parameters.
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.. py:class:: DataclassProtocol
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Bases: :py:obj:`typing_extensions.TypedDict`, :py:obj:`Generic`\ [\ :py:obj:`_T_DataClass`\ ]
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dict() -> new empty dictionary
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dict(mapping) -> new dictionary initialized from a mapping object's
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(key, value) pairs
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dict(iterable) -> new dictionary initialized as if via:
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d = {}
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for k, v in iterable:
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d[k] = v
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dict(**kwargs) -> new dictionary initialized with the name=value pairs
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in the keyword argument list. For example: dict(one=1, two=2)
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Container for data associated with a ChipFlow component.
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Attributes:
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data: The dataclass instance containing component data.
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.. py:class:: DriverModel

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