|
| 1 | +Chip Configurator |
| 2 | +================= |
| 3 | + |
| 4 | +The `ChipFlow Configurator <https://configurator.chipflow.io>`_ is a web-based tool for |
| 5 | +designing and visualizing custom chip layouts. It provides an intuitive interface |
| 6 | +for configuring IP blocks, pin assignments, and bus connections - then generates |
| 7 | +a complete development environment for you to build and simulate your design. |
| 8 | + |
| 9 | +.. image:: _screenshots/01-main-view.png |
| 10 | + :alt: ChipFlow Configurator main view |
| 11 | + :width: 100% |
| 12 | + |
| 13 | +Getting Started |
| 14 | +--------------- |
| 15 | + |
| 16 | +1. **Open the Configurator** |
| 17 | + |
| 18 | + Visit `configurator.chipflow.io <https://configurator.chipflow.io>`_ in your browser. |
| 19 | + |
| 20 | +2. **Select a Template** |
| 21 | + |
| 22 | + Use the dropdown selector to choose a chip template. Templates define the chip's |
| 23 | + pin count, available IP blocks, and layout constraints. |
| 24 | + |
| 25 | + .. image:: _screenshots/03-config-selector.png |
| 26 | + :alt: Template selector dropdown |
| 27 | + :width: 100% |
| 28 | + |
| 29 | +3. **Configure Your Design** |
| 30 | + |
| 31 | + - Enable or disable IP blocks using the sidebar controls |
| 32 | + - View pin assignments on the chip edges |
| 33 | + - See bus connections between components |
| 34 | + |
| 35 | +4. **Navigate the View** |
| 36 | + |
| 37 | + - **Pan**: Click and drag to move around |
| 38 | + - **Zoom**: Use mouse wheel or pinch gestures to zoom in/out |
| 39 | + |
| 40 | + .. image:: _screenshots/04-zoomed-out.png |
| 41 | + :alt: Zoomed out view showing full chip |
| 42 | + :width: 100% |
| 43 | + |
| 44 | +5. **Generate Your Design** |
| 45 | + |
| 46 | + When you're happy with your configuration, click the **Generate Design** button. |
| 47 | + This will: |
| 48 | + |
| 49 | + - Create a GitHub repository with your design |
| 50 | + - Launch a GitHub Codespace with everything pre-configured |
| 51 | + - Open a welcome page with next steps |
| 52 | + |
| 53 | +Working in Your Codespace |
| 54 | +------------------------- |
| 55 | + |
| 56 | +After clicking "Generate Design", you'll be taken to a GitHub Codespace with your |
| 57 | +chip design ready to build and simulate. The welcome page shows your design summary |
| 58 | +and provides the commands you need. |
| 59 | + |
| 60 | +Build Your Design |
| 61 | +^^^^^^^^^^^^^^^^^ |
| 62 | + |
| 63 | +Generate Verilog and compile the simulation: |
| 64 | + |
| 65 | +.. code-block:: bash |
| 66 | +
|
| 67 | + chipflow sim build |
| 68 | +
|
| 69 | +Run Simulation |
| 70 | +^^^^^^^^^^^^^^ |
| 71 | + |
| 72 | +Execute the simulation and see results: |
| 73 | + |
| 74 | +.. code-block:: bash |
| 75 | +
|
| 76 | + chipflow sim run |
| 77 | +
|
| 78 | +Submit for Fabrication |
| 79 | +^^^^^^^^^^^^^^^^^^^^^^ |
| 80 | + |
| 81 | +When your design is ready, submit it for silicon fabrication: |
| 82 | + |
| 83 | +.. code-block:: bash |
| 84 | +
|
| 85 | + chipflow silicon submit |
| 86 | +
|
| 87 | +Next Steps in the Codespace |
| 88 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 89 | + |
| 90 | +1. **Build your design** - Run ``chipflow sim build`` to generate Verilog and compile |
| 91 | +2. **Run simulation** - Execute ``chipflow sim run`` to test your design |
| 92 | +3. **Explore results** - Check generated Verilog, waveforms, and test output |
| 93 | +4. **Iterate and refine** - Modify your design and rebuild as needed |
| 94 | +5. **Submit for fabrication** - Run ``chipflow silicon submit`` when ready |
| 95 | + |
| 96 | +Key Features |
| 97 | +------------ |
| 98 | + |
| 99 | +Interactive Layout |
| 100 | +^^^^^^^^^^^^^^^^^^ |
| 101 | + |
| 102 | +- Drag, zoom, and pan the chip visualization |
| 103 | +- Click on IP blocks to see their details |
| 104 | +- Real-time updates as you make changes |
| 105 | + |
| 106 | +Configurable IP Blocks |
| 107 | +^^^^^^^^^^^^^^^^^^^^^^ |
| 108 | + |
| 109 | +- Enable or disable individual IP blocks |
| 110 | +- Scale and customize IP block parameters |
| 111 | +- View pin assignments and signal mappings |
| 112 | + |
| 113 | +Visual Bus Routing |
| 114 | +^^^^^^^^^^^^^^^^^^ |
| 115 | + |
| 116 | +- Color-coded connections between components |
| 117 | +- Toggle bus visibility in the sidebar |
| 118 | +- See which blocks share common buses |
| 119 | + |
| 120 | +One-Click Development Environment |
| 121 | +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 122 | + |
| 123 | +- Generates a complete GitHub repository |
| 124 | +- Pre-configured Codespace with all tools installed |
| 125 | +- Ready to build, simulate, and submit your design |
| 126 | + |
| 127 | +Resources |
| 128 | +--------- |
| 129 | + |
| 130 | +- `ChipFlow Documentation <https://docs.chipflow.io>`_ - Complete guides and API reference |
| 131 | +- `Report Issues <https://github.com/ChipFlow/chipflow-central/issues>`_ - Found a problem? Let us know |
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