Feature Request: Automatically generate Testbenches for FSMs (iVerilog / GHDL / Maybe C?)

[swittlich]

Currently, the plugin provides an excellent graphical FSM editor for Oneware Studio and automatically generates the FSM code. However, verifying the correctness of the generated FSM requires writing testbenches manually. This can be time-consuming and prone to human error, especially for large state machines.

Describe the solution you'd like

I would like the plugin/backend to automatically generate a basic testbench skeleton for each generated FSM. The testbench format should dynamically match the selected target output format:

• If the output format is Verilog, it should generate a testbench compatible with iVerilog.
• If the output format is VHDL, it should generate a testbench compatible with GHDL.

Ideally, this testbench should:

1. Instantiate the generated FSM module (DUT - Device Under Test).
2. Set up a default clock and reset signal generation block.
3. Provide a placeholder or a simple sequence of state transitions where the user can easily add their stimulus.
4. Be automatically added to the Oneware Studio project hierarchy alongside the generated FSM code.

Additional context

Since Oneware Studio supports both VHDL and Verilog workflows and uses tools like GHDL and iVerilog for simulation, having an automated testbench generation feature tightly integrated with the graphical FSM editor would drastically improve the HDL development and verification workflow.