forked from ics-jku/goldcrest-microcode-verification
-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathmicrocode.sl
More file actions
370 lines (349 loc) · 8.62 KB
/
microcode.sl
File metadata and controls
370 lines (349 loc) · 8.62 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
! Compliant
# ============================================================
# ARITHMETIC
# ============================================================
@ADD
@ADDI
@LUI
TMP0
IMMI TMP0 # negate IMMI | TMP0 - IMMI = 0 - mem[IMMI]
NEXT RVPC # increment RISC-V pc
TMP0 SRC1 END # SRC2 - -(TMP0)
@SUB
NEXT RVPC # increment RISC-V pc
IMMI SRC1 END
@AUIPC
TMP0
SRC2
RVPC TMP0 # copy RVPC to SRC2
TMP0 SRC2
TMP0 # RVPC + IMMI
IMMI TMP0
NEXT RVPC
TMP0 SRC2 END
# ============================================================
# JUMPS
# ============================================================
@LB
@LH
@LW
@LBU
@LHU
@SB
@SH
@SW
TMP0
IMMI TMP0 # negate IMMI | TMP0 - IMMI = 0 - mem[IMMI]
NEXT RVPC # increment RISC-V pc
TMP0 SRC1 END # SRC1 - -(TMP0)
# ============================================================
# JUMPS
# ============================================================
@JAL
TMP0
TMP1
SRC2 # reset SRC2
IMMI TMP0 # negate IMMI
RVPC TMP1 # -pc => TMP1
TMP0 RVPC # RVPC - -TMP0
TMP1 SRC2 # pc => SRC2
NEXT SRC2 END # add link address +4
@JALR
TMP0 # reset TMP0
TMP1 # reset TMP1
TMP2 # reset TMP2
TMP3 # reset TMP3
SRC1 TMP1 # -SRC2 => TMP1 calculate jump target
TMP1 IMMI # IMMI --(SRC2)
TMP1 # reset TMP1 set new pc after jump
jalr-prep:
WORD TMP0
INCR TMP0
IMMI TMP3 # save IMMI
jalr-loop:
TMP2
IMMI TMP2
TMP2 IMMI
INCR TMP0 jalr-loop
TMP0
IMMI TMP0 jalr-fin
INCR TMP3
jalr-fin:
IMMI
TMP3 IMMI
IMMI TMP1 # -(SRC2 + IMMI) => TMP1
NEXT RVPC # RVPC + 4
TMP0
RVPC TMP0 # -(RVPC + 4) store link pc
RVPC # reset RVPC
TMP1 RVPC # (SRC2 + IMMI) => RVPC
SRC1 # reset SRC2
TMP0 SRC1 END # (RVPC + 4) => SRC2
# ============================================================
# BRANCHES
# ============================================================
@BEQ
beq:
TMP0
TMP1
SRC1 TMP0 # copy SRC2 to TMP1
TMP0 TMP1
beq-check-one:
SRC2 SRC1 beq-check-two
TMP0 TMP0 beq-no-jump-two # NO
beq-check-two:
TMP1 SRC2 beq-jump # test if SRC1 <= SRC2
beq-no-jump-two:
NEXT RVPC END # goto next instruction
beq-jump:
TMP0
IMMI TMP0 # YES
TMP0 RVPC END # pc + B_imm
@BNE
bne:
TMP0
TMP1
SRC1 TMP0 # copy SRC2 to TMP1
TMP0 TMP1
SRC2 SRC1 bne-check-two # test if SRC2 <= SRC1
TMP0 TMP0 bne-jump
bne-check-two:
TMP1 SRC2 bne-no-jump # test if SRC1 <= SRC2
bne-jump:
TMP2
IMMI TMP2
TMP2 RVPC END
bne-no-jump:
NEXT RVPC END
@BLTU
TMP0
TMP1
SRC2 TMP0 bltu-one-small # check if SRC1 >= 0
SRC1 TMP1 blt-jump # check if SRC2 >= 0, if so then perform jump because SRC2 < SRC1
TMP1 TMP1 blt # now do normal blt instruction
bltu-one-small:
SRC1 TMP1 blt # check if SRC2 >= 0, if not then perform no jump
TMP1 TMP1 blt-no-jump # SRC2 > SRC1
@BLT # 68 // 1000100
blt:
# check src2 <= src1
SRC1 SRC2 blt-no-jump
blt-jump:
TMP0
# no jump src2 >= src1
IMMI TMP0
TMP0 RVPC END
blt-no-jump:
# src1 < src2 jump
NEXT RVPC END
@BGEU
TMP0
TMP1
SRC2 TMP0 bgeu-one-small # check if SRC1 >= 0
SRC1 TMP1 bge-no-jump # check if SRC2 >= 0, if so then perform no jump because SRC2 < SRC1
TMP1 TMP1 bge # now do normal blt instruction
bgeu-one-small:
SRC1 TMP1 bge # check if SRC2 >= 0, if not then perform jump
TMP1 TMP1 bge-jump # SRC2 > SRC1
@BGE
bge:
# check src2 <= src1
SRC1 SRC2 bge-jump
bge-no-jump:
# no jump src2 >= src1
NEXT RVPC END
bge-jump:
# src1 < src2 jump
TMP0
IMMI TMP0
TMP0 RVPC END
# ============================================================
# BIT LOGIC
# ============================================================
@XORI
@XOR
TMP2
WORD TMP2
TMP1 TMP1 xor-get-msb-src-one
xor-loop:
TMP0
TMP1 TMP0
TMP0 TMP1
xor-get-msb-src-one:
TMP0
SRC1 TMP0 xor-must-be-one
xor-must-be-zero:
TMP0
IMMI TMP0 xor-set-bit
TMP0 TMP0 xor-shift-two
xor-must-be-one:
TMP0
IMMI TMP0 xor-shift
xor-set-bit:
INCR TMP1
xor-shift:
TMP0
xor-shift-two:
SRC1 TMP0
TMP0 SRC1
TMP0
IMMI TMP0
TMP0 IMMI
INCR TMP2 xor-loop
xor-clean:
NEXT RVPC
TMP0
TMP0 TMP1 END
@ORI
@OR
TMP2
WORD TMP2
TMP1 TMP1 or-get-msb-src-two
or-loop:
TMP0
TMP1 TMP0
TMP0 TMP1
or-get-msb-src-two:
TMP0
SRC1 TMP0 or-get-msb-immi
or-set-bit:
INCR TMP1
TMP0 TMP0 or-shift-two
or-get-msb-immi:
TMP0
IMMI TMP0 or-shift
or-set-bit-two:
INCR TMP1
or-shift:
TMP0
or-shift-two:
SRC1 TMP0
TMP0 SRC1
TMP0
IMMI TMP0
TMP0 IMMI
INCR TMP2 or-loop
or-clean:
NEXT RVPC
TMP0
TMP0 TMP1 END
@ANDI
@AND
TMP2
WORD TMP2
TMP1 TMP1 and-get-msb-src-two
and-loop:
TMP0
TMP1 TMP0
TMP0 TMP1
and-get-msb-src-two:
TMP0
SRC1 TMP0 and-shift
and-get-msb-immi:
TMP0
IMMI TMP0 and-shift
and-set-bit:
INCR TMP1
and-shift:
TMP0
SRC1 TMP0
TMP0 SRC1
TMP0
IMMI TMP0
TMP0 IMMI
INCR TMP2 and-loop
and-clean:
NEXT RVPC
TMP0
TMP0 TMP1 END
# ============================================================
# SHIFTING
# ============================================================
@SLLI
@SLL
TMP0
TMP1
SRC1 TMP1
SRC1
IMMI TMP0 sll-check # -IMMI -> TMP0
sll-loop:
TMP1 SRC1 # SRC2 + SRC2
TMP1 # reset TMP1
SRC1 TMP1 # negate shift value
sll-check:
INCR TMP0 sll-loop # loop
sll-clean:
NEXT RVPC # next RISC-V
TMP1 SRC1 END # SRC2 + SRC2
@SRAI
@SRA
TMP0
SRC2
SRC1 TMP0 sra-is-pos
sra-is-neg: # set SRC2 to -1 to sign extend
CONE SRC2
TMP0 TMP0 srl
sra-is-pos:
@SRLI
@SRL
srl-setup:
TMP0
SRC2
srl:
TMP5
WORD TMP5
IMMI TMP0
TMP0 TMP5
srl-msb-check:
TMP0
SRC1 TMP0 srl-msb-unset
srl-msb-set:
TMP0
SRC2 TMP0 # SRC2 <<1
TMP0 SRC2 # SRC2 <<1
INCR SRC2 # set bit of SRC2
TMP0 TMP0 srl-check-loop
srl-msb-unset:
TMP0
SRC2 TMP0 # SRC2 <<1
TMP0 SRC2 # SRC2 <<1
srl-check-loop:
TMP0
TMP5 TMP0 srl-end
srl-move-op:
TMP0
SRC1 TMP0
TMP0 SRC1
INCR TMP5
TMP0 TMP0 srl-msb-check
srl-end:
NEXT RVPC
TMP0
TMP0 SRC2 END
# ============================================================
# SET BIT
# ============================================================
@SLTIU
@SLTU
TMP0
TMP1
IMMI TMP0 sltu-one-small # check if IMMI >= 0
TMP0
SRC1 TMP0 slt-set # check if SRC2 >= 0, if so then perform jump because SRC2 < SRC1
TMP0 TMP0 slt-check-one # now do normal blt instruction
sltu-one-small:
TMP0
SRC1 TMP0 slt-check-one # check if SRC2 >= 0, if not then perform no jump
TMP0 TMP0 slt-no-set # SRC2 > SRC1
@SLTI
@SLT
slt:
TMP1
slt-check-one:
SRC1 IMMI slt-no-set
slt-set:
CONE TMP1
slt-no-set:
TMP0
NEXT RVPC
TMP1 TMP0 END