Summary
Cadence Allegro computes per-net electrical characteristics (impedance, capacitance, inductance, resistance, propagation delay) from the routed layout combined with the stackup dielectric/conductor properties. These values are stored in the .brd database and can be exported programmatically using the extracta batch utility and predefined view files.
This data is distinct from design constraints (.tcfx) — it represents as-routed physical measurements, not design intent. It is valuable for post-route signal integrity analysis, impedance verification, and electrical sign-off.
This document covers everything needed to implement a tool that extracts this data: the CLI commands, the view file format, and the output file structure — all verified against a production Allegro 23.1 board.
Highest-value view file: net_bv.txt — Of the ~120 view files shipped with Cadence, net_bv.txt is the single most important for PCB Lens. It is the only view that produces data completely unavailable in either IPC-2581 exports or .tcfx constraint files: per-net post-route capacitance, inductance, resistance, impedance (min/avg/max), and propagation delay. All other view files (layer, stackup, component, etc.) produce data that is redundant with IPC-2581 or .tcfx. If only one extracta view is ever supported, it should be net_bv.txt.
Part 1: The extracta Utility
Location
<CADENCE_INSTALL>\tools\bin\extracta.exe
Example: C:\Cadence\SPB_23.1\tools\bin\extracta.exe
This is in the same tools\bin\ directory as a2ipc2581.exe and techfile.exe.
A companion tool extracta_compiler.exe also exists at the same path (used internally for view file compilation — not needed for basic extraction).
Environment Setup
Before calling extracta.exe, initialize the Cadence environment:
call <CADENCE_INSTALL>\tools\bin\allegro_cmd.bat
This is the same setup used for a2ipc2581.exe and techfile.exe.
Command Syntax
extracta <flags> <input.brd> <view_file.txt> <output.txt>
Verified flags:
| Flag |
Purpose |
-q |
Quiet mode — suppresses interactive prompts |
-s |
Suppress summary popup window |
Both flags should always be used together for headless/automated operation.
All valid flag characters: [aPlcdgkmnpqrstwzAX+]
There is no -h or --help flag — passing -h produces: Switch 'h' is invalid.
Full Example
call C:\Cadence\SPB_23.1\tools\bin\allegro_cmd.bat
extracta -q -s "C:\designs\my_project\PCB\my_design.brd" "C:\Cadence\SPB_23.1\share\pcb\text\views\net_bv.txt" "C:\designs\my_project\PCB\net_electrical_data.txt"
Expected Console Output
ERROR (LMF-10025): License call failed for feature Allegro_performance ...
This license warning is non-fatal — the export completes successfully despite it. It is the same warning seen with a2ipc2581.exe and techfile.exe. There is no other console output on success — the tool writes silently to the output file.
Execution Time
3–10 seconds depending on design complexity and net count. Slower than techfile because extracta loads the full Allegro database engine to compute/read electrical values.
License Requirements
Same Allegro license as the IPC-2581 exporter. Same serialization / queuing strategy should be applied.
Part 2: View Files
What They Are
View files are plain-text configuration files that tell extracta which database fields to export and in what order. They are the "schema" for the output.
Location
Cadence ships ~120 predefined view files in:
<CADENCE_INSTALL>\share\pcb\text\views\
View File Syntax
#
# Comment lines start with #
#
DATABASE_VIEW_NAME
FIELD_NAME_1
FIELD_NAME_2
# COMMENTED_OUT_FIELD <-- not exported
FIELD_NAME_3
END
- The first non-comment, non-blank line is the database view selector (e.g.,
LAYER, NET)
- Each uncommented line between the view name and
END is a field name to export
- Fields are exported in the order listed
- Commenting out a field (
#) excludes it from output
- Custom view files can be created by copying and editing these templates
Relevant View Files for Electrical Data
🔑 net_bv.txt is the #1 priority. It is the only extracta view that produces data not available from any other export path (IPC-2581 or .tcfx). The layer/stackup views below are included for completeness but their data overlaps heavily with the .tcfx stackup section.
net_bv.txt — Per-Net Electrical Measurements ⭐ HIGHEST VALUE
#
# net_baseview - basic fields for the NET view minus many of the properties
#
NET
NET_NAME_SORT
NET_NAME
NET_STATUS
NET_CAPACITANCE
NET_ETCH_LENGTH
NET_ETCH_WIDTH_AVERAGE
NET_IMPEDANCE_AVERAGE
NET_IMPEDANCE_MAXIMUM
NET_IMPEDANCE_MINIMUM
NET_INDUCTANCE
NET_MANHATTEN_LENGTH
NET_PATH_LENGTH
NET_PROPAGATION_DELAY_ACTUAL
NET_RESISTANCE
NET_VIA_COUNT
NET_ECL
NET_ELECTRICAL_CONSTRAINT_SET
NET_FIXED
NET_LOGICAL_PATH
NET_NO_RAT
NET_NO_RIPUP
NET_NO_ROUTE
NET_NO_TEST
NET_PHYSICAL_TYPE
NET_PROBE_NUMBER
NET_RATSNEST_SCHEDULE
NET_ROUTE_PRIORITY
NET_ROUTE_TO_SHAPE
NET_SAME_NET
NET_SCHEDULE
NET_SPACING_TYPE
NET_WEIGHT
END
layer_bv.txt — Layer Stackup Properties (Primary Stackup Only)
#
# layer_baseview - basic fields for the LAYER view
#
LAYER
LAYER_SORT
LAYER_SUBCLASS
LAYER_ARTWORK
LAYER_USE
LAYER_CONDUCTOR
LAYER_DIELECTRIC_CONSTANT
LAYER_ELECTRICAL_CONDUCTIVITY
LAYER_MATERIAL
LAYER_FILLIN_MATERIAL
LAYER_SHIELD_LAYER
LAYER_THERMAL_CONDUCTIVITY
LAYER_THICKNESS
LAYER_TYPE
LAYER_FUNCTION_TYPE
LAYER_LOSS_TANGENT
LAYER_FREQUENCY_DEPENDENT_FILE
LAYER_EMBEDDED_STATUS
LAYER_ETCH_FACTOR
# LAYER_STACKUP_NAME <-- uncomment for multi-region designs
# LAYER_STACKUP_TYPE
END
Important: With LAYER_STACKUP_NAME commented out, only the PRIMARY stackup layers are exported. To get all stackup regions, use multi_stackup_bv.txt instead (see below).
multi_stackup_bv.txt — Multi-Region Layer Stackup
#
# multi-layer_stackup_baseview - basic fields for the LAYER view for multi-zone designs
#
LAYER
LAYER_SORT
LAYER_STACKUP_NAME
LAYER_STACKUP_TYPE
LAYER_SUBCLASS
LAYER_CONDUCTOR
LAYER_MATERIAL
LAYER_FILLIN_MATERIAL
LAYER_THICKNESS
LAYER_FUNCTION_TYPE
END
When LAYER_STACKUP_NAME is included, extracta outputs one record per layer per stackup region. This is essential for multi-region flex/rigid-flex designs where different areas have different layer counts.
stackups_bv.txt — Stackup Region Summary
#
# stackups_baseview - basic fields for the LAYER view to give layer stackup info only
#
LAYER
LAYER_STACKUP_NAME
LAYER_STACKUP_POSITION
LAYER_STACKUP_TYPE
LAYER_SORT
END
Outputs one record per stackup region (not per layer) — just the region names, types, and positions.
Part 3: Output File Format
General Characteristics
- Encoding: Plain text, no BOM
- Delimiter: Space-separated positional fields (NOT CSV, NOT TSV)
- Header row: None — field order must be inferred from the view file
- Quoting: None — no quoting of any fields, ever
- Empty fields: Appear as consecutive spaces
- Line terminator: CRLF on Windows
- One record per line
Parsing Challenges
Material names contain spaces. This is the biggest parsing issue. Examples from verified output:
TAIFLEX FHB0525L311BT4(BLACK)
FLEX BASE(PI)
TAIYOINK-PSR-9000 FLX81EM
PLATED_COPPER_FOIL
ADHESIVE_EPOXY
Since the output has no quoting and uses spaces as delimiters, naive split(" ") parsing will break on multi-word material names. A positional/column-width parser or field-count-aware parser is needed.
Units are inline. Numeric values include their unit as a separate space-delimited token:
0.393701 mil
596000 mho/cm
0.27 pF
111.54 ohms
3.15 nH
0.00843 ns
39.61 mohms
Verified Output: net_bv.txt
One row per net. Fields in order (matching the view file):
| Position |
Field |
Example |
Unit |
| 1 |
Net name (sort key) |
SHORT_70_ |
— |
| 2 |
Net name sort index |
00000030 |
— |
| 3 |
Net name |
SHORT_70_30 |
— |
| 4 |
Net status |
REGULAR |
— |
| 5–6 |
Capacitance |
0.27 pF |
picofarads |
| 7 |
Etch length |
1.0600 |
mm (design units) |
| 8 |
Average etch width |
0.1346 |
mm |
| 9–10 |
Average impedance |
111.54 ohms |
ohms |
| 11–12 |
Maximum impedance |
161.35 ohms |
ohms |
| 13–14 |
Minimum impedance |
96.69 ohms |
ohms |
| 15–16 |
Inductance |
3.15 nH |
nanohenries |
| 17 |
Manhattan length |
1.0715 |
mm |
| 18 |
Path length |
1.0600 |
mm |
| 19–20 |
Propagation delay |
0.00843 ns |
nanoseconds |
| 21–22 |
Resistance |
39.61 mohms |
milliohms |
| 23 |
Via count |
8 |
— |
| 24+ |
Schematic logical path |
@\design_name\.\schematic\(sch_1):net_name |
— |
Full example row:
SHORT_70_ 00000030 SHORT_70_30 REGULAR 0.27 pF 1.0600 0.1346 111.54 ohms 161.35 ohms 96.69 ohms 3.15 nH 1.0715 1.0600 0.00843 ns 39.61 mohms 8 @\sc-XXXXXXX-01.a_design_name\.\sc-XXXXXXX-01.a\(sch_1):short_70_30
Observed record count: One row per routed net. Unrouted nets may not appear or may show zero-valued fields. A test design with 155 nets produced 31 rows — only nets with routed copper had records.
Verified Output: multi_stackup_bv.txt
One row per layer per stackup region. Fields in order:
| Position |
Field |
Example |
| 1 |
Sort key |
000003 |
| 2 |
Stackup region name |
PRIMARY |
| 3 |
Stackup type |
RIGID |
| 4 |
Layer subclass name |
TOP (blank for dielectrics) |
| 5 |
Conductor? |
YES / NO |
| 6 |
Material |
PLATED_COPPER_FOIL |
| 7 |
Thickness + unit |
0.393701 mil |
| 8 |
Function type |
CONDUCTOR / DIELECTRIC / DIELECTRIC_COVERLAY / SOLDER_MASK / SURFACE / CONDUCTIVE_FOIL / DIELECTRIC_BASE / DIELECTRIC_PREPREG |
Sort key encoding: The thousands digit groups records by stackup region (000xxx = region 0, 003xxx = region 1, 005xxx = region 2, etc.). Within each group, the ones digits give the layer order from top to bottom in the cross-section.
Full example rows:
000000 PRIMARY RIGID NO AIR 0 mil SURFACE
000001 PRIMARY RIGID COVERLAY_TOP NO TAIFLEX FHB0525L311BT4(BLACK) 0.984252 mil DIELECTRIC_COVERLAY
000003 PRIMARY RIGID TOP YES PLATED_COPPER_FOIL 0.393701 mil CONDUCTOR
000004 PRIMARY RIGID NO POLYIMIDE 0.511811 mil DIELECTRIC
000006 PRIMARY RIGID L2 YES COPPER 0.393701 mil CONDUCTOR
...
009000 3L RIGID NO AIR 0 mil SURFACE
009003 3L RIGID L2 YES COPPER 0.393701 mil CONDUCTOR
009005 3L RIGID L3 YES COPPER 0.393701 mil CONDUCTOR
009008 3L RIGID L4 YES COPPER 0.393701 mil CONDUCTOR
Observed record count: A design with 5 stackup regions and 18 layers in the primary stackup produced 87 rows total.
Verified Output: layer_bv.txt
One row per layer in the PRIMARY stackup only. Fields in order:
| Position |
Field |
Example |
| 1 |
Sort key |
000003 |
| 2 |
Layer subclass name |
TOP (blank for dielectrics) |
| 3 |
Artwork type |
POSITIVE (blank for non-conductor) |
| 4 |
Conductor? |
YES / NO |
| 5 |
Dielectric constant (Dk) |
4.500000 |
| 6–7 |
Electrical conductivity |
343000 mho/cm |
| 8 |
Material |
PLATED_COPPER_FOIL |
| 9 |
Fill-in material |
(blank or material name) |
| 10 |
Shield layer? |
NO |
| 11–12 |
Thickness |
0.393701 mil |
| 13 |
Layer type |
CONDUCTOR / DIELECTRIC / MASK / SURFACE |
| 14 |
Function type |
CONDUCTOR / DIELECTRIC / DIELECTRIC_COVERLAY / SURFACE / etc. |
| 15 |
Loss tangent |
0.035 |
| 16 |
Embedded status |
NOT_EMBEDDED (blank for non-conductors) |
| 17 |
Etch factor |
90.000 (blank for non-conductors) |
Full example rows:
000000 NO 1.000000 0 mho/cm AIR NO 0 mil SURFACE SURFACE 0 0.000
000001 COVERLAY_TOP NO 4.300000 0 mho/cm TAIFLEX FHB0525L311BT4(BLACK) NO 0.984252 mil MASK DIELECTRIC_COVERLAY 0.035 0.000
000003 TOP POSITIVE YES 4.500000 343000 mho/cm PLATED_COPPER_FOIL NO 0.393701 mil CONDUCTOR CONDUCTOR 0 NOT_EMBEDDED 90.000
000006 L2 POSITIVE YES 1.000000 596000 mho/cm COPPER NO 0.393701 mil CONDUCTOR CONDUCTOR 0 NOT_EMBEDDED 90.000
Observed record count: 18 rows for a 5-layer flex (5 conductors + dielectrics + coverlays + surfaces).
Part 4: How the Electrical Values Are Computed
The values in the net_bv.txt output are not raw measurements — they are computed by Allegro's built-in analysis engine from the routed layout geometry combined with stackup properties. Understanding this is important for interpreting the data correctly.
| Field |
How Allegro Computes It |
| Capacitance |
2D/2.5D field-solver model. Uses routed trace geometry (width, length, spacing to adjacent copper) combined with stackup dielectric properties (Dk, thickness) from the cross-section. Sums distributed capacitance of each trace segment to its reference plane(s), including fringing field corrections. |
| Inductance |
Same field-solver approach. Models the magnetic loop formed by the trace and its return path (reference plane). Computes partial inductance per segment from trace geometry and spacing to the return plane, then sums across the net. |
| Resistance |
DC resistance: R = ρ · L / (W · t) where ρ is resistivity (from CDS_LAYER_ELECTRICAL_CONDUCTIVITY in the stackup), L is etch length, W is trace width, t is copper thickness. Via barrel resistance is added per via. |
| Impedance (min/avg/max) |
Characteristic impedance Z₀ = √(L/C) per unit length. The min/max/avg reflects variation along the net as trace width and reference plane spacing change (e.g., a trace crossing from a 5L region to a 3L region, or necking down near a via). |
| Propagation delay |
t_pd = √(LC) per unit length × total etch length. Depends directly on the stackup Dk values — higher Dk means slower propagation. |
These values are post-route — they are stored/updated in the .brd database after routing and DRC. They reflect the as-routed physical reality, not design intent (constraints).
Part 5: Real-World Data Characteristics
Based on testing with a production Allegro 23.1 flex design:
| Metric |
Observed Value |
extracta execution time |
3–10 seconds |
net_bv.txt output size |
~7 KB for 31 nets |
multi_stackup_bv.txt output size |
~6 KB for 87 rows (5 stackup regions) |
layer_bv.txt output size |
~1.5 KB for 18 rows |
| Nets with electrical data |
Only routed nets appear (31 of 155 total) |
| Output file encoding |
Plain text, CRLF, no BOM |
Part 6: Available View Files
Cadence ships ~120 view files. The full list (filename and size) from a verified SPB 23.1 installation:
| Filename |
Size |
Description |
net_bv.txt |
682 B |
⭐ Per-net electrical data — HIGHEST VALUE. Only view with data unavailable elsewhere (post-route C/L/R/Z/tpd). If only one view is supported, it must be this one. |
layer_bv.txt |
1,510 B |
Layer stackup (primary region only) |
multi_stackup_bv.txt |
1,318 B |
Multi-region layer stackup |
stackups_bv.txt |
1,132 B |
Stackup region summary |
comp_bv.txt |
712 B |
Component data |
net_rep.txt |
457 B |
Net report |
pad_rep.txt |
760 B |
Padstack report |
pad_rep2.txt |
3,374 B |
Extended padstack report |
via_structure.txt |
255 B |
Via structure data |
drc_rep.txt |
124 B |
DRC report |
bom_rep.txt |
649 B |
BOM report |
ncdrill.txt |
1,991 B |
NC drill data |
fabmaster.txt |
3,572 B |
Fabmaster export |
analysis.txt |
1,193 B |
Analysis data |
(~106 additional view files exist for manufacturing, placement, pin, symbol, and other data — omitted for brevity.)
Custom view files can be created by copying any of these and adding/removing/commenting field names.
Summary
Cadence Allegro computes per-net electrical characteristics (impedance, capacitance, inductance, resistance, propagation delay) from the routed layout combined with the stackup dielectric/conductor properties. These values are stored in the
.brddatabase and can be exported programmatically using theextractabatch utility and predefined view files.This data is distinct from design constraints (
.tcfx) — it represents as-routed physical measurements, not design intent. It is valuable for post-route signal integrity analysis, impedance verification, and electrical sign-off.This document covers everything needed to implement a tool that extracts this data: the CLI commands, the view file format, and the output file structure — all verified against a production Allegro 23.1 board.
Part 1: The
extractaUtilityLocation
Example:
C:\Cadence\SPB_23.1\tools\bin\extracta.exeThis is in the same
tools\bin\directory asa2ipc2581.exeandtechfile.exe.A companion tool
extracta_compiler.exealso exists at the same path (used internally for view file compilation — not needed for basic extraction).Environment Setup
Before calling
extracta.exe, initialize the Cadence environment:This is the same setup used for
a2ipc2581.exeandtechfile.exe.Command Syntax
Verified flags:
-q-sBoth flags should always be used together for headless/automated operation.
All valid flag characters:
[aPlcdgkmnpqrstwzAX+]There is no
-hor--helpflag — passing-hproduces:Switch 'h' is invalid.Full Example
Expected Console Output
This license warning is non-fatal — the export completes successfully despite it. It is the same warning seen with
a2ipc2581.exeandtechfile.exe. There is no other console output on success — the tool writes silently to the output file.Execution Time
3–10 seconds depending on design complexity and net count. Slower than
techfilebecauseextractaloads the full Allegro database engine to compute/read electrical values.License Requirements
Same Allegro license as the IPC-2581 exporter. Same serialization / queuing strategy should be applied.
Part 2: View Files
What They Are
View files are plain-text configuration files that tell
extractawhich database fields to export and in what order. They are the "schema" for the output.Location
Cadence ships ~120 predefined view files in:
View File Syntax
LAYER,NET)ENDis a field name to export#) excludes it from outputRelevant View Files for Electrical Data
net_bv.txt— Per-Net Electrical Measurements ⭐ HIGHEST VALUElayer_bv.txt— Layer Stackup Properties (Primary Stackup Only)Important: With
LAYER_STACKUP_NAMEcommented out, only the PRIMARY stackup layers are exported. To get all stackup regions, usemulti_stackup_bv.txtinstead (see below).multi_stackup_bv.txt— Multi-Region Layer StackupWhen
LAYER_STACKUP_NAMEis included,extractaoutputs one record per layer per stackup region. This is essential for multi-region flex/rigid-flex designs where different areas have different layer counts.stackups_bv.txt— Stackup Region SummaryOutputs one record per stackup region (not per layer) — just the region names, types, and positions.
Part 3: Output File Format
General Characteristics
Parsing Challenges
Material names contain spaces. This is the biggest parsing issue. Examples from verified output:
Since the output has no quoting and uses spaces as delimiters, naive
split(" ")parsing will break on multi-word material names. A positional/column-width parser or field-count-aware parser is needed.Units are inline. Numeric values include their unit as a separate space-delimited token:
Verified Output:
net_bv.txtOne row per net. Fields in order (matching the view file):
SHORT_70_00000030SHORT_70_30REGULAR0.27 pF1.06000.1346111.54 ohms161.35 ohms96.69 ohms3.15 nH1.07151.06000.00843 ns39.61 mohms8@\design_name\.\schematic\(sch_1):net_nameFull example row:
Observed record count: One row per routed net. Unrouted nets may not appear or may show zero-valued fields. A test design with 155 nets produced 31 rows — only nets with routed copper had records.
Verified Output:
multi_stackup_bv.txtOne row per layer per stackup region. Fields in order:
000003PRIMARYRIGIDTOP(blank for dielectrics)YES/NOPLATED_COPPER_FOIL0.393701 milCONDUCTOR/DIELECTRIC/DIELECTRIC_COVERLAY/SOLDER_MASK/SURFACE/CONDUCTIVE_FOIL/DIELECTRIC_BASE/DIELECTRIC_PREPREGSort key encoding: The thousands digit groups records by stackup region (000xxx = region 0, 003xxx = region 1, 005xxx = region 2, etc.). Within each group, the ones digits give the layer order from top to bottom in the cross-section.
Full example rows:
Observed record count: A design with 5 stackup regions and 18 layers in the primary stackup produced 87 rows total.
Verified Output:
layer_bv.txtOne row per layer in the PRIMARY stackup only. Fields in order:
000003TOP(blank for dielectrics)POSITIVE(blank for non-conductor)YES/NO4.500000343000 mho/cmPLATED_COPPER_FOILNO0.393701 milCONDUCTOR/DIELECTRIC/MASK/SURFACECONDUCTOR/DIELECTRIC/DIELECTRIC_COVERLAY/SURFACE/ etc.0.035NOT_EMBEDDED(blank for non-conductors)90.000(blank for non-conductors)Full example rows:
Observed record count: 18 rows for a 5-layer flex (5 conductors + dielectrics + coverlays + surfaces).
Part 4: How the Electrical Values Are Computed
The values in the
net_bv.txtoutput are not raw measurements — they are computed by Allegro's built-in analysis engine from the routed layout geometry combined with stackup properties. Understanding this is important for interpreting the data correctly.R = ρ · L / (W · t)where ρ is resistivity (fromCDS_LAYER_ELECTRICAL_CONDUCTIVITYin the stackup), L is etch length, W is trace width, t is copper thickness. Via barrel resistance is added per via.Z₀ = √(L/C)per unit length. The min/max/avg reflects variation along the net as trace width and reference plane spacing change (e.g., a trace crossing from a 5L region to a 3L region, or necking down near a via).t_pd = √(LC)per unit length × total etch length. Depends directly on the stackup Dk values — higher Dk means slower propagation.These values are post-route — they are stored/updated in the
.brddatabase after routing and DRC. They reflect the as-routed physical reality, not design intent (constraints).Part 5: Real-World Data Characteristics
Based on testing with a production Allegro 23.1 flex design:
extractaexecution timenet_bv.txtoutput sizemulti_stackup_bv.txtoutput sizelayer_bv.txtoutput sizePart 6: Available View Files
Cadence ships ~120 view files. The full list (filename and size) from a verified SPB 23.1 installation:
net_bv.txtlayer_bv.txtmulti_stackup_bv.txtstackups_bv.txtcomp_bv.txtnet_rep.txtpad_rep.txtpad_rep2.txtvia_structure.txtdrc_rep.txtbom_rep.txtncdrill.txtfabmaster.txtanalysis.txt(~106 additional view files exist for manufacturing, placement, pin, symbol, and other data — omitted for brevity.)
Custom view files can be created by copying any of these and adding/removing/commenting field names.