Pin Function Names Missing from Some DSN Reads

[vzegnameta]

Summary

When the Universal Netlist MCP reads .DSN files directly, query_component sometimes does not return pin function names. The same component queried via its exported .dat path always returns pin names, but queried via its .DSN path sometimes returns only pin-to-net mappings with no function name.

The behavior is inconsistent: some .DSN files return pin names correctly, others drop them entirely. Within a single design where pin names are missing, all components in that design are affected — it is not per-component.

Expected Behavior

query_component should return pin objects with both a name (function) and net for every pin, regardless of whether the design is read from .dat or .DSN:

{
  "refdes": "U1",
  "pins": {
    "A1": { "name": "VDD",  "net": "PP_1V8" },
    "A2": { "name": "SCL",  "net": "I2C_BUS_SCL" },
    "A3": { "name": "SDA",  "net": "I2C_BUS_SDA" },
    "B1": { "name": "GND",  "net": "GND" },
    "B2": { "name": "OUT0", "net": "DAC_CH0" },
    "B3": { "name": "IRQ",  "net": "HOST_IRQ_N" }
  },
  "mpn": "EXAMPLE-IC-001",
  "value": "EXAMPLE-IC-001"
}

Actual Behavior

Case A: DSN read returns pin names (works correctly)

Some .DSN files return pin names identically to the .dat path. For example, a 56-pin image sensor:

.dat read:

{
  "refdes": "U1",
  "pins": {
    "1":  { "name": "AGND_1",    "net": "AGND" },
    "2":  { "name": "AVDD_1",    "net": "SENSOR_AVDD_2P8" },
    "3":  { "name": "XSHUTDOWN", "net": "SENSOR_EN" },
    "50": { "name": "SDA",       "net": "I2C_SENSOR_SDA" },
    "51": { "name": "SCL",       "net": "I2C_SENSOR_SCL" },
    "53": { "name": "XVCLK",     "net": "SENSOR_CLK_24M" }
  }
}

.DSN read — identical ✅:

{
  "refdes": "U1",
  "pins": {
    "1":  { "name": "AGND_1",    "net": "AGND" },
    "2":  { "name": "AVDD_1",    "net": "SENSOR_AVDD_2P8" },
    "3":  { "name": "XSHUTDOWN", "net": "SENSOR_EN" },
    "50": { "name": "SDA",       "net": "I2C_SENSOR_SDA" },
    "51": { "name": "SCL",       "net": "I2C_SENSOR_SCL" },
    "53": { "name": "XVCLK",     "net": "SENSOR_CLK_24M" }
  }
}

Case B: DSN read drops pin names (the bug)

Other .DSN files drop pin names entirely. The pin value degrades from an object ({"name": ..., "net": ...}) to a flat string (just the net name):

.dat read — has pin names:

{
  "refdes": "U2",
  "pins": {
    "B4": { "name": "SCL/SYNC",  "net": "I2C_BUS_SCL" },
    "C4": { "name": "A0/SDI",    "net": "I2C_BUS_SDA" },
    "D4": { "name": "SDA/SCLK",  "net": "I2C_BUS_SDA" },
    "B1": { "name": "VDD",       "net": "PP_4V0" },
    "C1": { "name": "AGND",      "net": "GND" },
    "A1": { "name": "VREF",      "net": "DAC_VREF" },
    "D2": { "name": "OUT0",      "net": "DAC_CH0" },
    "A2": { "name": "OUT3/ADC",  "net": "DAC_CH3" },
    "D1": { "name": "CAP",       "net": "N00012345" }
  }
}

.DSN read — pin names gone ❌:

{
  "refdes": "U2",
  "pins": {
    "B4": "I2C_BUS_SCL",
    "C4": "I2C_BUS_SDA",
    "D4": "I2C_BUS_SDA",
    "B1": "PP_4V0",
    "C1": "GND",
    "A1": "DAC_VREF",
    "D2": "DAC_CH0",
    "A2": "DAC_CH3",
    "D1": "N00012345"
  }
}

A second component (30-pin BGA) in the same design is also affected:

.dat read:

{
  "refdes": "U3",
  "pins": {
    "J2": { "name": "IRQ_N",   "net": "HOST_IRQ_N" },
    "F1": { "name": "SCL",     "net": "I2C_BUS_SCL" },
    "E2": { "name": "SDA",     "net": "I2C_BUS_SDA" },
    "K1": { "name": "EN",      "net": "DRIVER_EN" },
    "B1": { "name": "LP",      "net": "LED_COMMON_ANODE" },
    "D3": { "name": "ID0",     "net": "GND" },
    "D1": { "name": "VSS_EE",  "net": "GND" },
    "F3": { "name": "DVSS",    "net": "GND" }
  }
}

.DSN read — also missing pin names ❌:

{
  "refdes": "U3",
  "pins": {
    "J2": "HOST_IRQ_N",
    "F1": "I2C_BUS_SCL",
    "E2": "I2C_BUS_SDA",
    "K1": "DRIVER_EN",
    "B1": "LED_COMMON_ANODE",
    "D3": "GND",
    "D1": "GND",
    "F3": "GND"
  }
}

Impact

1. Multiple pins on the same net become indistinguishable

With names: D3: ID0, D1: VSS_EE, F3: DVSS — each pin's role is clear even though they all connect to GND.

Without names: D3: GND, D1: GND, F3: GND — three identical-looking entries with no way to tell them apart.

2. Pin function identification requires datasheet cross-referencing

With names: "Which pin is SCL?" → B4: SCL/SYNC — instant answer.

Without names: "Which pin is SCL?" → B4: I2C_BUS_SCL — you can guess from the net name, but this breaks down for auto-named nets like N00012345.

3. Alternate pin functions are invisible

With names: A2: OUT3/ADC reveals the pin supports ADC mode. D4: SDA/SCLK reveals an SPI alternate function.

Without names: A2: DAC_CH3 — no indication of the ADC capability.

Reproduction

1. Find a .DSN file that has a companion exported .dat (pstxnet.dat) for the same design
2. Query the same component via both paths using query_component
3. Compare the pins field — the .dat read returns {"name": "...", "net": "..."} objects, the .DSN read returns flat "net_name" strings

Not all .DSN files exhibit this. Some return pin names correctly (Case A above). The bug manifests on a per-design basis — when a design is affected, all components in that design are missing pin names.

Environment

• Tool: Universal Netlist MCP
• Input: Cadence OrCAD .DSN schematic files (read directly, no Allegro export)
• Comparison: Same designs queried via exported pstxnet.dat (Allegro PCB netlist format)