More speed up the emulation

[myftptoyman]

I’m experimenting with the dual-core Rocket design on Arcilator, running it on both RTX 4090 and RTX 4080 GPUs. So far, the simulator tops out at around 50 – 57 k cycles/s. My profiling suggests that the deep logic levels are the primary bottleneck. I’m considering collapsing the AIG netlist into 6-input LUT cells—similar to how GEM packs SRAM LUTs—to shorten the logic depth. If this works, I estimate we could push performance to roughly 100 – 200 k cycles/s, making the GPU flow much more competitive with FPGA-based emulators.

[gzz2000]

We are pleased to see novel ideas inspired by our work!
We also observed the deep logic level bottleneck and our solution was to introduce a Boomerang-shaped execution stage to fully utilize each shuffle between two consecutive stages.
We encourage you to make a theoretical evaluation on these overheads under your 6-input LUT framework and compare it with our original Boomerang stage. If you find your solution promising, please have a try and let us know your progress :)

[myftptoyman]

I ran several tests to measure logic-level depth and PE usage.
On a RISC-V CPU core, the AND-gate implementation reaches 156 logic levels and about 440 000 cells, whereas the LUT-4 implementation needs only 56 logic levels and roughly 220 000 cells. The AND-gate PE requires a level-split of 20 to partition the logic path, but the LUT-4 PE does not.

My next step is to flatten the design and port it to a CUDA kernel.

I’ve never learned Rust; I simply rely on “vibe coding” to drive the cursor while porting the LUT-4 structure. According to the AI analysis, switching to the LUT-4 structure could deliver roughly a 50 % speed-up.

[gzz2000]

Have you counted the number of Boomerang stages or the logic levels? The former number should be much lower than 156.

[yanqingz]

For a point of reference, In our open source benchmarks, the baseline Rocket has a 156-wide multiplier, which reaches ~11-13 boomerang stages, subject to the quality of the hypergraph partitioning and subsequent merging algorithm. 156 AIG logic levels is well within reason.

Compacting logic to LUT format brings several advantages, in addition to reducing logic levels, good LUT compilers can compact logic into N-input-M-output format, further compacting logic. Comes at a possibly steep cost of complex routing of signals, which would defeat the memory access latency savings from GEM.