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feat(pmu): integrate CUTEPMU AME perf counters #67

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1 change: 1 addition & 0 deletions src/main/scala/cutewrapper/XSCuteTop.scala
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Expand Up @@ -22,6 +22,7 @@ class XSCuteTopImpl(wrapper: XSCuteTop) extends LazyModuleImp(wrapper) {
val matrix_data_in = wrapper.cute_tl.module.io.matrix_data_in.cloneType
})
io.ctrl2top <> cute.io.ctrl2top
io.perf <> cute.io.perf
wrapper.cute_tl.module.io.matrix_data_in <> io.matrix_data_in
wrapper.cute_tl.module.io.mmu <> cute.io.mmu2llc
io.mmu2llc := DontCare
Expand Down
18 changes: 18 additions & 0 deletions src/main/scala/xiangshan/XSCore.scala
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Expand Up @@ -36,6 +36,7 @@ import xiangshan.backend.trace.TraceCoreInterface
import xiangshan.mem._
import xiangshan.cache.mmu._
import xiangshan.cache.mmu.TlbRequestIO
import cute.{AmePerfFromCSRIO, AmePerfToCoreIO}
import scala.collection.mutable.ListBuffer

abstract class XSModule(implicit val p: Parameters) extends Module
Expand Down Expand Up @@ -119,6 +120,8 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
val dft_reset = Option.when(hasDFT)(Input(new DFTResetSignals()))
val amuCtrl = Option.when(HasMatrixExtension)(Decoupled(new AmuCtrlIO))
val amuRelease = Option.when(HasMatrixExtension)(Flipped(Decoupled(new AmuReleaseIO2XS)))
val ameToCUTE = Option.when(HasMatrixExtension)(Output(new AmePerfFromCSRIO))
val ameFromCUTE = Option.when(HasMatrixExtension)(Input(new AmePerfToCoreIO))
})

dontTouch(io.l2_flush_done)
Expand Down Expand Up @@ -206,8 +209,23 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
backend.io.perf.perfEventsBackend := DontCare
backend.io.perf.retiredInstr := DontCare
backend.io.perf.ctrlInfo := DontCare
backend.io.perf.perfEventsAme.foreach(_.value := 0.U)
backend.io.perf.fixedPerfAme.foreach(_.value := 0.U)

backend.io.mem.storeDebugInfo <> memBlock.io.mem_to_ooo.storeDebugInfo

if (HasMatrixExtension) {
val enableAme = p(MatAccKey) == MatAcc.CUTE
io.ameToCUTE.get.csrW.valid := false.B
io.ameToCUTE.get.csrW.bits.addr := 0.U
io.ameToCUTE.get.csrW.bits.data := 0.U

when(enableAme.B) {
io.ameToCUTE.get.csrW := backend.io.csrCustomCtrl.distribute_csr.w
backend.io.perf.perfEventsAme := io.ameFromCUTE.get.perfEventsAme
backend.io.perf.fixedPerfAme := io.ameFromCUTE.get.fixedPerfAme
}
}

if (HasMatrixExtension) {
val amuCtrlArbiter = Module(new Arbiter(new AmuCtrlIO, CommitWidth))
Expand Down
17 changes: 16 additions & 1 deletion src/main/scala/xiangshan/XSTile.scala
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Expand Up @@ -33,7 +33,7 @@ import coupledL2.tl2chi.PortIO
import xiangshan.backend.trace.TraceCoreInterface
import xiangshan.backend.fu.matrix._
import xiangshan.backend.fu.matrix.Bundles._
import cute.XSCute
import cute.{AmePerfToCoreIO, XSCute}

object MatAcc extends Enumeration {
type MatAcc = Value
Expand Down Expand Up @@ -258,10 +258,25 @@ class XSTile()(implicit p: Parameters) extends LazyModule

val matrix_data_out = l2top.module.io.matrixDataOut512L2
cute.module.io.matrix_data_in <> matrix_data_out
core.module.io.ameToCUTE.foreach { toCUTE =>
cute.module.io.cute.perf.fromCSR <> toCUTE
}
core.module.io.ameFromCUTE.foreach { fromCUTE =>
fromCUTE <> cute.module.io.cute.perf.toCore
}

cute.module.io.hartId := io.hartId
}

if (HasMatrixExtension && cuteOpt.isEmpty) {
core.module.io.ameToCUTE.foreach { toCUTE =>
toCUTE.csrW.valid := false.B
toCUTE.csrW.bits.addr := 0.U
toCUTE.csrW.bits.data := 0.U
}
core.module.io.ameFromCUTE.foreach(_ := 0.U.asTypeOf(new AmePerfToCoreIO))
}

if (!HasMatrixExtension) {
l2top.module.io.matrixDataOut512L2 := DontCare
l2top.module.io.matrixDataOut512L2.foreach(_.ready := false.B)
Expand Down
4 changes: 4 additions & 0 deletions src/main/scala/xiangshan/backend/fu/CSR.scala
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Expand Up @@ -36,6 +36,7 @@ import utils.MathUtils.{BigIntGenMask, BigIntNot}
import xiangshan.backend.trace._
import freechips.rocketchip.rocket.CSRs
import system.HasSoCParameter
import cute.{CuteParamsKey, PerfEventAme}

class FpuCsrIO extends Bundle {
val fflags = Output(Valid(UInt(5.W)))
Expand Down Expand Up @@ -70,10 +71,13 @@ class MpuCsrIO(implicit p: Parameters) extends XSBundle {
}

class PerfCounterIO(implicit p: Parameters) extends XSBundle {
private val ameCounterNum = if (HasMatrixExtension && p(MatAccKey) == MatAcc.CUTE) p(CuteParamsKey).AmeCounterNum else 29
val perfEventsFrontend = Vec(numCSRPCntFrontend, new PerfEvent)
val perfEventsBackend = Vec(numCSRPCntCtrl, new PerfEvent)
val perfEventsLsu = Vec(numCSRPCntLsu, new PerfEvent)
val perfEventsHc = Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)
val perfEventsAme = Vec(ameCounterNum, new PerfEventAme)
val fixedPerfAme = Vec(2, new PerfEventAme)
val retiredInstr = UInt(7.W)
val frontendInfo = new Bundle {
val ibufFull = Bool()
Expand Down
59 changes: 52 additions & 7 deletions src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
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Expand Up @@ -7,6 +7,7 @@ import freechips.rocketchip.rocket.CSRs
import xiangshan.backend.fu.NewCSR.CSRBundles.{Counteren, PrivState}
import xiangshan.backend.fu.NewCSR.CSRDefines._
import org.chipsalliance.cde.config.Parameters
import xiangshan.backend.fu.util.CSRConst._
import system.HasSoCParameter

class CSRPermitModule(implicit p: Parameters) extends Module {
Expand Down Expand Up @@ -186,6 +187,8 @@ class MLevelPermitModule extends Module {
private val tvm = io.in.status.tvm

private val mcounteren = io.in.xcounteren.mcounteren
private val ameMcounteren = io.in.xcounteren.ameMcounteren
private val ameScounteren = io.in.xcounteren.ameScounteren

private val mstateen0 = io.in.xstateen.mstateen0
private val mstateen1 = io.in.xstateen.mstateen1
Expand All @@ -211,13 +214,15 @@ class MLevelPermitModule extends Module {

private val csrIsRO = addr(11, 10) === "b11".U
private val csrIsHPM = addr >= CSRs.cycle.U && addr <= CSRs.hpmcounter31.U
private val csrIsAmeURO = addr === AmeCycle.U || addr === AmeInstret.U || (addr >= AmeHpmcounter3.U && addr <= AmeHpmcounter31.U)
private val csrIsFp = Seq(CSRs.fflags, CSRs.frm, CSRs.fcsr).map(_.U === addr).reduce(_ || _)
private val csrIsVec = Seq(CSRs.vstart, CSRs.vxsat, CSRs.vxrm, CSRs.vcsr, CSRs.vtype).map(_.U === addr).reduce(_ || _)
private val csrIsWritableVec = Seq(CSRs.vstart, CSRs.vxsat, CSRs.vxrm, CSRs.vcsr).map(_.U === addr).reduce(_ || _)
private val csrIsMatrix = Seq(CSRs.xmcsr, CSRs.xmxrm, CSRs.xmsat, CSRs.xmfflags, CSRs.xmfrm, CSRs.xmsaten).map(_.U === addr).reduce(_ || _)
private val csrIsWritableMatrix = Seq(CSRs.xmcsr, CSRs.xmxrm, CSRs.xmsat, CSRs.xmfflags, CSRs.xmfrm, CSRs.xmsaten).map(_.U === addr).reduce(_ || _)

private val counterAddr = addr(4, 0) // 32 counters
private val ameCounterAddr = Mux(addr === AmeCycle.U, 0.U, Mux(addr === AmeInstret.U, 2.U, addr(4, 0)))

private val rwIllegal = csrIsRO && wen

Expand All @@ -234,6 +239,11 @@ class MLevelPermitModule extends Module {
private val rwStimecmp_EX_II = !privState.isModeM && (!mcounterenTM || !menvcfgSTCE) && (addr === CSRs.vstimecmp.U || addr === CSRs.stimecmp.U)

private val accessHPM_EX_II = csrIsHPM && !privState.isModeM && !mcounteren(counterAddr)
private val accessAmeURO_EX_II = csrIsAmeURO && (
privState.isModeHS && !ameMcounteren(ameCounterAddr) ||
privState.isModeHU && (!ameMcounteren(ameCounterAddr) || !ameScounteren(ameCounterAddr))
)
private val accessAmeScountovf_EX_II = addr === AmeScountovf.U && privState.isModeHU

private val rwSatp_EX_II = privState.isModeHS && tvm && (addr === CSRs.satp.U || addr === CSRs.hgatp.U)

Expand Down Expand Up @@ -294,7 +304,17 @@ class MLevelPermitModule extends Module {
// [0x800, 0x8ff], [0xcc0, 0xcff]
private val csrIsUCustom = (addr(11, 8) === "b1000".U) || (addr(11, 6) === "b110011".U)
private val allCustom = csrIsHVSCustom || csrIsSCustom || csrIsUCustom
private val accessCustom_EX_II = allCustom && !privState.isModeM && !mstateen0.C.asBool
private val csrIsAmeCounterCSR = (
addr === AmeMcounteren.U || addr === AmeScounteren.U || addr === AmeHcounteren.U ||
addr === AmeMcountinhibit.U ||
(addr >= AmeMhpmevent3.U && addr <= AmeMhpmevent31.U) ||
(addr >= AmeMhpmcounter3.U && addr <= AmeMhpmcounter31.U) ||
addr === AmeMcycle.U || addr === AmeMinstret.U ||
addr === AmeCycle.U || addr === AmeInstret.U ||
(addr >= AmeHpmcounter3.U && addr <= AmeHpmcounter31.U) ||
addr === AmeScountovf.U
)
private val accessCustom_EX_II = allCustom && !csrIsAmeCounterCSR && !privState.isModeM && !mstateen0.C.asBool

private val xstateControlAccess_EX_II = accessStateen_EX_II || accessEnvcfg_EX_II || accessIND_EX_II || accessAIA_EX_II ||
accessTopie_EX_II || accessContext_EX_II || accessCustom_EX_II
Expand All @@ -303,7 +323,7 @@ class MLevelPermitModule extends Module {
*/

io.out.mLevelPermit_EX_II := rwIllegal || fpVecMatrix_EX_II || rwStimecmp_EX_II ||
accessHPM_EX_II || rwSatp_EX_II || rwStopei_EX_II || xstateControlAccess_EX_II
accessHPM_EX_II || accessAmeURO_EX_II || accessAmeScountovf_EX_II || rwSatp_EX_II || rwStopei_EX_II || xstateControlAccess_EX_II
io.out.hasLegalWriteFcsr := wen && csrIsFp && !fsEffectiveOff
io.out.hasLegalWriteVcsr := wen && csrIsWritableVec && !vsEffectiveOff
io.out.hasLegalWriteMcsr := wen && csrIsWritableMatrix && !msEffectiveOff
Expand Down Expand Up @@ -337,7 +357,8 @@ class SLevelPermitModule extends Module {
private val accessHPM_EX_II = csrIsHPM && privState.isModeHU && !scounteren(counterAddr)

private val csrIsUCustom = (addr(11, 8) === "b1000".U) || (addr(11, 6) === "b110011".U)
private val accessCustom_EX_II = csrIsUCustom && privState.isModeHU && !sstateen0.C.asBool
private val csrIsAmeURO = addr === AmeCycle.U || addr === AmeInstret.U || (addr >= AmeHpmcounter3.U && addr <= AmeHpmcounter31.U)
private val accessCustom_EX_II = csrIsUCustom && !csrIsAmeURO && privState.isModeHU && !sstateen0.C.asBool

io.out.sLevelPermit_EX_II := accessHPM_EX_II || accessCustom_EX_II
}
Expand Down Expand Up @@ -417,9 +438,12 @@ class VirtualLevelPermitModule(implicit val p: Parameters) extends Module with H
io.in.status.vgein,
)

private val (hcounteren, scounteren) = (
private val (hcounteren, scounteren, ameMcounteren, ameHcounteren, ameScounteren) = (
io.in.xcounteren.hcounteren,
io.in.xcounteren.scounteren,
io.in.xcounteren.ameMcounteren,
io.in.xcounteren.ameHcounteren,
io.in.xcounteren.ameScounteren,
)

private val hcounterenTM = hcounteren(1)
Expand All @@ -439,7 +463,9 @@ class VirtualLevelPermitModule(implicit val p: Parameters) extends Module with H
private val hvictlVTI = io.in.aia.hvictlVTI

private val csrIsHPM = addr >= CSRs.cycle.U && addr <= CSRs.hpmcounter31.U
private val csrIsAmeURO = addr === AmeCycle.U || addr === AmeInstret.U || (addr >= AmeHpmcounter3.U && addr <= AmeHpmcounter31.U)
private val counterAddr = addr(4, 0) // 32 counters
private val ameCounterAddr = Mux(addr === AmeCycle.U, 0.U, Mux(addr === AmeInstret.U, 2.U, addr(4, 0)))

private val rwSatp_EX_VI = privState.isModeVS && vtvm && (addr === CSRs.satp.U)

Expand All @@ -455,6 +481,11 @@ class VirtualLevelPermitModule(implicit val p: Parameters) extends Module with H
privState.isModeVS && !hcounteren(counterAddr) ||
privState.isModeVU && (!hcounteren(counterAddr) || !scounteren(counterAddr))
)
private val accessAmeURO_EX_VI = csrIsAmeURO && (
privState.isModeVS && (!ameMcounteren(ameCounterAddr) || !ameHcounteren(ameCounterAddr)) ||
privState.isModeVU && (!ameMcounteren(ameCounterAddr) || !ameHcounteren(ameCounterAddr) || !ameScounteren(ameCounterAddr))
)
private val accessAmeScountovf_EX_VI = addr === AmeScountovf.U && privState.isModeVU

/**
* Sm/Ssstateen begin
Expand Down Expand Up @@ -496,14 +527,25 @@ class VirtualLevelPermitModule(implicit val p: Parameters) extends Module with H
private val csrIsSCustom = (addr(11, 10) =/= "b00".U) && (addr(9, 8) === "b01".U) && (addr(7, 6) === "b11".U)
// [0x800, 0x8ff], [0xcc0, 0xcff]
private val csrIsUCustom = (addr(11, 8) === "b1000".U) || (addr(11, 6) === "b110011".U)
private val accessCustom_EX_VI = (csrIsSCustom || csrIsUCustom) && privState.isVirtual && !hstateen0.C.asBool ||
csrIsUCustom && privState.isModeVU && hstateen0.C.asBool && !sstateen0.C.asBool
private val csrIsAmeCounterCSR = (
addr === AmeMcounteren.U || addr === AmeScounteren.U || addr === AmeHcounteren.U ||
addr === AmeMcountinhibit.U ||
(addr >= AmeMhpmevent3.U && addr <= AmeMhpmevent31.U) ||
(addr >= AmeMhpmcounter3.U && addr <= AmeMhpmcounter31.U) ||
addr === AmeMcycle.U || addr === AmeMinstret.U ||
addr === AmeCycle.U || addr === AmeInstret.U ||
(addr >= AmeHpmcounter3.U && addr <= AmeHpmcounter31.U) ||
addr === AmeScountovf.U
)
private val accessCustom_EX_VI = (csrIsSCustom || csrIsUCustom) && !csrIsAmeCounterCSR && privState.isVirtual && !hstateen0.C.asBool ||
csrIsUCustom && !csrIsAmeCounterCSR && privState.isModeVU && hstateen0.C.asBool && !sstateen0.C.asBool

private val xstateControlAccess_EX_VI = accessStateen_EX_VI || accessEnvcfg_EX_VI || accessIND_EX_VI || accessAIA_EX_VI ||
accessTopie_EX_VI || accessContext_EX_VI || accessCustom_EX_VI

io.out.virtualLevelPermit_EX_II := rwVStopei_EX_II
io.out.virtualLevelPermit_EX_VI := rwSatp_EX_VI || rwStopei_EX_VI || rwSip_Sie_EX_VI || rwStimecmp_EX_VI || accessHPM_EX_VI || xstateControlAccess_EX_VI
io.out.virtualLevelPermit_EX_VI := rwSatp_EX_VI || rwStopei_EX_VI || rwSip_Sie_EX_VI || rwStimecmp_EX_VI ||
accessHPM_EX_VI || accessAmeURO_EX_VI || accessAmeScountovf_EX_VI || xstateControlAccess_EX_VI
}

class IndirectCSRPermitModule extends Module {
Expand Down Expand Up @@ -620,6 +662,9 @@ class xcounterenIO extends Bundle {
// Accessing PMC from **HU level** will trap EX_II, if s[x]=0
// Accessing PMC from **VU level** will trap EX_VI, if m[x]=1 && h[x]=1 && s[x]=0
val scounteren = UInt(32.W)
val ameMcounteren = UInt(32.W)
val ameHcounteren = UInt(32.W)
val ameScounteren = UInt(32.W)
}

class xenvcfgIO extends Bundle {
Expand Down
7 changes: 6 additions & 1 deletion src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
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Expand Up @@ -12,6 +12,7 @@ import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._
import xiangshan.backend.fu.NewCSR.CSREvents.{SretEventSinkBundle, TrapEntryHSEventSinkBundle}
import xiangshan.backend.fu.NewCSR.CSRFunc._
import xiangshan.backend.fu.NewCSR.ChiselRecordForField._
import xiangshan.backend.fu.util.CSRConst._
import system.HasSoCParameter

import scala.collection.immutable.SeqMap
Expand Down Expand Up @@ -61,6 +62,10 @@ trait HypervisorLevel { self: NewCSR =>
val hcounteren = Module(new CSRModule("Hcounteren", new Counteren))
.setAddr(CSRs.hcounteren)

val ameHcounteren = if (enableAme) Some(
Module(new CSRModule("AmeHcounteren", new Counteren)).setAddr(AmeHcounteren)
) else None

val hgeie = Module(new CSRModule("Hgeie", new HgeieBundle))
.setAddr(CSRs.hgeie)

Expand Down Expand Up @@ -217,7 +222,7 @@ trait HypervisorLevel { self: NewCSR =>
hstateen2,
hstateen3,
hcontext,
)
) ++ ameHcounteren.toSeq

val hypervisorCSRMap: SeqMap[Int, (CSRAddrWriteBundle[_], UInt)] = SeqMap.from(
hypervisorCSRMods.map(csr => (csr.addr -> (csr.w -> csr.rdata))).iterator
Expand Down
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