sdram controller for DE10-LITE in verilog

[roman012285]

Hi, I am looking for that controller in Verilog/system Verilog. Can you help me please?

[Sch-Tim]

I'm sorry, I can barely even read verilog code.
If you only want to use the code without modification, it should be possible to implement it.

[roman012285]

Thanks, i cant inderstant why its not working. Do you familier with any tutorial that explains the state machine of sdram. I am sure that every thing in my implementation is implemented good, its not that hard but somehow it seems I miss something.
I just want to read and write one 16 bit without any bursts. If you famileir with person yhat can help even for money I will be happy

[Sch-Tim]

If you share some code/errors, I can try something.
What is this project for? Is it some commercial or a student project?

I can read verilog code, but I never wrote more than some customizations to finished verilog examples.

[roman012285]

Thanks, I am a hobist working on riscv architecture, its not comercial.
I will send you thanks allot.
Maybe it will be better to meet at zoom of course with pay so I will be able to ask some questions and get short guide from you