From 29b4063d2384679f5f585f59eae96163f10356ab Mon Sep 17 00:00:00 2001 From: rleiser1995 Date: Fri, 29 Mar 2024 12:27:18 +0100 Subject: [PATCH 01/13] Added the current verilog files to a new modul, added the surrounding code, derived from the bdaq example to a new example. --- =1.8.1 | 88 ++ Makefile | 53 + basil/HL/tdl_tdc.py | 142 +++ basil/TL/SiSim.py | 2 +- basil/firmware/modules/tdl_tdc/clk_divide.v | 23 + basil/firmware/modules/tdl_tdc/controller.v | 226 ++++ .../tdl_tdc/counter/signal_clipper.vhdl | 57 + .../counter/slimfast_multioption_counter.ucf | 29 + .../counter/slimfast_multioption_counter.v | 171 +++ .../counter/slimfast_multioption_counter.xdc | 31 + .../delayline/carrysampler_spartan6_20ps.v | 95 ++ .../modules/tdl_tdc/delayline/sample_deser.v | 116 ++ .../modules/tdl_tdc/priority_encoder_only.v | 73 ++ basil/firmware/modules/tdl_tdc/sw_interface.v | 243 ++++ basil/firmware/modules/tdl_tdc/tdc.v | 148 +++ basil/firmware/modules/tdl_tdc/tdc_core.v | 194 +++ .../modules/tdl_tdc/tdl_supersampler.v | 49 + .../firmware/modules/tdl_tdc/utils/delay_n.v | 22 + .../tdl_tdc/utils/graycode_2stage_cdc.v | 28 + basil/firmware/modules/tdl_tdc/word_broker.v | 113 ++ examples/tdc_bdaq/SiTCP | 1 + examples/tdc_bdaq/SiTCP.xdc | 31 + examples/tdc_bdaq/Vivado/tdc_bdaq.xpr | 449 +++++++ examples/tdc_bdaq/bdaq53.xdc | 106 ++ examples/tdc_bdaq/tdc_bdaq.py | 186 +++ examples/tdc_bdaq/tdc_bdaq.v | 469 +++++++ examples/tdc_bdaq/tdc_bdaq.xdc | 43 + examples/tdc_bdaq/tdc_bdaq.yaml | 46 + examples/tdc_bdaq/vivado.jou | 115 ++ examples/tdc_bdaq/vivado.log | 1110 +++++++++++++++++ sim_build/cmds.f | 1 + tests/Makefile | 53 + tests/test_SimTdl_Tdc.py | 180 +++ tests/test_SimTdl_Tdc.v | 212 ++++ 34 files changed, 4904 insertions(+), 1 deletion(-) create mode 100644 =1.8.1 create mode 100644 Makefile create mode 100644 basil/HL/tdl_tdc.py create mode 100644 basil/firmware/modules/tdl_tdc/clk_divide.v create mode 100644 basil/firmware/modules/tdl_tdc/controller.v create mode 100644 basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl create mode 100644 basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.ucf create mode 100644 basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v create mode 100644 basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.xdc create mode 100644 basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v create mode 100644 basil/firmware/modules/tdl_tdc/delayline/sample_deser.v create mode 100644 basil/firmware/modules/tdl_tdc/priority_encoder_only.v create mode 100644 basil/firmware/modules/tdl_tdc/sw_interface.v create mode 100644 basil/firmware/modules/tdl_tdc/tdc.v create mode 100644 basil/firmware/modules/tdl_tdc/tdc_core.v create mode 100644 basil/firmware/modules/tdl_tdc/tdl_supersampler.v create mode 100644 basil/firmware/modules/tdl_tdc/utils/delay_n.v create mode 100644 basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v create mode 100644 basil/firmware/modules/tdl_tdc/word_broker.v create mode 160000 examples/tdc_bdaq/SiTCP create mode 100644 examples/tdc_bdaq/SiTCP.xdc create mode 100644 examples/tdc_bdaq/Vivado/tdc_bdaq.xpr create mode 100644 examples/tdc_bdaq/bdaq53.xdc create mode 100644 examples/tdc_bdaq/tdc_bdaq.py create mode 100644 examples/tdc_bdaq/tdc_bdaq.v create mode 100644 examples/tdc_bdaq/tdc_bdaq.xdc create mode 100644 examples/tdc_bdaq/tdc_bdaq.yaml create mode 100644 examples/tdc_bdaq/vivado.jou create mode 100644 examples/tdc_bdaq/vivado.log create mode 100644 sim_build/cmds.f create mode 100644 tests/Makefile create mode 100644 tests/test_SimTdl_Tdc.py create mode 100644 tests/test_SimTdl_Tdc.v diff --git a/=1.8.1 b/=1.8.1 new file mode 100644 index 00000000..93c81f6e --- /dev/null +++ b/=1.8.1 @@ -0,0 +1,88 @@ +Collecting pyvisa + Downloading PyVISA-1.14.1-py3-none-any.whl.metadata (7.1 kB) +Collecting pyvisa-sim + Downloading PyVISA_sim-0.6.0-py3-none-any.whl.metadata (5.7 kB) +Requirement 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Building wheel for coverage (pyproject.toml): started + Building wheel for coverage (pyproject.toml): finished with status 'done' + Created wheel for coverage: filename=coverage-6.5.0-cp312-cp312-linux_x86_64.whl size=187573 sha256=c2b7a4fc6a4a9c216790a49e5d47d791fd413ba34cfea8cc0e09be4fb36c20f8 + Stored in directory: /users/rleiser/.cache/pip/wheels/a7/85/79/1888edb87e446075e2d1d011f7470ac992016bc1fc7f65ed38 + Building wheel for docopt (setup.py): started + Building wheel for docopt (setup.py): finished with status 'done' + Created wheel for docopt: filename=docopt-0.6.2-py2.py3-none-any.whl size=13705 sha256=ef366333a56bc116be14830d83ee06b081a6169cce47c51d5ead04ddc09e2eb6 + Stored in directory: /users/rleiser/.cache/pip/wheels/1a/bf/a1/4cee4f7678c68c5875ca89eaccf460593539805c3906722228 +Successfully built cocotb-bus coverage docopt +Installing collected packages: find-libpython, docopt, urllib3, typing-extensions, idna, coverage, cocotb, charset-normalizer, certifi, stringparser, requests, pyvisa, cocotb-bus, pyvisa-sim, pytest-cov, coveralls +Successfully installed certifi-2024.2.2 charset-normalizer-3.3.2 cocotb-1.8.1 cocotb-bus-0.2.1 coverage-6.5.0 coveralls-3.3.1 docopt-0.6.2 find-libpython-0.4.0 idna-3.7 pytest-cov-5.0.0 pyvisa-1.14.1 pyvisa-sim-0.6.0 requests-2.31.0 stringparser-0.7 typing-extensions-4.11.0 urllib3-2.2.1 diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..03405359 --- /dev/null +++ b/Makefile @@ -0,0 +1,53 @@ +SIMULATION_HOST?=localhost +SIMULATION_PORT?=12345 +SIMULATION_BUS?=basil.utils.sim.BasilBusDriver +SIMULATION_END_ON_DISCONNECT?=1 + +VERILOG_SOURCES = /users/rleiser/work/basil_branch/tests/test_SimTdc.v + +TOPLEVEL = tb +MODULE = basil.utils.sim.Test + +ICARUS_INCLUDE_DIRS = -I/users/rleiser/work/basil_branch/basil/firmware/modules -I/users/rleiser/work/basil_branch/basil/firmware/modules/includes +ICARUS_DEFINES += + +NOT_ICARUS_DEFINES = +NOT_ICARUS_INCLUDE_DIRS=+incdir+./ +incdir+/users/rleiser/work/basil_branch/basil/firmware/modules +incdir+/users/rleiser/work/basil_branch/basil/firmware/modules/includes +COMPILE_ARGS_DEFINES = +BUILD_ARGS_DEFINES = + + + +export SIMULATION_HOST +export SIMULATION_PORT +export SIMULATION_BUS +export SIMULATION_END_ON_DISCONNECT + +export COCOTB=$(shell cocotb-config --share) +#export COCOTB=$(shell SPHINX_BUILD=1 python -c "import cocotb; import os; print(os.path.dirname(os.path.dirname(os.path.abspath(cocotb.__file__))))") +#export PYTHONPATH=$(shell python -c "from distutils import sysconfig; print(sysconfig.get_python_lib())"):$(COCOTB) +#export LD_LIBRARY_PATH=/lib/x86_64-linux-gnu:$(PYTHONLIBS) +export PYTHONHOME=$(shell python -c "from distutils.sysconfig import get_config_var; print(get_config_var('prefix'))") + +ifeq ($(SIM),questa) + EXTRA_ARGS += $(NOT_ICARUS_DEFINES) + EXTRA_ARGS += $(NOT_ICARUS_INCLUDE_DIRS) +else ifeq ($(SIM),ius) + EXTRA_ARGS += $(NOT_ICARUS_DEFINES) + EXTRA_ARGS += $(NOT_ICARUS_INCLUDE_DIRS) +else + COMPILE_ARGS += $(ICARUS_DEFINES) + COMPILE_ARGS += $(ICARUS_INCLUDE_DIRS) +endif + +COMPILE_ARGS += $(COMPILE_ARGS_DEFINES) +ifeq ($(SIM), verilator) + BUILD_ARGS += $(BUILD_ARGS_DEFINES) +endif + +TOPLEVEL_LANG?=verilog +export TOPLEVEL_LANG + +include $(shell cocotb-config --makefiles)/Makefile.sim + + \ No newline at end of file diff --git a/basil/HL/tdl_tdc.py b/basil/HL/tdl_tdc.py new file mode 100644 index 00000000..d5547138 --- /dev/null +++ b/basil/HL/tdl_tdc.py @@ -0,0 +1,142 @@ +# +# ------------------------------------------------------------ +# Copyright (c) All rights reserved +# SiLab, Institute of Physics, University of Bonn +# ------------------------------------------------------------ +# + +from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer +import numpy as np + + +class tdl_tdc(RegisterHardwareLayer): + '''TDC controller interface + ''' + + GHZ_S_FREQ = 0.48 + CLK_DIV = 3 + word_type_codes = {0 : 'TRIGGERED', + 1 : 'RISING', + 2 : 'FALLING', + 3 : 'TIMESTAMP', + 4 : 'CALIB', + 5 : 'MISS', + 6 : 'RST'} + + _registers = {'RESET': {'descr': {'addr': 0, 'size': 7, 'offset': 1, 'properties': ['writeonly']}}, + 'VERSION': {'descr': {'addr': 0, 'size': 8, 'properties': ['ro']}}, + 'ENABLE': {'descr': {'addr': 1, 'size': 1, 'offset': 0}}, + 'ENABLE_EXTERN': {'descr': {'addr': 1, 'size': 1, 'offset': 1}}, + 'EN_ARMING': {'descr': {'addr': 1, 'size': 1, 'offset': 2}}, + 'EN_WRITE_TIMESTAMP': {'descr': {'addr': 1, 'size': 1, 'offset': 3}}, + 'EN_TRIGGER_DIST': {'descr': {'addr': 1, 'size': 1, 'offset': 4}}, + 'EN_NO_WRITE_TRIG_ERR': {'descr': {'addr': 1, 'size': 1, 'offset': 5}}, + 'EN_INVERT_TDC': {'descr': {'addr': 1, 'size': 1, 'offset': 6}}, + 'EN_INVERT_TRIGGER': {'descr': {'addr': 1, 'size': 1, 'offset': 7}}, + 'EVENT_COUNTER': {'descr': {'addr': 2, 'size': 32, 'properties': ['ro']}}, + 'LOST_DATA_COUNTER': {'descr': {'addr': 6, 'size': 8, 'properties': ['ro']}}, + 'TDL_MISS_COUNTER' : {'descr' : {'addr': 7, 'size': 8, 'porperties' :['ro']}}, + 'EN_CALIBRATION_MOD': {'descr': {'addr': 8, 'size': 1, 'offset': 0}}} + + _require_version = "==2" + + calib_vector = np.ones(92) + calib_sum = np.sum(calib_vector) + + def __init__(self, intf, conf): + super(tdl_tdc, self).__init__(intf, conf) + + def get_tdc_value(self, word): + # The last 7 bit are tdl data, the first 7 bits are word type and source, so 18 bits are counter information + # Of these, the last two bits are timing wrt. the fast clock and the first 16 wrt. to the slow clock + return self.CLK_DIV*((word >> 9) & 0x0FFFF) + (((word >> 7) & 0x3)) + + def get_word_type(self, word): + return (word >> (32 - 7) & 0b111) + + def is_calib_word(self, word): + return self.get_word_type(word) == 4 + + def is_time_word(self, word): + return self.get_word_type(word) in [0, 1, 2,] + + def get_raw_tdl_values(self, word): + return word & 0b1111111 + + def tdl_to_time(self, tdl_value) : + sample_proportion = np.sum(self.calib_vector[0:tdl_value-1])/self.calib_sum + return sample_proportion * 1/self.GHZ_S_FREQ + + def set_calib_values(self, calib_values) : + calib_values = np.append(calib_values,np.arange(92)) + data_sort, value_counts = np.unique(calib_values % 128, return_counts = True) + self.calib_vector = value_counts + self.calib_sum = np.sum(value_counts) + + def tdc_word_to_time(self, word) : + if isinstance(word, dict) : + word = word['raw_word'] + if (not self.is_time_word(word)) : + word_type = self.word_type_codes[self.get_word_type(word)] + raise ValueError('can not convert tdc word of type %s to time' % word_type ) + tdc_value = self.get_tdc_value(word) + tdc_time = 1/self.GHZ_S_FREQ * tdc_value + return tdc_time - self.tdl_to_time(self.get_raw_tdl_values(word)) + + def disassemble_tdc_word(self, word): + # Shift away the 32 - 7 data bits and grab 3 bit word type + word_type = self.word_type_codes[self.get_word_type(word)] + if word_type in ['CALIB', 'TRIGGERED', 'RISING', 'FALLING'] : + return {'source_id' : (word >> (32 - 4)), + 'word_type' : word_type, + 'tdl_value' : word & 0b1111111, + 'fine_time_value' : self.get_tdc_value(word) % self.CLK_DIV, + 'fast_clk_value' : self.get_tdc_value(word), + 'raw_word' : word} + elif word_type == 'TIMESTAMP' : + return {'source_id' : (word >> (32 - 4)), + 'word_type' : word_type, + 'timestamp' : (word >> 9) & 0xFFFF, + 'raw_word' : word} + else : + return {'source_id' : (word >> (32 - 4)), + 'word_type' : word_type, + 'raw_word' : word} + + + def reset(self): + self.RESET = 0 + + def get_lost_data_counter(self): + return self.LOST_DATA_COUNTER + + def missed_data_counter(self): + return self.TDL_MISS_COUNTER + + def set_en(self, value): + self.ENABLE = value + + def get_en(self): + return self.ENABLE + + def set_en_extern(self, value): + self.ENABLE_EXTERN = value + + def get_en_extern(self): + return self.ENABLE_EXTERN + + def set_arming(self, value): + self.EN_ARMING = value + + def get_arming(self): + return self.EN_ARMING + + def set_write_timestamp(self, value): + self.EN_WRITE_TIMESTAMP = value + + def get_write_timestamp(self): + return self.EN_WRITE_TIMESTAMP + + def get_event_counter(self): + return self.EVENT_COUNTER + diff --git a/basil/TL/SiSim.py b/basil/TL/SiSim.py index 467a9df6..0964115a 100644 --- a/basil/TL/SiSim.py +++ b/basil/TL/SiSim.py @@ -40,7 +40,7 @@ def init(self): port = self._init['port'] # try few times for simulator to setup - try_cnt = 60 + try_cnt = 120 if 'timeout' in self._init.keys(): try_cnt = self._init['timeout'] diff --git a/basil/firmware/modules/tdl_tdc/clk_divide.v b/basil/firmware/modules/tdl_tdc/clk_divide.v new file mode 100644 index 00000000..60a2281e --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/clk_divide.v @@ -0,0 +1,23 @@ +module clk_divide( + input wire CLK_IN, + output wire calib_sig +); +parameter CLK_DIVISOR = 3; // Actually the clock is divided by this factor, times two +localparam index_bits = $clog2(CLK_DIVISOR); + +reg [index_bits:0] count_index; + +reg pulse = 0; + +always @(posedge CLK_IN) begin + if (count_index == CLK_DIVISOR) begin + count_index <= 0; + pulse <= ~pulse; + end else begin + count_index <= count_index + 1; + end +end + +assign calib_sig = pulse; + +endmodule diff --git a/basil/firmware/modules/tdl_tdc/controller.v b/basil/firmware/modules/tdl_tdc/controller.v new file mode 100644 index 00000000..84d2e8eb --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/controller.v @@ -0,0 +1,226 @@ +// Main state machine of the tdc. Contains the logic for switching the +// multiplexer, controling the corse counter, arming, calibration +// states and the trigger distance mode. Furthermore counts successful events +// and tdl misses. +module controller ( + input wire CLK, + input wire rst, + input wire [1:0] hit_status, + input wire tdl_status, + input wire arm_flag, + input wire en, + input wire en_arm_mode, + input wire en_calib_mode, + input wire en_write_trigger_distance, + + output reg counter_count, + output reg counter_reset, + output wire [state_bits-1:0] tdc_state, + output reg [7:0] miss_cnt, + output reg [31:0] event_cnt, + output reg [mux_bits-1:0] mux_addr +); + +parameter state_bits = 4; +parameter mux_bits =2; + +// 2 bit flag to store hit and miss information of the group of +// samples. This needs to be in sync with the sample deser +localparam TDL_IDLE = 0; +localparam TDL_HIT = 1; +localparam TDL_MISSED = 2; + +// Input Mux addresses +// These need to be in sync with the tdc core. +localparam TRIG_IN = 0; +localparam SIG_IN = 1; +localparam SIG_IN_B = 2; +localparam CALIB_OSC = 3; + +function [state_bits-1:0] int_to_gray; + input [state_bits-1:0] int; + begin + int_to_gray = int ^ (int >> 1); + end +endfunction +// TDC states +// These need to be in sync with the word broker. +localparam [state_bits-1:0] IDLE = 0; +localparam [state_bits-1:0] IDLE_TRIG = 1; +localparam [state_bits-1:0] TRIGGERED = 2; +localparam [state_bits-1:0] RIS_EDGE = 3; +localparam [state_bits-1:0] FAL_EDGE = 4; +localparam [state_bits-1:0] MISSED = 6; +localparam [state_bits-1:0] CALIB = 7; +localparam [state_bits-1:0] CALIB_HIT = 8; +localparam [state_bits-1:0] RESET = 9; + + +reg [state_bits-1:0] state = 0; +reg [state_bits-1:0] previous_state = 0; +always @(posedge CLK) begin + previous_state <= state; +end + +assign tdc_state = state; +wire hit; +assign hit = (hit_status == TDL_HIT) && tdl_status; + + + + +always @(state, en_write_trigger_distance) begin + // State dependent control outputs + case(state) + RESET: begin + mux_addr <= TRIG_IN; + counter_reset <= 1; + counter_count <= 0; + end + IDLE: begin + mux_addr <= SIG_IN; + counter_reset <= 1; + counter_count <= 0; + end + IDLE_TRIG: begin + mux_addr <= TRIG_IN; + counter_reset <= 1; + counter_count <= 0; + end + TRIGGERED: begin + mux_addr <= SIG_IN; + counter_reset <= 0; + counter_count <= 1; + end + RIS_EDGE: begin + mux_addr <= SIG_IN_B; + counter_reset <= 0; + counter_count <= 1; + end + FAL_EDGE: begin + if (en_write_trigger_distance) + mux_addr <= TRIG_IN; + else + mux_addr <= SIG_IN; + counter_reset <= 1; + counter_count <= 0; + end + CALIB: begin + mux_addr <= CALIB_OSC; + counter_reset <= 1; + counter_count <= 0; + end + CALIB_HIT: begin + mux_addr <= CALIB_OSC; + counter_reset <= 1; + counter_count <= 0; + end + MISSED: begin + counter_reset <= 1; + counter_count <= 0; + mux_addr <= TRIG_IN; + end + default: begin + mux_addr <= TRIG_IN; + counter_reset <= 1; + counter_count <= 0; + end + endcase +end + +always @(posedge CLK) begin + // State dependent counting of events + case(state) + RESET: begin + event_cnt <= 0; + miss_cnt <= 0; + end + IDLE: begin + if (previous_state == FAL_EDGE) + event_cnt <= event_cnt + 1; // This is really a multicycle path: Only every 4 cycles can this occur. + end + IDLE_TRIG: begin + if (previous_state == FAL_EDGE) + event_cnt <= event_cnt + 1; // This is really a multicycle path: Only every 4 cycles can this occur. + end + MISSED: + miss_cnt <= miss_cnt + 1; + endcase +end + +wire armed; +reg arm_flag_latch; +assign armed = en_arm_mode?arm_flag_latch:1; + +// State transitions +always @(posedge CLK) begin + arm_flag_latch <= arm_flag | arm_flag_latch; + // Interrupt-style state transitions + if (rst) begin + state <= RESET; + arm_flag_latch <= 0; + end else if (~en) begin + state <= IDLE; + end else if (hit_status == TDL_MISSED) begin + state <= MISSED; + end else begin + // Regular state-dependent transition + case(state) + IDLE: begin + if (en_calib_mode) begin + state <= CALIB; + end else if (en_write_trigger_distance) begin + state <= IDLE_TRIG; + end else if (armed) begin + if (hit) + state <= RIS_EDGE; + end else begin + state <= state; + end + end + IDLE_TRIG: begin + if (en_calib_mode) begin + state <= CALIB; + end else if (~en_write_trigger_distance) begin + state <= IDLE; + end else if (armed) begin + if (hit) + state <= TRIGGERED; + end else begin + state <= state; + end + end + TRIGGERED: begin + if (hit) + state <= RIS_EDGE; + else + state <= state; + end + RIS_EDGE: begin + if (hit) + state <= FAL_EDGE; + else + state <= state; + end + FAL_EDGE: begin + arm_flag_latch <= 0; + if (en_write_trigger_distance) + state <= IDLE_TRIG; + else + state <= IDLE; + end + CALIB: begin + if (~en_calib_mode) + state <= IDLE_TRIG; + else if (hit) + state <= CALIB_HIT; + else + state <= CALIB; + end + CALIB_HIT: state <= CALIB; + MISSED: state <= IDLE_TRIG; + RESET: state <= IDLE_TRIG; + endcase + end +end +endmodule diff --git a/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl b/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl new file mode 100644 index 00000000..917c88da --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl @@ -0,0 +1,57 @@ +------------------------------------------------------------------------- +---- ---- +---- Company: University of Bonn ---- +---- Engineer: John Bieling ---- +---- ---- +------------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2015 John Bieling ---- +---- ---- +---- This program is free software; you can redistribute it and/or ---- +---- modify it under the terms of the GNU General Public License as ---- +---- published by the Free Software Foundation; either version 3 of ---- +---- the License, or (at your option) any later version. ---- +---- ---- +---- This program is distributed in the hope that it will be useful, ---- +---- but WITHOUT ANY WARRANTY; without even the implied warranty of ---- +---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ---- +---- GNU General Public License for more details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, see ---- +---- . ---- +---- ---- +------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity signal_clipper is + Port ( sig : in STD_LOGIC; + CLK : in STD_LOGIC; + clipped_sig : out STD_LOGIC := '0'); +end signal_clipper; + +architecture Behavioral of signal_clipper is +signal q1 : STD_LOGIC := '0'; +signal q2 : STD_LOGIC := '0'; + +begin + +process (CLK) is +begin + if (rising_edge(CLK)) then + q1 <= sig; + q2 <= q1; + clipped_sig <= q1 AND NOT q2; + end if; +end process; + +end Behavioral; diff --git a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.ucf b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.ucf new file mode 100644 index 00000000..638d347a --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.ucf @@ -0,0 +1,29 @@ +##--------------------------------------------------------------------- +##-- -- +##-- Company: University of Bonn -- +##-- Engineer: John Bieling -- +##-- -- +##--------------------------------------------------------------------- +##-- -- +##-- Copyright (C) 2015 John Bieling -- +##-- -- +##-- This program is free software; you can redistribute it and/or -- +##-- modify it under the terms of the GNU General Public License as -- +##-- published by the Free Software Foundation; either version 3 of -- +##-- the License, or (at your option) any later version. -- +##-- -- +##-- This program is distributed in the hope that it will be useful, -- +##-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +##-- GNU General Public License for more details. -- +##-- -- +##-- You should have received a copy of the GNU General Public -- +##-- License along with this program; if not, see -- +##-- . -- +##-- -- +##--------------------------------------------------------------------- + +TIMEGRP "SFCounter" = ffs("*/SFC_*"); +TIMESPEC TS_SlimFastCounter = FROM "SFCounter" TO "SFCounter" 40 ns; +#set_multicycle_path -setup 15 -from [get_cells -hier *SFC_*] -to [get_cells -hier *SFC_* ] +#set_multicycle_path -hold 2 -from [get_cells -hier *SFC_*] -to [get_cells -hier *SFC_* ] diff --git a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v new file mode 100644 index 00000000..a887d8b6 --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v @@ -0,0 +1,171 @@ +//`include "tdl_tdc/counter/slimfast_multioption_counter.xdc" +//`include "tdl_tdc/counter/signal_clipper.vhdl" + +//`default_nettype none +//--------------------------------------------------------------------- +//-- -- +//-- Company: University of Bonn -- +//-- Engineer: John Bieling -- +//-- -- +//--------------------------------------------------------------------- +//-- -- +//-- Copyright (C) 2015 John Bieling -- +//-- -- +//-- This program is free software; you can redistribute it and/or -- +//-- modify it under the terms of the GNU General Public License as -- +//-- published by the Free Software Foundation; either version 3 of -- +//-- the License, or (at your option) any later version. -- +//-- -- +//-- This program is distributed in the hope that it will be useful, -- +//-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +//-- GNU General Public License for more details. -- +//-- -- +//-- You should have received a copy of the GNU General Public -- +//-- License along with this program; if not, see -- +//-- . -- +//-- -- +//--------------------------------------------------------------------- + + +//-- The module can be configured with these parameters (defaults given in braces): +//-- +//-- outputwidth(32) : width of output register +//-- size(31) : Size of counter, set from 5 to outputwidth-1. (overflow bit is extra, so max (outputwidth-1) Bit) +//-- clip_count(1) : sets if the count signal is to be clipped +//-- clip_reset(1 : sets if the reset signal is to be clipped +//-- +//-- !!! IMPORTANT !!! Include slimfast_multioption_counter.ucf + + +module slimfast_multioption_counter (countClock, + count, + reset, + countout); + + parameter clip_count = 1; + parameter clip_reset = 1; + parameter size = 31; + parameter outputwidth = 32; + + input wire countClock; + input wire count; + input wire reset; + + output wire [outputwidth-1:0] countout; + + wire [size-3:0] highbits_this; + wire [size-3:0] highbits_next; + + //-- Counter + slimfast_multioption_counter_core #(.clip_count(clip_count),.clip_reset(clip_reset),.size(size),.outputwidth(outputwidth)) counter( + .countClock(countClock), + .count(count), + .reset(reset), + .highbits_this(highbits_this), + .highbits_next(highbits_next), + .countout(countout) + ); + + //-- pure combinatorial +1 operation (multi cycle path, this may take up to 40ns without breaking the counter) + assign highbits_next = highbits_this + 1; + +endmodule + + +module slimfast_multioption_counter_core (countClock, + count, + reset, + highbits_this, + highbits_next, + countout); + + parameter clip_count = 1; + parameter clip_reset = 1; + parameter size = 31; + parameter outputwidth = 32; + + + input wire countClock; + input wire count; + input wire reset; + + input wire [size-3:0] highbits_next; + output wire [size-3:0] highbits_this; + + output wire [outputwidth-1:0] countout; + + + wire final_count; + wire final_reset; + + reg [2:0] fast_counts = 3'b0; + (* KEEP = "true" *) reg [size-3:0] SFC_slow_counts = 'b0; //SFC_ prefix to make this name unique + wire [size-3:0] slow_counts_next; + + + + //-- if an if-statement compares a value to 1 (not 1'b1), it is a generate-if + generate + + //-- this is pure combinatorial + //-- after change of SFC_slow_counts, the update of slow_counts_next is allowed to take + //-- 16clk cycles of countClock + assign highbits_this = SFC_slow_counts; + assign slow_counts_next[size-4:0] = highbits_next[size-4:0]; + + //the overflow bit is counted like all the other bits, but it cannot fall back to zero + assign slow_counts_next[size-3] = highbits_next[size-3] || highbits_this[size-3]; + + if (clip_count == 0) assign final_count = count; else + if (clip_count == 1) + begin + wire clipped_count; + signal_clipper countclip ( .sig(count), .CLK(countClock), .clipped_sig(clipped_count)); + assign final_count = clipped_count; + end else begin // I added this, so that one could switch from "clipped" to "not clipped" without changing the number of flip flop stages + reg piped_count; + always@(posedge countClock) + begin + piped_count <= count; + end + assign final_count = piped_count; + end + + if (clip_reset == 0) assign final_reset = reset; else + begin + wire clipped_reset; + signal_clipper resetclip ( .sig(reset), .CLK(countClock), .clipped_sig(clipped_reset)); + assign final_reset = clipped_reset; + end + + + always@(posedge countClock) + begin + + if (final_reset == 1'b1) + begin + + fast_counts <= 0; + SFC_slow_counts <= 0; + + end else begin + + //-- uses overflow as CE, valid only one clock cycle + if (final_count == 1'b1 && fast_counts == 3'b111) begin + SFC_slow_counts <= slow_counts_next; + end + + //-- uses final_count as CE + if (final_count == 1'b1) fast_counts <= fast_counts + 1'b1; + + end + + end + + endgenerate + + assign countout[outputwidth-1] = SFC_slow_counts[size-3]; + assign countout[outputwidth-2:0] = {'b0,SFC_slow_counts[size-4:0],fast_counts}; + +endmodule diff --git a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.xdc b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.xdc new file mode 100644 index 00000000..2423e633 --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.xdc @@ -0,0 +1,31 @@ +##--------------------------------------------------------------------- +##-- -- +##-- Company: University of Bonn -- +##-- Engineer: John Bieling -- +##-- -- +##--------------------------------------------------------------------- +##-- -- +##-- Copyright (C) 2015 John Bieling -- +##-- -- +##-- This program is free software; you can redistribute it and/or -- +##-- modify it under the terms of the GNU General Public License as -- +##-- published by the Free Software Foundation; either version 3 of -- +##-- the License, or (at your option) any later version. -- +##-- -- +##-- This program is distributed in the hope that it will be useful, -- +##-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +##-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +##-- GNU General Public License for more details. -- +##-- -- +##-- You should have received a copy of the GNU General Public -- +##-- License along with this program; if not, see -- +##-- . -- +##-- -- +##--------------------------------------------------------------------- + +#TIMEGRP "SFCounter" = ffs("*/SFC_*"); +#TIMESPEC TS_SlimFastCounter = FROM "SFCounter" TO "SFCounter" 40 ns; +# We should have up to 8 cycles to do this computation, as the fast count has 3 bits +set_multicycle_path -setup -from [get_pins -hier *SFC_*/C] -to [get_pins -hier *SFC_*/D] 8; +set_multicycle_path -hold -end -from [get_pins -hier *SFC_*/C] -to [get_pins -hier *SFC_*/D] 7; + diff --git a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v new file mode 100644 index 00000000..d3dd21e9 --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v @@ -0,0 +1,95 @@ + +//--------------------------------------------------------------------- +//-- -- +//-- Company: University of Bonn -- +//-- Engineer: John Bieling -- +//-- -- +//--------------------------------------------------------------------- +//-- -- +//-- Copyright (C) 2015 John Bieling -- +//-- -- +//-- This program is free software; you can redistribute it and/or -- +//-- modify it under the terms of the GNU General Public License as -- +//-- published by the Free Software Foundation; either version 3 of -- +//-- the License, or (at your option) any later version. -- +//-- -- +//-- This program is distributed in the hope that it will be useful, -- +//-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +//-- GNU General Public License for more details. -- +//-- -- +//-- You should have received a copy of the GNU General Public -- +//-- License along with this program; if not, see -- +//-- . -- +//-- -- +//--------------------------------------------------------------------- + +module CHAIN_CELL (CINIT, CI, CO, DO, CLK); + + output wire [3:0] DO; + output wire CO; + input wire CI; + input wire CLK; + input wire CINIT; + + wire [3:0] carry_out; + + CARRY4 CARRY4_inst ( + .CO(carry_out), // 4-bit carry out + .O(), // 4-bit carry chain XOR data out + .CI(CI), // 1-bit carry cascade input + .CYINIT(CINIT), // 1-bit carry initialization + .DI(4'b0000), // 4-bit carry-MUX data in + .S(4'b1111) // 4-bit carry-MUX select input + ); + assign CO = carry_out[3]; + + (* BEL = "FFD" *) FDCE #(.INIT(1'b0)) TDL_FF_D (.D(carry_out[3]), .Q(DO[3]), .C(CLK), .CE(1'b1), .CLR(1'b0)); + (* BEL = "FFC" *) FDCE #(.INIT(1'b0)) TDL_FF_C (.D(carry_out[2]), .Q(DO[2]), .C(CLK), .CE(1'b1), .CLR(1'b0)); + (* BEL = "FFB" *) FDCE #(.INIT(1'b0)) TDL_FF_B (.D(carry_out[1]), .Q(DO[1]), .C(CLK), .CE(1'b1), .CLR(1'b0)); + (* BEL = "FFA" *) FDCE #(.INIT(1'b0)) TDL_FF_A (.D(carry_out[0]), .Q(DO[0]), .C(CLK), .CE(1'b1), .CLR(1'b0)); + +endmodule + + + +module carry_sampler_spartan6 (d, q, CLK); + + parameter bits = 74; + parameter resolution = 1; + + input wire d; + input wire CLK; + output wire [bits-1:0] q; + + wire [(bits*resolution/4)-1:0] connect; + wire [bits*resolution-1:0] register_out; + + genvar i,j; + generate + + CHAIN_CELL FirstCell( + .DO({register_out[2],register_out[3],register_out[0],register_out[1]}), + .CINIT(d), + .CI(1'b0), + .CO(connect[0]), + .CLK(CLK) + ); + + for (i=1; i < bits*resolution/4; i=i+1) begin : carry_chain + CHAIN_CELL MoreCells( + .DO({register_out[4*i+2],register_out[4*i+3],register_out[4*i+0],register_out[4*i+1]}), //swapped to avoid empty bins + .CINIT(1'b0), + .CI(connect[i-1]), + .CO(connect[i]), + .CLK(CLK) + ); + end + + for (j=0; j < bits; j=j+1) begin : carry_sampler + assign q[j] = register_out[j*resolution]; + end + + endgenerate + +endmodule diff --git a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v new file mode 100644 index 00000000..287568dc --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v @@ -0,0 +1,116 @@ +module sample_deser( + input wire CLK_FAST, + input wire CLK_SLOW, + input wire [dlyline_bits-1:0] sample_in, + + output reg [1:0 ] hit_status, + output reg [fine_time_bits-1:0] fine_time, + output reg [dlyline_bits-1:0] selected_sample +); +// We will use a 2 bit flag to store hit and miss information of the group of +// samples. This needs to be in sync with the tdc controller. +localparam IDLE = 0; +localparam HIT = 1; +localparam MISSED = 2; + + +parameter dlyline_bits = 96; +parameter internally_rising = 1'b1; +parameter fine_time_bits = 2; +parameter clk_ratio = 3; // This parameter almost works, only the mux address generation below needs to be set manually + +// shift register of delay line samples on the fast clock +integer i; +reg [dlyline_bits-1:0] samples [clk_ratio-1:0]; +always @(posedge CLK_FAST) begin + samples[0] <= sample_in; + for(i=1; i >1) ^ data; + +reg [DATA_WIDTH-1:0] gray_cdc0, gray_cdc1, data_bus_clk; +always @(posedge OUT_CLK) begin + gray_cdc0 <= gray; + gray_cdc1 <= gray_cdc0; +end + +integer i; +always @(*) begin + data_bus_clk[DATA_WIDTH-1] = gray_cdc1[DATA_WIDTH-1]; + for(i = DATA_WIDTH-2; i >= 0; i = i - 1) begin + data_bus_clk[i] = gray_cdc1[i] ^ data_bus_clk[i + 1]; + end +end + +assign data_out_clk = data_bus_clk; + +endmodule diff --git a/basil/firmware/modules/tdl_tdc/word_broker.v b/basil/firmware/modules/tdl_tdc/word_broker.v new file mode 100644 index 00000000..f80c51d5 --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/word_broker.v @@ -0,0 +1,113 @@ +module word_broker ( + input wire CLK, + input wire [counter_bits-1:0] corse_time, + input wire counter_overflow, + input wire [fine_time_bits-1:0] fine_time, + input wire [encodebits-1:0] tdl_time, + input wire [state_bits-1:0] tdc_state, + input wire en_write_timestamp, + input wire en_no_trig_err, // This is not implemented as there are no trig errors in this design. The tdl expects bubble errors. + input wire [15:0] timestamp, + + output reg out_valid, + output reg [32-1:0] out_word +); + + +parameter state_bits = 4; +parameter counter_bits = 10; +parameter encodebits = 7; +parameter fine_time_bits = 2; + + +localparam DATA_IDENTIFIER = 4'b0100; +localparam word_type_bits = 3; + +// Word type codes +localparam [word_type_bits-1:0] TRIGGERED_WORD = 0; +localparam [word_type_bits-1:0] RISING_WORD = 1; +localparam [word_type_bits-1:0] FALLING_WORD = 2; +localparam [word_type_bits-1:0] TIMESTAMP_WORD = 3; +localparam [word_type_bits-1:0] CALIB_WORD = 4; +localparam [word_type_bits-1:0] MISS_WORD = 5; +localparam [word_type_bits-1:0] RESET_WORD = 6; + +function [state_bits-1:0] int_to_gray; + input [state_bits-1:0] int; + begin + int_to_gray = int ^ (int >> 1); + end +endfunction +// TDC states +localparam [state_bits-1:0] IDLE = 0; +localparam [state_bits-1:0] IDLE_TRIG = 1; +localparam [state_bits-1:0] TRIGGERED = 2; +localparam [state_bits-1:0] RIS_EDGE = 3; +localparam [state_bits-1:0] FAL_EDGE = 4; +localparam [state_bits-1:0] FIFO_FULL = 5; +localparam [state_bits-1:0] MISSED = 6; +localparam [state_bits-1:0] CALIB = 7; +localparam [state_bits-1:0] CALIB_HIT = 8; +localparam [state_bits-1:0] RESET = 9; + + + +reg [state_bits-1:0] previous_state; +always @(posedge CLK) begin + previous_state <= tdc_state; +end + +always @(posedge CLK) begin + case({previous_state, tdc_state}) + {IDLE_TRIG, TRIGGERED}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, TRIGGERED_WORD, corse_time, fine_time, tdl_time}; + end + {IDLE, RIS_EDGE}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, RISING_WORD, corse_time, fine_time, tdl_time}; + end + {TRIGGERED,RIS_EDGE}: begin + out_valid <= 1; + if (~counter_overflow) + out_word <= {DATA_IDENTIFIER, RISING_WORD, corse_time, fine_time, tdl_time}; + else + out_word <= {DATA_IDENTIFIER, RISING_WORD, {counter_bits{1'b1}}, fine_time, tdl_time}; + end + {RIS_EDGE,FAL_EDGE}: begin + out_valid <= 1; + if (~counter_overflow) + out_word <= {DATA_IDENTIFIER, FALLING_WORD, corse_time, fine_time, tdl_time}; + else + out_word <= {DATA_IDENTIFIER, FALLING_WORD, {counter_bits{1'b1}}, fine_time, tdl_time}; + end + {FAL_EDGE,IDLE}: begin + if(en_write_timestamp) begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, TIMESTAMP_WORD, timestamp, 9'b0}; + end + else begin + out_valid <= 0; + out_word <= 0; + end + end + {MISSED, IDLE}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, MISS_WORD, 25'b0}; + end + {RESET, IDLE}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, RESET_WORD, timestamp, 9'b0}; + end + {CALIB, CALIB_HIT}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, CALIB_WORD,16'b0, fine_time, tdl_time}; + end + default: begin + out_valid <= 0; + out_word <= 0; + end + endcase +end + +endmodule diff --git a/examples/tdc_bdaq/SiTCP b/examples/tdc_bdaq/SiTCP new file mode 160000 index 00000000..9f6f22ae --- /dev/null +++ b/examples/tdc_bdaq/SiTCP @@ -0,0 +1 @@ +Subproject commit 9f6f22ae29e17663b4a93d80cd28dd3c576979c8 diff --git a/examples/tdc_bdaq/SiTCP.xdc b/examples/tdc_bdaq/SiTCP.xdc new file mode 100644 index 00000000..734543fa --- /dev/null +++ b/examples/tdc_bdaq/SiTCP.xdc @@ -0,0 +1,31 @@ +#######SiTCP####### + +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */GMII_RXBUF/cmpWrAddr*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXBUF/smpWrStatusAddr*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */GMII_TXBUF/orRdAct*/C}] -to [get_pins -hier -filter {name =~ */GMII_TXBUF/irRdAct*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */GMII_TXBUF/muxEndTgl/C}] -to [get_pins -hier -filter {name =~ */GMII_TXBUF/rsmpMuxTrnsEnd*/D}] 5.500 + +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX10Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/irMacFlowEnb/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX12Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyMac*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX13Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyMac*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX14Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyMac*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX15Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyMac*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX16Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyMac*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX17Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyMac*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX18Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyIp*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX19Data*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyIp*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX1AData*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyIp*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */SiTCP_INT_REG/regX1BData*/C}] -to [get_pins -hier -filter {name =~ */GMII_RXCNT/muxMyIp*/D}] 5.500 + +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */GMII_TXBUF/dlyBank0LastWrAddr*/C}] -to [get_pins -hier -filter {name =~ */GMII_TXBUF/rsmpBank0LastWrAddr*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */GMII_TXBUF/dlyBank1LastWrAddr*/C}] -to [get_pins -hier -filter {name =~ */GMII_TXBUF/rsmpBank1LastWrAddr*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */GMII_TXBUF/memRdReq*/C}] -to [get_pins -hier -filter {name =~ */GMII_TXBUF/irMemRdReq*/D}] 5.500 + +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */GMII_RXCNT/orMacTim*/C}] -to [get_pins -hier -filter {name =~ */GMII_TXCNT/irMacPauseTime*/D}] 5.500 +set_max_delay -datapath_only -from [get_pins -hier -filter {name =~ */GMII_RXCNT/orMacPause/C}] -to [get_pins -hier -filter {name =~ */GMII_TXCNT/irMacPauseExe_0/D}] 5.500 + +set_false_path -from [get_pins -hier -filter {name =~ */SiTCP_INT/SiTCP_RESET_OUT/C}] + + + + + diff --git a/examples/tdc_bdaq/Vivado/tdc_bdaq.xpr b/examples/tdc_bdaq/Vivado/tdc_bdaq.xpr new file mode 100644 index 00000000..a83236b4 --- /dev/null +++ b/examples/tdc_bdaq/Vivado/tdc_bdaq.xpr @@ -0,0 +1,449 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/examples/tdc_bdaq/bdaq53.xdc b/examples/tdc_bdaq/bdaq53.xdc new file mode 100644 index 00000000..65938f84 --- /dev/null +++ b/examples/tdc_bdaq/bdaq53.xdc @@ -0,0 +1,106 @@ + +create_clock -period 10.000 -name clkin -add [get_ports clkin] +create_clock -period 8.000 -name rgmii_rxc -add [get_ports rgmii_rxc] + +set_false_path -from [get_clocks CLK125PLLTX] -to [get_clocks BUS_CLK_PLL] +set_false_path -from [get_clocks BUS_CLK_PLL] -to [get_clocks CLK125PLLTX] +set_false_path -from [get_clocks BUS_CLK_PLL] -to [get_clocks rgmii_rxc] +set_false_path -from [get_clocks rgmii_rxc] -to [get_clocks BUS_CLK_PLL] +set_false_path -from [get_clocks BUS_CLK_PLL] -to [get_clocks CLK160PLL] +set_false_path -from [get_clocks CLK160PLL] -to [get_clocks BUS_CLK_PLL] +set_false_path -from [get_clocks CLK160PLL] -to [get_clocks CLK480PLL] +set_false_path -from [get_clocks BUS_CLK_PLL] -to [get_clocks CLK480PLL] +set_false_path -from [get_clocks rgmii_rxc] -to [get_clocks CLK160PLL] + +set_false_path -from [get_cells -hier -filter {NAME =~ */calib_sig_gen/* && IS_SEQUENTIAL ==1}] -to [get_cells -hier -filter {NAME =~ */i_controller/* && IS_SEQUENTIAL ==1 }] +set_false_path -from [get_cells -hier -filter {NAME =~ */input_mux_addr_buf_reg* && IS_SEQUENTIAL ==1}] -to [get_cells -hier -filter {NAME =~ */tdl_sampler/carry_chain* && IS_SEQUENTIAL ==1 }] +set_false_path -from [get_cells -hier -filter {NAME =~ */calib_sig_gen/* && IS_SEQUENTIAL ==1}] -to [get_cells -hier -filter {NAME =~ */tdl_sampler/* && IS_SEQUENTIAL ==1 }] +set_false_path -from [get_cells -hier -filter {NAME =~ */conf_en_invert_tdc_synchronizer_dv_clk/* && IS_SEQUENTIAL ==1}] -to [get_cells -hier -filter {NAME =~ */tdl_sampler/carry_chain* && IS_SEQUENTIAL ==1}] + +#NET "Clk100" +set_property PACKAGE_PIN AA4 [get_ports clkin] +set_property IOSTANDARD LVCMOS15 [get_ports clkin] + +set_property PACKAGE_PIN G9 [get_ports RESET_N] +set_property IOSTANDARD LVCMOS33 [get_ports RESET_N] +set_property PULLUP true [get_ports RESET_N] + +set_property SLEW FAST [get_ports mdio_phy_mdc] +set_property IOSTANDARD LVCMOS33 [get_ports mdio_phy_mdc] +set_property PACKAGE_PIN B25 [get_ports mdio_phy_mdc] + +set_property SLEW FAST [get_ports mdio_phy_mdio] +set_property IOSTANDARD LVCMOS33 [get_ports mdio_phy_mdio] +set_property PACKAGE_PIN B26 [get_ports mdio_phy_mdio] + +#M20 is routed to Connector C. The Ethernet PHY on th KX2 board has NO reset connection +set_property SLEW FAST [get_ports phy_rst_n] +set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n] +set_property PACKAGE_PIN M20 [get_ports phy_rst_n] + +set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc] +set_property PACKAGE_PIN G22 [get_ports rgmii_rxc] + +set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rx_ctl] +set_property PACKAGE_PIN F23 [get_ports rgmii_rx_ctl] + +set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[0]}] +set_property PACKAGE_PIN H23 [get_ports {rgmii_rxd[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[1]}] +set_property PACKAGE_PIN H24 [get_ports {rgmii_rxd[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[2]}] +set_property PACKAGE_PIN J21 [get_ports {rgmii_rxd[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_rxd[3]}] +set_property PACKAGE_PIN H22 [get_ports {rgmii_rxd[3]}] + +set_property SLEW FAST [get_ports rgmii_txc] +set_property IOSTANDARD LVCMOS33 [get_ports rgmii_txc] +set_property PACKAGE_PIN K23 [get_ports rgmii_txc] + +set_property SLEW FAST [get_ports rgmii_tx_ctl] +set_property IOSTANDARD LVCMOS33 [get_ports rgmii_tx_ctl] +set_property PACKAGE_PIN J23 [get_ports rgmii_tx_ctl] + +set_property SLEW FAST [get_ports {rgmii_txd[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[0]}] +set_property PACKAGE_PIN J24 [get_ports {rgmii_txd[0]}] +set_property SLEW FAST [get_ports {rgmii_txd[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[1]}] +set_property PACKAGE_PIN J25 [get_ports {rgmii_txd[1]}] +set_property SLEW FAST [get_ports {rgmii_txd[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[2]}] +set_property PACKAGE_PIN L22 [get_ports {rgmii_txd[2]}] +set_property SLEW FAST [get_ports {rgmii_txd[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_txd[3]}] +set_property PACKAGE_PIN K22 [get_ports {rgmii_txd[3]}] + +# LEDs +#LED 0..3 are onboard LEDs +set_property PACKAGE_PIN U9 [get_ports {LED[0]}] +set_property IOSTANDARD LVCMOS15 [get_ports {LED[0]}] +set_property PACKAGE_PIN V12 [get_ports {LED[1]}] +set_property IOSTANDARD LVCMOS15 [get_ports {LED[1]}] +set_property PACKAGE_PIN V13 [get_ports {LED[2]}] +set_property IOSTANDARD LVCMOS15 [get_ports {LED[2]}] +set_property PACKAGE_PIN W13 [get_ports {LED[3]}] +set_property IOSTANDARD LVCMOS15 [get_ports {LED[3]}] +#LED 4..7 are LEDs on the BDAQ53 base board +set_property PACKAGE_PIN E21 [get_ports {LED[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}] +set_property PACKAGE_PIN E22 [get_ports {LED[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}] +set_property PACKAGE_PIN D21 [get_ports {LED[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}] +set_property PACKAGE_PIN C22 [get_ports {LED[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}] +set_property SLEW SLOW [get_ports LED*] + +# SPI configuration flash +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] + + + + + diff --git a/examples/tdc_bdaq/tdc_bdaq.py b/examples/tdc_bdaq/tdc_bdaq.py new file mode 100644 index 00000000..1ace2051 --- /dev/null +++ b/examples/tdc_bdaq/tdc_bdaq.py @@ -0,0 +1,186 @@ +# ------------------------------------------------------------ +# SiTCP throughput test +# Reads data for a couple of seconds and displays the data rate +# +# Copyright (c) All rights reserved +# SiLab, Physics Institute, University of Bonn +# ------------------------------------------------------------ +# +import logging +import time + +import numpy as np +import matplotlib.pyplot as plt + +from basil.dut import Dut + + +def disassemble_tdc_word(word): + word_type_codes = {0: 'TRIGGERED', + 1 : 'RISING', + 2 : 'FALLING', + 3 : 'TIMESTAMP', + 4 : 'OVFLOW', + 5 : 'CALIB', + 6 : 'MISS', + 7 : 'RST'} + # Shift away the 32 - 7 data bits and grab 3 bit word type + return {'source_id' : (word >> (32 - 4)), + 'word_type' : word_type_codes[(word >> (32 - 7)) & 0b111], + 'tdl_value' : word & 0b1111111, + 'fine_value' : (word >> 7) & 0b11, + 'corse_value' : (word >> 9) & 0xFFFF} + +GHZ_S_FREQ = 0.48 +CLK_DIV = 3 + + +chip = Dut("tdc_bdaq.yaml") +chip.init() +chip['TDL_TDC'].reset() + + +chip['CONTROL']['EN'] = 0 +chip['CONTROL'].write() + +logging.info("Starting data test ...") + +chip['CONTROL']['EN'] = 1 +chip['CONTROL'].write() + +chip['TDL_TDC'].RESET =1 + +print(chip['TDL_TDC'].get_en_extern()) +print(chip['TDL_TDC'].get_arming()) +chip['TDL_TDC'].EN_TRIGGER_DIST = 0 +chip['TDL_TDC'].ENABLE = 1 +chip['TDL_TDC'].RESET=0 +chip['TDL_TDC'].EN_TRIGGER_DIST = 1 +collected_data = np.empty(0, dtype=np.uint32) +test_duration = 3 +start_time = time.time() + +chip['TDL_TDC'].EN_CALIBRATION_MOD = 1 +print(chip['TDL_TDC'].EN_CALIBRATION_MOD) + +while time.time() - start_time < test_duration: + time.sleep(.01) + + fifo_data = chip['FIFO'].get_data() + data_size = len(fifo_data) + collected_data = np.concatenate((collected_data,fifo_data), dtype=np.uint32) + for word_int in fifo_data[-1:] : + word_dict = chip['TDL_TDC'].disassemble_tdc_word(word_int) + print(word_dict) + + +chip['TDL_TDC'].EN_CALIBRATION_MOD = 0 +chip['TDL_TDC'].RESET=1 +chip['FIFO'].get_data() + +chip['CONTROL']['EN'] = 0 # stop data source +chip['CONTROL'].write() + +calib_data_indices = chip['TDL_TDC'].is_calib_word(collected_data) +print(calib_data_indices) + +calib_vector = np.ones(92) +calib_sum = np.sum(calib_vector) + +def histogram_plots(data): + if max(data) - min(data) < 1000: + d = 1 + left_of_first_bin = data.min() - float(d)/2 + right_of_last_bin = data.max() + float(d)/2 + _ = plt.hist(data, np.arange(left_of_first_bin,right_of_last_bin + d, d)) + else: + #data = np.random.choice(data,,replace=False) + _ = plt.hist(data, 1000) + plt.title("Histogram of TDL code density") + plt.show() + +if any(calib_data_indices) : + calib_values = chip['TDL_TDC'].get_raw_tdl_values(np.array(collected_data[calib_data_indices])) + print(calib_values[-20:]) + chip['TDL_TDC'].set_calib_values(calib_values) + logging.info("Calibration set using %s samples" % len(calib_values)) + + #histogram_plots(calib_values[0:int(np.floor(len(calib_values)*1/3))]) + #histogram_plots(calib_values[0:int(np.floor(len(calib_values)*2/3))]) + #histogram_plots(calib_values) + + + + + + +collected_rising = [] +collected_falling = [] +chip['CONTROL']['EN'] = 1 # start data source +chip['CONTROL'].write() +chip['FIFO'].get_data() + +chip['TDL_TDC'].EN_CALIBRATION_MOD = 0 +chip['TDL_TDC'].RESET=1 +time.sleep(0.1) +chip['TDL_TDC'].RESET=0 +chip['FIFO'].get_data() +logging.info("Ready for measurements") +chip['TDL_TDC'].EN_TRIGGER_DIST = 1 +chip['TDL_TDC'].EN_WRITE_TIMESTAMP = 0 +chip['FIFO'].get_data() + +delta_t = 0 + +def reject_outliers(data, m=2): + return data[abs(data - np.median(data)) < m] +def plot_histogram(collected, title): + d = 0.010 + left_of_first_bin = np.min(collected) - float(d)/2 + right_of_last_bin = np.max(collected) + float(d)/2 + plt.hist(collected, np.arange(left_of_first_bin, right_of_last_bin + d, d)) + plt.ylabel(title) + plt.xlabel('ns') + +while True : + time.sleep(.01) + + fifo_data = chip['FIFO'].get_data() + data_size = len(fifo_data) + for word_int in fifo_data[-8:] : + word_dict = chip['TDL_TDC'].disassemble_tdc_word(word_int) + if (word_dict['word_type'] in ['TRIGGERED', 'RISING', 'FALLING']) : + if (word_dict['word_type'] == 'TRIGGERED') : + delta_t = chip['TDL_TDC'].tdc_word_to_time(word_dict) + + word_time = chip['TDL_TDC'].tdc_word_to_time(word_dict) - delta_t + + if (word_dict['word_type'] == 'RISING'): + delta_t += word_time + print('%s Time: %.3f, Delta Time: %.3f' % (word_dict['word_type'], chip['TDL_TDC'].tdc_word_to_time(word_dict), word_time)) + print(word_dict) + + if(word_dict['word_type'] == 'RISING') : + collected_rising.append(word_time) + elif(word_dict['word_type'] == 'FALLING') : + collected_falling.append(word_time) + +# if(len(collected_falling) * len(collected_rising) > 0 and len(collected_falling) % 40 == 39) : +# rising = np.array(collected_rising) +# falling = np.array(collected_falling) +# rising_no_outliers = reject_outliers(rising) +# falling_no_outliers = reject_outliers(falling) +# n_outliers = len(collected_rising) - len(rising_no_outliers) + len(collected_falling) - len(falling_no_outliers) +# logging.info("%i outliers removed" % n_outliers) +# logging.info("Rising std: %.3f" % np.std(rising_no_outliers)) +# logging.info("Falling std: %.3f" % np.std(falling_no_outliers)) +# plt.subplot(2, 1, 1) +# plot_histogram(collected_rising, '# rising edge') +# plt.subplot(2, 1, 2) +# plot_histogram(collected_falling, '# falling edge') +# plt.tight_layout() +# plt.show() + + + + diff --git a/examples/tdc_bdaq/tdc_bdaq.v b/examples/tdc_bdaq/tdc_bdaq.v new file mode 100644 index 00000000..a97ee135 --- /dev/null +++ b/examples/tdc_bdaq/tdc_bdaq.v @@ -0,0 +1,469 @@ +// /** +// * ------------------------------------------------------------ +// * Copyright (c) All rights reserved +// * SiLab, Physics Institute, University of Bonn +// * ------------------------------------------------------------ + +`include "utils/fifo_32_to_8.v" +`include "utils/generic_fifo.v" +`include "utils/rgmii_io.v" +`include "utils/rbcp_to_bus.v" +`include "utils/bus_to_ip.v" +`include "rrp_arbiter/rrp_arbiter.v" +`include "gpio/gpio_core.v" +`include "gpio/gpio.v" +`include "tdl_tdc/tdc.v" + +module tdc_bdaq( + input wire sig_in, + input wire trig_in, + input wire RESET_N, + input wire clkin, + + output wire [3:0] rgmii_txd, + output wire rgmii_tx_ctl, + output wire rgmii_txc, + input wire [3:0] rgmii_rxd, + input wire rgmii_rx_ctl, + input wire rgmii_rxc, + output wire mdio_phy_mdc, + inout wire mdio_phy_mdio, + output wire phy_rst_n, + + output wire [7:0] LED +); + +wire RST; +wire BUS_CLK_PLL, CLK125PLLTX, CLK125PLLTX90; +wire PLL_FEEDBACK, LOCKED; + +PLLE2_BASE #( + .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW + .CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64) + .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000). + .CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). + + .CLKOUT0_DIVIDE(7), // Divide amount for CLKOUT0 (1-128) + .CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT1_DIVIDE(4), // Divide amount for CLKOUT0 (1-128) + .CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT2_DIVIDE(8), // Divide amount for CLKOUT0 (1-128) + .CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT3_DIVIDE(8), // Divide amount for CLKOUT0 (1-128) + .CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT3_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT4_DIVIDE(8), // Divide amount for CLKOUT0 (1-128) + .CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT4_PHASE(-5.625), // Phase offset for CLKOUT0 (-360.000-360.000). + + .DIVCLK_DIVIDE(1), // Master division value, (1-56) + .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999). + .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE") +) +PLLE2_BASE_BUS ( + .CLKOUT0(BUS_CLK_PLL), + .CLKOUT1(), + .CLKOUT2(CLK125PLLTX), + .CLKOUT3(CLK125PLLTX90), + .CLKOUT4(), + .CLKOUT5(), + .CLKFBOUT(PLL_FEEDBACK), + .LOCKED(LOCKED), + .CLKIN1(clkin), + .PWRDWN(0), + .RST(!RESET_N), + .CLKFBIN(PLL_FEEDBACK) +); + +wire CLK160, CLK40; +wire PLL2_FEEDBACK, LOCKED160; +PLLE2_BASE #( + .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW + .CLKFBOUT_MULT(16), // Multiply value for all CLKOUT, (2-64) + .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000). + .CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). + + .CLKOUT0_DIVIDE(10), // Divide amount for CLKOUT0 (1-128) + .CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT0_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT1_DIVIDE(10), // Divide amount for CLKOUT0 (1-128) + .CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT2_DIVIDE(40), // Divide amount for CLKOUT0 (1-128) + .CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT3_DIVIDE(8), // Divide amount for CLKOUT0 (1-128) + .CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT3_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT4_DIVIDE(8), // Divide amount for CLKOUT0 (1-128) + .CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT4_PHASE(-5.625), // Phase offset for CLKOUT0 (-360.000-360.000). + + .DIVCLK_DIVIDE(1), // Master division value, (1-56) + .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999). + .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE") +) +PLLE2_BASE_160 ( + .CLKOUT0(CLK160), + .CLKOUT1(), + .CLKOUT2(CLK40), + .CLKOUT3(), + .CLKOUT4(), + .CLKOUT5(), + .CLKFBOUT(PLL2_FEEDBACK), + .LOCKED(LOCKED160), + .CLKIN1(clkin), + .PWRDWN(0), + .RST(!RESET_N), + .CLKFBIN(PLL2_FEEDBACK) +); + +wire PLL3_FEEDBACK, LOCKED480; +wire CLK160PLL, CLK480PLL; + +PLLE2_BASE #( + .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW + .CLKFBOUT_MULT(6), // Multiply value for all CLKOUT, (2-64) + .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000). + .CLKIN1_PERIOD(6.250), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). + + .CLKOUT0_DIVIDE(6), // Divide amount for CLKOUT0 (1-128) + .CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT1_DIVIDE(2), // Divide amount for CLKOUT0 (1-128) + .CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT1_PHASE(0.000), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT2_DIVIDE(24), // Divide amount for CLKOUT0 (1-128) + .CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT3_DIVIDE(8), // Divide amount for CLKOUT0 (1-128) + .CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT3_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .CLKOUT4_DIVIDE(8), // Divide amount for CLKOUT0 (1-128) + .CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999). + .CLKOUT4_PHASE(0), // Phase offset for CLKOUT0 (-360.000-360.000). + + .DIVCLK_DIVIDE(1), // Master division value, (1-56) + .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999). + .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE") +) +PLLE2_BASE_480 ( + .CLKOUT0(CLK160PLL), + .CLKOUT1(CLK480PLL), + .CLKOUT2(), + .CLKOUT3(), + .CLKOUT4(), + .CLKOUT5(), + .CLKFBOUT(PLL3_FEEDBACK), + .LOCKED(LOCKED480), + .CLKIN1(CLK160), + .PWRDWN(0), + .RST(!RESET_N), + .CLKFBIN(PLL3_FEEDBACK) +); + + + +wire BUS_CLK; +BUFG BUFG_inst_BUS_CKL (.O(BUS_CLK), .I(BUS_CLK_PLL) ); + +wire CLK125TX, CLK125TX90, CLK125RX; +BUFG BUFG_inst_CLK125TX ( .O(CLK125TX), .I(CLK125PLLTX) ); +BUFG BUFG_inst_CLK125TX90 ( .O(CLK125TX90), .I(CLK125PLLTX90) ); +BUFG BUFG_inst_CLK125RX ( .O(CLK125RX), .I(rgmii_rxc) ); + +assign RST = !RESET_N | !LOCKED | !LOCKED160 | !LOCKED480; + + +wire gmii_tx_en; +wire [7:0] gmii_txd; +wire gmii_tx_er; +wire gmii_crs; +wire gmii_col; +wire gmii_rx_dv; +wire [7:0] gmii_rxd; +wire gmii_rx_er; +wire mdio_gem_i; +wire mdio_gem_o; +wire mdio_gem_t; +wire link_status; +wire [1:0] clock_speed; +wire duplex_status; + +rgmii_io rgmii +( + .rgmii_txd(rgmii_txd), + .rgmii_tx_ctl(rgmii_tx_ctl), + .rgmii_txc(rgmii_txc), + + .rgmii_rxd(rgmii_rxd), + .rgmii_rx_ctl(rgmii_rx_ctl), + + .gmii_txd_int(gmii_txd), // Internal gmii_txd signal. + .gmii_tx_en_int(gmii_tx_en), + .gmii_tx_er_int(gmii_tx_er), + .gmii_col_int(gmii_col), + .gmii_crs_int(gmii_crs), + .gmii_rxd_reg(gmii_rxd), // RGMII double data rate data valid. + .gmii_rx_dv_reg(gmii_rx_dv), // gmii_rx_dv_ibuf registered in IOBs. + .gmii_rx_er_reg(gmii_rx_er), // gmii_rx_er_ibuf registered in IOBs. + + .eth_link_status(link_status), + .eth_clock_speed(clock_speed), + .eth_duplex_status(duplex_status), + + // Following are generated by DCMs + .tx_rgmii_clk_int(CLK125TX), // Internal RGMII transmitter clock. + .tx_rgmii_clk90_int(CLK125TX90), // Internal RGMII transmitter clock w/ 90 deg phase + .rx_rgmii_clk_int(CLK125RX), // Internal RGMII receiver clock + + .reset(!phy_rst_n) +); + + +// Instantiate tri-state buffer for MDIO +IOBUF i_iobuf_mdio( + .O(mdio_gem_i), + .IO(mdio_phy_mdio), + .I(mdio_gem_o), + .T(mdio_gem_t) +); + +wire TCP_CLOSE_REQ; +wire TCP_OPEN_ACK; +wire RBCP_ACT, RBCP_WE, RBCP_RE; +wire [7:0] RBCP_WD, RBCP_RD; +wire [31:0] RBCP_ADDR; +wire TCP_RX_WR; +wire TCP_TX_WR; +wire [7:0] TCP_RX_DATA; +wire [7:0] TCP_TX_DATA; +wire TCP_TX_FULL; +wire RBCP_ACK; +wire SiTCP_RST; +reg [10:0] TCP_RX_WC_11B; + + +WRAP_SiTCP_GMII_XC7K_32K sitcp( + .CLK(BUS_CLK) , // in : System Clock >129MHz + .RST(RST) , // in : System reset + + .FORCE_DEFAULTn(1'b0) , // in : Load default parameters + .EXT_IP_ADDR(32'hc0a80a10) , // in : IP address[31:0] //192.168.10.16 + .EXT_TCP_PORT(16'd24) , // in : TCP port #[15:0] + .EXT_RBCP_PORT(16'd4660) , // in : RBCP port #[15:0] + .PHY_ADDR(5'd3) , // in : PHY-device MIF address[4:0] + + .EEPROM_CS() , // out : Chip select + .EEPROM_SK() , // out : Serial data clock + .EEPROM_DI() , // out : Serial write data + .EEPROM_DO(1'b0) , // in : Serial read data + + .USR_REG_X3C() , // out : Stored at 0xFFFF_FF3C + .USR_REG_X3D() , // out : Stored at 0xFFFF_FF3D + .USR_REG_X3E() , // out : Stored at 0xFFFF_FF3E + .USR_REG_X3F() , // out : Stored at 0xFFFF_FF3F + + .GMII_RSTn(phy_rst_n) , // out : PHY reset + .GMII_1000M(1'b1) , // in : GMII mode (0:MII, 1:GMII) + + .GMII_TX_CLK(CLK125TX) , // in : Tx clock + .GMII_TX_EN(gmii_tx_en) , // out : Tx enable + .GMII_TXD(gmii_txd) , // out : Tx data[7:0] + .GMII_TX_ER(gmii_tx_er) , // out : TX error + .GMII_RX_CLK(CLK125RX) , // in : Rx clock + .GMII_RX_DV(gmii_rx_dv) , // in : Rx data valid + .GMII_RXD(gmii_rxd) , // in : Rx data[7:0] + .GMII_RX_ER(gmii_rx_er) , // in : Rx error + .GMII_CRS(gmii_crs) , // in : Carrier sense + .GMII_COL(gmii_col) , // in : Collision detected + .GMII_MDC(mdio_phy_mdc) , // out : Clock for MDIO + .GMII_MDIO_IN(mdio_gem_i) , // in : Data + .GMII_MDIO_OUT(mdio_gem_o) , // out : Data + .GMII_MDIO_OE(mdio_gem_t) , // out : MDIO output enable + .SiTCP_RST(SiTCP_RST) , // out : Reset for SiTCP and related circuits + .TCP_OPEN_REQ(1'b0) , // in : Reserved input, shoud be 0 + .TCP_OPEN_ACK(TCP_OPEN_ACK) , // out : Acknowledge for open (=Socket busy) + .TCP_ERROR() , // out : TCP error, its active period is equal to MSL + .TCP_CLOSE_REQ(TCP_CLOSE_REQ) , // out : Connection close request + .TCP_CLOSE_ACK(TCP_CLOSE_REQ) , // in : Acknowledge for closing + .TCP_RX_WC({5'b1,TCP_RX_WC_11B}) , // in : Rx FIFO write count[15:0] (Unused bits should be set 1) + .TCP_RX_WR(TCP_RX_WR) , // out : Write enable + .TCP_RX_DATA(TCP_RX_DATA) , // out : Write data[7:0] + .TCP_TX_FULL(TCP_TX_FULL) , // out : Almost full flag + .TCP_TX_WR(TCP_TX_WR) , // in : Write enable + .TCP_TX_DATA(TCP_TX_DATA) , // in : Write data[7:0] + .RBCP_ACT(RBCP_ACT) , // out : RBCP active + .RBCP_ADDR(RBCP_ADDR) , // out : Address[31:0] + .RBCP_WD(RBCP_WD) , // out : Data[7:0] + .RBCP_WE(RBCP_WE) , // out : Write enable + .RBCP_RE(RBCP_RE) , // out : Read enable + .RBCP_ACK(RBCP_ACK) , // in : Access acknowledge + .RBCP_RD(RBCP_RD) // in : Read data[7:0] +); + + +wire [31:0] BUS_ADD; +wire [7:0] BUS_DATA; +wire BUS_WR, BUS_RD, BUS_RST; +assign BUS_RST = SiTCP_RST; + +rbcp_to_bus irbcp_to_bus( + .BUS_RST(BUS_RST), + .BUS_CLK(BUS_CLK), + + .RBCP_ACT(RBCP_ACT), + .RBCP_ADDR(RBCP_ADDR), + .RBCP_WD(RBCP_WD), + .RBCP_WE(RBCP_WE), + .RBCP_RE(RBCP_RE), + .RBCP_ACK(RBCP_ACK), + .RBCP_RD(RBCP_RD), + + .BUS_WR(BUS_WR), + .BUS_RD(BUS_RD), + .BUS_ADD(BUS_ADD), + .BUS_DATA(BUS_DATA) + ); + +localparam GPIO_BASEADDR = 32'h1000; +localparam GPIO_HIGHADDR = 32'h101f; +wire [7:0] GPIO; +gpio #( + .BASEADDR(GPIO_BASEADDR), + .HIGHADDR(GPIO_HIGHADDR), + .ABUSWIDTH(32), + .IO_WIDTH(8), + .IO_DIRECTION(8'hff) +) i_gpio_rx ( + .BUS_CLK(BUS_CLK), + .BUS_RST(BUS_RST), + .BUS_ADD(BUS_ADD), + .BUS_DATA(BUS_DATA[7:0]), + .BUS_RD(BUS_RD), + .BUS_WR(BUS_WR), + .IO(GPIO) +); + +wire EN, ARM; +assign EN = GPIO[0]; +assign ARM = GPIO[1]; + + +localparam TDC_BASEADDR = 32'h1020; +localparam TDC_HIGHADDR = 32'h111f; +wire [31:0] tdc_fifo_data; +tdc #( + .BASEADDR(TDC_BASEADDR), + .HIGHADDR(TDC_HIGHADDR), + .ABUSWIDTH(32), + .DATA_IDENTIFIER(4'b0100) +) i_tdc ( + .BUS_CLK(BUS_CLK), + .bus_add(BUS_ADD), + .bus_data(BUS_DATA), + .bus_rst(BUS_RST), + .bus_wr(BUS_WR), + .bus_rd(BUS_RD), + + .CLK480(CLK480PLL), + .CLK160(CLK160PLL), + .CALIB_CLK(CLK125RX), + .tdc_in(sig_in), + .trig_in(trig_in), + + .timestamp(42), + .ext_en(EN), + .arm_tdc(ARM), + .fifo_read(tdc_fifo_read), + + .fifo_empty(tdc_fifo_empty), + .fifo_data(tdc_fifo_data) +); + +wire tdc_fifo_read, tdc_fifo_empty; +wire ARB_WRITE_OUT; +wire [31:0] ARB_DATA_OUT; +wire TCP_FIFO_FULL, TCP_FIFO_EMPTY; +reg FIFO_NEXT; + +rrp_arbiter #( + .WIDTH(1) +) i_rrp_arbiter ( + .RST(BUS_RST), + .CLK(BUS_CLK), + .WRITE_REQ(!tdc_fifo_empty), + .HOLD_REQ(1'b0), // wait for writing for given stream (priority) + .DATA_IN(tdc_fifo_data), // incoming data for arbitration + .READ_GRANT(tdc_fifo_read), // indicate to stream that data has been accepted + .READY_OUT(~TCP_FIFO_FULL && FIFO_NEXT), // indicates ready for outgoing stream (input) + .WRITE_OUT(ARB_WRITE_OUT), // indicates will of write to outgoing stream + .DATA_OUT(ARB_DATA_OUT) // outgoing data stream +); + +assign TCP_TX_WR = !TCP_TX_FULL & !TCP_FIFO_EMPTY; + +fifo_32_to_8 #( + .DEPTH(128*1024) +) i_data_fifo ( + .RST(BUS_RST), + .CLK(BUS_CLK), + + .WRITE(ARB_WRITE_OUT && FIFO_NEXT), + .READ(TCP_TX_WR), + .DATA_IN(ARB_DATA_OUT), + .FULL(TCP_FIFO_FULL), + .EMPTY(TCP_FIFO_EMPTY), + .DATA_OUT(TCP_TX_DATA) +); + +reg ETH_START_SENDING, ETH_START_SENDING_temp, ETH_START_SENDING_LOCK; + + +/* ------- Main FSM ------- */ +always @(posedge BUS_CLK) begin + // wait for start condition + ETH_START_SENDING <= EN; //TCP_OPEN_ACK; + + if (ETH_START_SENDING && !ETH_START_SENDING_temp) + ETH_START_SENDING_LOCK <= 1; + ETH_START_SENDING_temp <= ETH_START_SENDING; + + // RX FIFO word counter + if (TCP_RX_WR) + TCP_RX_WC_11B <= TCP_RX_WC_11B + 1; + else + TCP_RX_WC_11B <= 11'd0; + + + // FIFO handshake + if (ETH_START_SENDING_LOCK) + FIFO_NEXT <= 1'b1; + else + FIFO_NEXT <= 1'b0; + + // stop, if connection is closed by host + if (TCP_CLOSE_REQ || !EN) + ETH_START_SENDING_LOCK <= 0; +end + +assign LED = ~{ TCP_OPEN_ACK, TCP_CLOSE_REQ, TCP_RX_WR, TCP_TX_WR, + TCP_FIFO_FULL, TCP_FIFO_EMPTY, ARB_WRITE_OUT, TCP_TX_WR}; + + +endmodule diff --git a/examples/tdc_bdaq/tdc_bdaq.xdc b/examples/tdc_bdaq/tdc_bdaq.xdc new file mode 100644 index 00000000..2c0360b0 --- /dev/null +++ b/examples/tdc_bdaq/tdc_bdaq.xdc @@ -0,0 +1,43 @@ +#TDL input +# LEMO RX_0 +#set_property PACKAGE_PIN AB22 [get_ports sig_in] +# DP_ML ("DP2") L_1_P +set_property PACKAGE_PIN C19 [get_ports sig_in] +set_property IOSTANDARD LVCMOS25 [get_ports sig_in] +# LEMO RX_1 +#set_property PACKAGE_PIN AD23 [get_ports trig_in] +# DP_ML ("DP2") L_0_P +set_property PACKAGE_PIN A18 [get_ports trig_in] +set_property IOSTANDARD LVCMOS25 [get_ports trig_in] + +# DP_ML ("DP2") connected to SelectIOs +#set_property PACKAGE_PIN C19 [get_ports DP_GPIO_P[1]] +#set_property PACKAGE_PIN E18 [get_ports DP_GPIO_P[2]] + + + +set_property LOC SLICE_X38Y3 [get_cells -hier -regexp .*FirstCell/CARRY4_inst] + + +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/hit_status[0]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/hit_status[1]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/fine_time[0]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/fine_time[1]}] + + +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/encoder/position_out[0]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/encoder/position_out[1]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/encoder/position_out[2]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/encoder/position_out[3]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/encoder/position_out[4]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/encoder/position_out[5]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/encoder/position_out[6]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/tdc_state_delayed[0]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/tdc_state_delayed[1]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/tdc_state_delayed[2]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/tdc_state_delayed[3]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/fine_time_delayed[0]}] +set_property MARK_DEBUG true [get_nets {i_tdc/i_tdc_core/fine_time_delayed[1]}] + + +set_property MARK_DEBUG true [get_nets i_tdc/en_write_trigger_distance] diff --git a/examples/tdc_bdaq/tdc_bdaq.yaml b/examples/tdc_bdaq/tdc_bdaq.yaml new file mode 100644 index 00000000..b164cb57 --- /dev/null +++ b/examples/tdc_bdaq/tdc_bdaq.yaml @@ -0,0 +1,46 @@ +# +# ------------------------------------------------------------ +# Copyright (c) All rights reserved +# SiLab, Physics Institute, University of Bonn +# ------------------------------------------------------------ +# + +transfer_layer: + - name : intf + type : SiTcp + init: + ip : "192.168.10.16" + udp_port : 4660 + tcp_port : 24 + tcp_connection : True + +hw_drivers: + - name : GPIO_DRV + type : gpio + interface : intf + base_addr : 0x1000 + size : 8 + + - name : TDL_TDC + type : tdl_tdc + interface : intf + base_addr : 0x1020 + + - name : FIFO + type : sitcp_fifo + interface : intf + base_addr : 0x200000000 + base_data_addr : 0x100000000 + +registers: + - name : CONTROL + type : StdRegister + hw_driver : GPIO_DRV + size : 8 + fields: + - name : EN + size : 1 + offset : 0 + - name : ARM + size : 1 + offset : 1 diff --git a/examples/tdc_bdaq/vivado.jou b/examples/tdc_bdaq/vivado.jou new file mode 100644 index 00000000..e1f5c994 --- /dev/null +++ b/examples/tdc_bdaq/vivado.jou @@ -0,0 +1,115 @@ +#----------------------------------------------------------- +# Vivado v2022.2 (64-bit) +# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# Start of session at: Fri May 10 17:15:45 2024 +# Process ID: 738038 +# Current directory: /users/rleiser/work/basil_branch/examples/tdc_bdaq +# Command line: vivado +# Log file: /users/rleiser/work/basil_branch/examples/tdc_bdaq/vivado.log +# Journal file: /users/rleiser/work/basil_branch/examples/tdc_bdaq/vivado.jou +# Running On: asiclab006.physik.uni-bonn.de, OS: Linux, CPU Frequency: 1701.310 MHz, CPU Physical cores: 6, Host memory: 67208 MB +#----------------------------------------------------------- +start_gui +create_project tdc_bdaq /users/rleiser/work/basil_branch/examples/tdc_bdaq/Vivado -part xc7k160tffg676-2 +add_files -norecurse /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +add_files -fileset constrs_1 -norecurse {/users/rleiser/work/basil_branch/examples/tdc_bdaq/SiTCP.xdc /users/rleiser/work/basil_branch/examples/tdc_bdaq/bdaq53.xdc /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.xdc} +update_compile_order -fileset sources_1 +launch_runs synth_1 -jobs 8 +wait_on_run synth_1 +add_files {/users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/rec_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_fsm.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_pos.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s6.v /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/.word_broker.sv /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_divider.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/fx3_if/FX3_IF.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_reset_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl /users/rleiser/work/basil_branch/basil/firmware/modules/utils/DCM_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_icon.xco /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFGDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/simple_arbiter.v /users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_ila.xco /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller.v /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.v /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_neg.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ramb_8_to_n.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fx2_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/reset_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_sbus.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/OBUFDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/BUFG_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/sbus_to_ip.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ddr_des.v /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/tcp_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/decode_8b10b.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_ch.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s6.v /users/rleiser/work/basil_branch/basil/firmware/modules/includes/log2func.v /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/pulse_gen_rising.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq.v /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tb/uartlib.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/receiver_logic.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3_noibuf.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/sync_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_8_to_32.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_multiplier.v} +update_compile_order -fileset sources_1 +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/DCM_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_8_to_32.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_sbus.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart_master.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_neg.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fx3_if/FX3_IF.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3_noibuf.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s6.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s3.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s6.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/simple_arbiter.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_divider.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fx2_to_bus.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/reset_gen.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/tcp_to_bus.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tb/uartlib.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v] -no_script -reset -force -quiet +remove_files {/users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/DCM_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq.v /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_8_to_32.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_sbus.v /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c.v /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi.v /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller.v /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_neg.v /users/rleiser/work/basil_branch/basil/firmware/modules/fx3_if/FX3_IF.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3_noibuf.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s6.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s6.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/simple_arbiter.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_divider.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fx2_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/reset_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/tcp_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/tb/uartlib.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v} +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFDS_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFGDS_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/OBUFDS_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_multiplier.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/sbus_to_ip.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart.v] -no_script -reset -force -quiet +remove_files {/users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFGDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/OBUFDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_multiplier.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/sbus_to_ip.v /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart.v} +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/receiver_logic.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ddr_des.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_pos.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_reset_sync.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_ch.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/pulse_gen_rising.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ramb_8_to_n.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_fsm.v] -no_script -reset -force -quiet +remove_files {/users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/receiver_logic.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ddr_des.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_pos.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_reset_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_ch.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/pulse_gen_rising.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ramb_8_to_n.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_fsm.v} +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/rec_sync.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/sync_master.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/decode_8b10b.v] -no_script -reset -force -quiet +remove_files {/users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/rec_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/sync_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/decode_8b10b.v} +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_sim.v] -no_script -reset -force -quiet +remove_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_sim.v +set_property include_dirs /users/rleiser/work/basil_branch/basil/firmware/modules [current_fileset] +set_property dataflow_viewer_settings "min_width=16" [current_fileset] +update_compile_order -fileset sources_1 +reset_run synth_1 +launch_runs synth_1 -jobs 8 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 8 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 8 +wait_on_run synth_1 +reset_run synth_1 +launch_runs synth_1 -jobs 8 +wait_on_run synth_1 diff --git a/examples/tdc_bdaq/vivado.log b/examples/tdc_bdaq/vivado.log new file mode 100644 index 00000000..3f2b2e49 --- /dev/null +++ b/examples/tdc_bdaq/vivado.log @@ -0,0 +1,1110 @@ +#----------------------------------------------------------- +# Vivado v2022.2 (64-bit) +# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022 +# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022 +# Start of session at: Fri May 10 17:15:45 2024 +# Process ID: 738038 +# Current directory: /users/rleiser/work/basil_branch/examples/tdc_bdaq +# Command line: vivado +# Log file: /users/rleiser/work/basil_branch/examples/tdc_bdaq/vivado.log +# Journal file: /users/rleiser/work/basil_branch/examples/tdc_bdaq/vivado.jou +# Running On: asiclab006.physik.uni-bonn.de, OS: Linux, CPU Frequency: 1701.310 MHz, CPU Physical cores: 6, Host memory: 67208 MB +#----------------------------------------------------------- +start_gui +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc702:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc702/1.4/board.xml as part xc7z020clg484-1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu104:part0:1.1 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu104/1.1/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.4/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.5 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.5/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.6 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.6/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180_es:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/es/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc702:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc702/1.4/board.xml as part xc7z020clg484-1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu104:part0:1.1 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu104/1.1/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.4/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.5 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.5/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.6 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.6/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/xilinx/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +INFO: [Common 17-14] Message 'Board 49-26' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +create_project tdc_bdaq /users/rleiser/work/basil_branch/examples/tdc_bdaq/Vivado -part xc7k160tffg676-2 +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/xilinx/Vivado/2022.2/data/ip'. +create_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 6631.676 ; gain = 58.055 ; free physical = 47645 ; free virtual = 66953 +add_files -norecurse /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +add_files -fileset constrs_1 -norecurse {/users/rleiser/work/basil_branch/examples/tdc_bdaq/SiTCP.xdc /users/rleiser/work/basil_branch/examples/tdc_bdaq/bdaq53.xdc /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.xdc} +update_compile_order -fileset sources_1 +launch_runs synth_1 -jobs 8 +WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. +[Fri May 10 17:18:56 2024] Launched synth_1... +Run output will be captured here: /users/rleiser/work/basil_branch/examples/tdc_bdaq/Vivado/tdc_bdaq.runs/synth_1/runme.log +add_files {/users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/rec_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_fsm.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_pos.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s6.v /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/.word_broker.sv /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_divider.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/fx3_if/FX3_IF.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_reset_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl /users/rleiser/work/basil_branch/basil/firmware/modules/utils/DCM_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_icon.xco /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFGDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/simple_arbiter.v /users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_ila.xco /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller.v /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.v /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_neg.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ramb_8_to_n.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fx2_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/reset_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_sbus.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/OBUFDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/BUFG_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/sbus_to_ip.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ddr_des.v /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/tcp_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/decode_8b10b.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_ch.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s6.v /users/rleiser/work/basil_branch/basil/firmware/modules/includes/log2func.v /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/pulse_gen_rising.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq.v /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tb/uartlib.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/receiver_logic.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3_noibuf.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/sync_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_8_to_32.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_multiplier.v} +CRITICAL WARNING: [IP_Flow 19-11718] IP file '/users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_icon.xco' could not be added. XCO files are no longer supported in Vivado. Please use Vivado 2021.2 or earlier to migrate XCO files to XCI format. +CRITICAL WARNING: [IP_Flow 19-3389] Failed to import IP file '/users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_icon.xco': Invalid file type specified: '/users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_icon.xco'. File must have a valid Vivado IP extension (.xci). + +CRITICAL WARNING: [Vivado 12-1464] The source file '/users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_icon.xco' cannot be added to the fileset 'sources_1'. +CRITICAL WARNING: [IP_Flow 19-11718] IP file '/users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_ila.xco' could not be added. XCO files are no longer supported in Vivado. Please use Vivado 2021.2 or earlier to migrate XCO files to XCI format. +CRITICAL WARNING: [IP_Flow 19-3389] Failed to import IP file '/users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_ila.xco': Invalid file type specified: '/users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_ila.xco'. File must have a valid Vivado IP extension (.xci). + +CRITICAL WARNING: [Vivado 12-1464] The source file '/users/rleiser/work/basil_branch/basil/firmware/modules/chipscope/chipscope_ila.xco' cannot be added to the fileset 'sources_1'. +update_compile_order -fileset sources_1 +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/DCM_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_8_to_32.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_sbus.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart_master.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_neg.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fx3_if/FX3_IF.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3_noibuf.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s6.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s3.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s6.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/simple_arbiter.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_divider.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fx2_to_bus.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/reset_gen.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/tcp_to_bus.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tb/uartlib.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v] -no_script -reset -force -quiet +remove_files {/users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_iobuf.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/DCM_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq.v /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_8_to_32.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_sbus.v /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c.v /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx.v /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi.v /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller.v /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_neg.v /users/rleiser/work/basil_branch/basil/firmware/modules/fx3_if/FX3_IF.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s3_noibuf.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_s6.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s3.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ODDR_s6.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S2_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/simple_arbiter.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync_cnt.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_divider.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fx2_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/reset_gen.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/tcp_to_bus.v /users/rleiser/work/basil_branch/basil/firmware/modules/tb/uartlib.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v} +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo_core.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFDS_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFGDS_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/OBUFDS_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_multiplier.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/sbus_to_ip.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart.v] -no_script -reset -force -quiet +remove_files {/users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/cmd_seq/cmd_seq_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/tdc_s3/tdc_s3_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/pulse_gen/pulse_gen_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_rec/seq_rec_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/spi_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/jtag_master/jtag_master_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/seq_gen/seq_gen_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/fei4_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/i2c/i2c_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/timestamp/timestamp_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/sram_fifo/sram_fifo_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/bram_fifo/bram_fifo_core.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IBUFGDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/OBUFDS_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/clock_multiplier.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/sbus_to_ip.v /users/rleiser/work/basil_branch/basil/firmware/modules/uart/uart.v} +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/receiver_logic.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ddr_des.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_pos.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_reset_sync.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_ch.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/pulse_gen_rising.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ramb_8_to_n.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_fsm.v] -no_script -reset -force -quiet +remove_files {/users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/receiver_logic.v /users/rleiser/work/basil_branch/basil/firmware/modules/spi/blk_mem_gen_8_to_1_2k.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ddr_des.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/CG_MOD_pos.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_pulse_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_reset_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/m26_rx/m26_rx_ch.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/pulse_gen_rising.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/ramb_8_to_n.v /users/rleiser/work/basil_branch/basil/firmware/modules/tlu/tlu_controller_fsm.v} +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/rec_sync.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/sync_master.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v] -no_script -reset -force -quiet +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/decode_8b10b.v] -no_script -reset -force -quiet +remove_files {/users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/rec_sync.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/sync_master.v /users/rleiser/work/basil_branch/basil/firmware/modules/utils/RAMB16_S1_S9_sim.v /users/rleiser/work/basil_branch/basil/firmware/modules/fei4_rx/decode_8b10b.v} +export_ip_user_files -of_objects [get_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_sim.v] -no_script -reset -force -quiet +remove_files /users/rleiser/work/basil_branch/basil/firmware/modules/utils/IDDR_sim.v +set_property include_dirs /users/rleiser/work/basil_branch/basil/firmware/modules [current_fileset] +set_property dataflow_viewer_settings "min_width=16" [current_fileset] +update_compile_order -fileset sources_1 +reset_run synth_1 +launch_runs synth_1 -jobs 8 +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'bus_to_ip' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'fifo_32_to_8' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gerneric_fifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gpio' [/users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v:10] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gpio_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v:8] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rbcp_to_bus' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rgmii_io' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rrp_arbiter' [/users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_sw_interface' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_sw_interface' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/.word_broker.sv:1] +WARNING: [HDL 9-3756] overwriting previous definition of interface 'SiLibUSB' [/users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v:1] +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'three_stage_synchronizer()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'bus_to_ip()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'CHAIN_CELL()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'carry_sampler_spartan6()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_syncfifo()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_fifomem()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rptr_empty()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'wptr_full()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_sync_r2w()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_sync_w2r()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'clk_divide()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'controller()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'delay_n()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'fifo_32_to_8()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'flag_domain_crossing()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gerneric_fifo()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gpio()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 10 of file /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v +Duplicate found at line 10 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gpio_core()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 8 of file /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v +Duplicate found at line 8 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'graycode_2stage_cdc()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'priority_encoder_only()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rbcp_to_bus()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rgmii_io()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rrp_arbiter()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'sample_deser()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'SiLibUSB()' found in library 'xil_defaultlib' +Duplicate found at line 13 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.v + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'slimfast_multioption_counter()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'slimfast_multioption_counter_core()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc_sw_interface()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdl_and_detector()' found in library 'xil_defaultlib' +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v + (Active) Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'word_broker()' found in library 'xil_defaultlib' +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/.word_broker.sv +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc_core()' found in library 'xil_defaultlib' +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. +[Fri May 10 17:23:58 2024] Launched synth_1... +Run output will be captured here: /users/rleiser/work/basil_branch/examples/tdc_bdaq/Vivado/tdc_bdaq.runs/synth_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 8 +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'bus_to_ip' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'fifo_32_to_8' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gerneric_fifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gpio' [/users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v:10] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gpio_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v:8] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rbcp_to_bus' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rgmii_io' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rrp_arbiter' [/users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_sw_interface' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_sw_interface' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/.word_broker.sv:1] +WARNING: [HDL 9-3756] overwriting previous definition of interface 'SiLibUSB' [/users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v:1] +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'three_stage_synchronizer()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'bus_to_ip()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'CHAIN_CELL()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'carry_sampler_spartan6()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_syncfifo()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_fifomem()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rptr_empty()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'wptr_full()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_sync_r2w()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_sync_w2r()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'clk_divide()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'controller()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'delay_n()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'fifo_32_to_8()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'flag_domain_crossing()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gerneric_fifo()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gpio()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 10 of file /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v +Duplicate found at line 10 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gpio_core()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 8 of file /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v +Duplicate found at line 8 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'graycode_2stage_cdc()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'priority_encoder_only()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rbcp_to_bus()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rgmii_io()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rrp_arbiter()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'sample_deser()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'SiLibUSB()' found in library 'xil_defaultlib' +Duplicate found at line 13 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.v + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'slimfast_multioption_counter()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'slimfast_multioption_counter_core()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc_sw_interface()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdl_and_detector()' found in library 'xil_defaultlib' +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v + (Active) Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'word_broker()' found in library 'xil_defaultlib' +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/.word_broker.sv +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc_core()' found in library 'xil_defaultlib' +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. +[Fri May 10 17:25:27 2024] Launched synth_1... +Run output will be captured here: /users/rleiser/work/basil_branch/examples/tdc_bdaq/Vivado/tdc_bdaq.runs/synth_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 8 +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'bus_to_ip' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'fifo_32_to_8' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gerneric_fifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gpio' [/users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v:10] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gpio_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v:8] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rbcp_to_bus' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rgmii_io' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rrp_arbiter' [/users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_sw_interface' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_sw_interface' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/.word_broker.sv:1] +WARNING: [HDL 9-3756] overwriting previous definition of interface 'SiLibUSB' [/users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v:1] +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'three_stage_synchronizer()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'bus_to_ip()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'CHAIN_CELL()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'carry_sampler_spartan6()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_syncfifo()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_fifomem()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rptr_empty()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'wptr_full()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_sync_r2w()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_sync_w2r()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'clk_divide()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'controller()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'delay_n()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'fifo_32_to_8()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'flag_domain_crossing()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gerneric_fifo()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gpio()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 10 of file /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v +Duplicate found at line 10 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gpio_core()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 8 of file /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v +Duplicate found at line 8 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'graycode_2stage_cdc()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'priority_encoder_only()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rbcp_to_bus()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rgmii_io()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rrp_arbiter()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'sample_deser()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'SiLibUSB()' found in library 'xil_defaultlib' +Duplicate found at line 13 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.v + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'slimfast_multioption_counter()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'slimfast_multioption_counter_core()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc_sw_interface()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdl_and_detector()' found in library 'xil_defaultlib' +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v + (Active) Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'word_broker()' found in library 'xil_defaultlib' +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/.word_broker.sv +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc_core()' found in library 'xil_defaultlib' +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. +[Fri May 10 17:26:12 2024] Launched synth_1... +Run output will be captured here: /users/rleiser/work/basil_branch/examples/tdc_bdaq/Vivado/tdc_bdaq.runs/synth_1/runme.log +reset_run synth_1 +launch_runs synth_1 -jobs 8 +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'three_stage_synchronizer' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'bus_to_ip' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'CHAIN_CELL' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:27] +WARNING: [HDL 9-3756] overwriting previous definition of module 'carry_sampler_spartan6' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v:56] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_syncfifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_fifomem' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:83] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rptr_empty' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:121] +WARNING: [HDL 9-3756] overwriting previous definition of module 'wptr_full' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:157] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_r2w' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:193] +WARNING: [HDL 9-3756] overwriting previous definition of module 'cdc_sync_w2r' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v:209] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'clk_divide' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'controller' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'delay_n' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'fifo_32_to_8' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'flag_domain_crossing' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gerneric_fifo' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gpio' [/users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v:10] +WARNING: [HDL 9-3756] overwriting previous definition of module 'gpio_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v:8] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'graycode_2stage_cdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'priority_encoder_only' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v:7] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rbcp_to_bus' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rgmii_io' [/users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'rrp_arbiter' [/users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'sample_deser' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:41] +WARNING: [HDL 9-3756] overwriting previous definition of module 'slimfast_multioption_counter_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v:76] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_sw_interface' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_sw_interface' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v:5] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdc_core' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v:11] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of module 'tdl_and_detector' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v:4] +WARNING: [HDL 9-3756] overwriting previous definition of interface 'SiLibUSB' [/users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv:12] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v:1] +WARNING: [HDL 9-3756] overwriting previous definition of module 'word_broker' [/users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/word_broker.v:1] +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'three_stage_synchronizer()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/3_stage_synchronizer.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'bus_to_ip()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/bus_to_ip.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'CHAIN_CELL()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 27 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'carry_sampler_spartan6()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 56 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_syncfifo()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_fifomem()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 83 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rptr_empty()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 121 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'wptr_full()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 157 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_sync_r2w()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 193 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'cdc_sync_w2r()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/cdc_syncfifo.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 209 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'clk_divide()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/clk_divide.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'controller()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/controller.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'delay_n()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/delay_n.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'fifo_32_to_8()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/fifo_32_to_8.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'flag_domain_crossing()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/flag_domain_crossing.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gerneric_fifo()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/generic_fifo.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gpio()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 10 of file /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio.v +Duplicate found at line 10 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'gpio_core()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 8 of file /users/rleiser/work/basil_branch/basil/firmware/modules/gpio/gpio_core.v +Duplicate found at line 8 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'graycode_2stage_cdc()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/utils/graycode_2stage_cdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'priority_encoder_only()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/priority_encoder_only.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 7 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rbcp_to_bus()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rbcp_to_bus.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rgmii_io()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/utils/rgmii_io.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'rrp_arbiter()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/rrp_arbiter/rrp_arbiter.v +Duplicate found at line 12 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'sample_deser()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'SiLibUSB()' found in library 'xil_defaultlib' +Duplicate found at line 13 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.v + (Active) Duplicate found at line 12 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tb/silbusb.sv +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'slimfast_multioption_counter()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 41 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'slimfast_multioption_counter_core()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 76 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc_sw_interface()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/sw_interface.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 5 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdl_and_detector()' found in library 'xil_defaultlib' +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v + (Active) Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdl_supersampler.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'word_broker()' found in library 'xil_defaultlib' +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +Duplicate found at line 1 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc_core()' found in library 'xil_defaultlib' +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 11 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v + (Active) Duplicate found at line 11 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc_core.v +WARNING: [filemgmt 20-1318] Duplicate Design Unit 'tdc()' found in library 'xil_defaultlib' + (Active) Duplicate found at line 4 of file /users/rleiser/work/basil_branch/basil/firmware/modules/tdl_tdc/tdc.v +Duplicate found at line 4 of file /users/rleiser/work/basil_branch/examples/tdc_bdaq/tdc_bdaq.v +WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. +[Fri May 10 17:29:48 2024] Launched synth_1... +Run output will be captured here: /users/rleiser/work/basil_branch/examples/tdc_bdaq/Vivado/tdc_bdaq.runs/synth_1/runme.log +exit +INFO: [Common 17-206] Exiting Vivado at Fri May 10 17:36:19 2024... diff --git a/sim_build/cmds.f b/sim_build/cmds.f new file mode 100644 index 00000000..3e26e00a --- /dev/null +++ b/sim_build/cmds.f @@ -0,0 +1 @@ ++timescale+1ns/1ps diff --git a/tests/Makefile b/tests/Makefile new file mode 100644 index 00000000..3e139bf3 --- /dev/null +++ b/tests/Makefile @@ -0,0 +1,53 @@ +SIMULATION_HOST?=localhost +SIMULATION_PORT?=12345 +SIMULATION_BUS?=basil.utils.sim.BasilBusDriver +SIMULATION_END_ON_DISCONNECT?=1 + +VERILOG_SOURCES = /users/rleiser/work/basil_branch/tests/test_SimTimestamp.v + +TOPLEVEL = tb +MODULE = basil.utils.sim.Test + +ICARUS_INCLUDE_DIRS = -I/users/rleiser/work/basil_branch/basil/firmware/modules -I/users/rleiser/work/basil_branch/basil/firmware/modules/includes +ICARUS_DEFINES += + +NOT_ICARUS_DEFINES = +NOT_ICARUS_INCLUDE_DIRS=+incdir+./ +incdir+/users/rleiser/work/basil_branch/basil/firmware/modules +incdir+/users/rleiser/work/basil_branch/basil/firmware/modules/includes +COMPILE_ARGS_DEFINES = +BUILD_ARGS_DEFINES = + + + +export SIMULATION_HOST +export SIMULATION_PORT +export SIMULATION_BUS +export SIMULATION_END_ON_DISCONNECT + +export COCOTB=$(shell cocotb-config --share) +#export COCOTB=$(shell SPHINX_BUILD=1 python -c "import cocotb; import os; print(os.path.dirname(os.path.dirname(os.path.abspath(cocotb.__file__))))") +#export PYTHONPATH=$(shell python -c "from distutils import sysconfig; print(sysconfig.get_python_lib())"):$(COCOTB) +#export LD_LIBRARY_PATH=/lib/x86_64-linux-gnu:$(PYTHONLIBS) +export PYTHONHOME=$(shell python -c "from distutils.sysconfig import get_config_var; print(get_config_var('prefix'))") + +ifeq ($(SIM),questa) + EXTRA_ARGS += $(NOT_ICARUS_DEFINES) + EXTRA_ARGS += $(NOT_ICARUS_INCLUDE_DIRS) +else ifeq ($(SIM),ius) + EXTRA_ARGS += $(NOT_ICARUS_DEFINES) + EXTRA_ARGS += $(NOT_ICARUS_INCLUDE_DIRS) +else + COMPILE_ARGS += $(ICARUS_DEFINES) + COMPILE_ARGS += $(ICARUS_INCLUDE_DIRS) +endif + +COMPILE_ARGS += $(COMPILE_ARGS_DEFINES) +ifeq ($(SIM), verilator) + BUILD_ARGS += $(BUILD_ARGS_DEFINES) +endif + +TOPLEVEL_LANG?=verilog +export TOPLEVEL_LANG + +include $(shell cocotb-config --makefiles)/Makefile.sim + + \ No newline at end of file diff --git a/tests/test_SimTdl_Tdc.py b/tests/test_SimTdl_Tdc.py new file mode 100644 index 00000000..ca72b1ce --- /dev/null +++ b/tests/test_SimTdl_Tdc.py @@ -0,0 +1,180 @@ +# +# ------------------------------------------------------------ +# Copyright (c) All rights reserved +# SiLab, Institute of Physics, University of Bonn +# ------------------------------------------------------------ +# + +import unittest +import os + +from basil.dut import Dut +from basil.utils.sim.utils import cocotb_compile_and_run, cocotb_compile_clean + +cnfg_yaml = """ +transfer_layer: + - name : INTF + type : SiSim + init: + host : localhost + port : 12345 + +hw_drivers: + - name : SEQ_GEN + type : seq_gen + interface : INTF + base_addr : 0x0000 + + - name : TDC0 + type : tdl_tdc + interface : INTF + base_addr : 0x8000 + + - name : TDC1 + type : tdl_tdc + interface : INTF + base_addr : 0x8100 + + - name : TDC2 + type : tdl_tdc + interface : INTF + base_addr : 0x8200 + + - name : FIFO0 + type : bram_fifo + interface : INTF + base_addr : 0x8300 + base_data_addr : 0x60000000 + + - name : FIFO1 + type : bram_fifo + interface : INTF + base_addr : 0x8400 + base_data_addr : 0x70000000 + + - name : FIFO2 + type : bram_fifo + interface : INTF + base_addr : 0x8500 + base_data_addr : 0x80000000 + +registers: + - name : SEQ + type : TrackRegister + hw_driver : SEQ_GEN + seq_width : 8 + seq_size : 65535 + tracks : + - name : TDC_TRIGGER_IN + position : 0 + - name : TDC_IN + position : 1 + - name : TDC_ARM + position : 2 + - name : TDC_EXT_EN + position : 3 + - name : S4 + position : 4 + - name : S5 + position : 5 + - name : S6 + position : 6 + - name : S7 + position : 7 +""" + + +class TestSimTdc(unittest.TestCase): + def setUp(self): + cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimTdc.v')]) + + self.chip = Dut(cnfg_yaml) + self.chip.init() + + def test_tdc(self): + self.chip['TDC0'].ENABLE = 1 + self.chip['TDC0'].EN_TRIGGER_DIST = 0 + self.chip['TDC0'].EN_TRIGGER_DIST = 1 + self.chip['SEQ'].REPEAT = 1 + + for write_timestamp in range(0,1): + for index, i in enumerate(range(1045, 1047)): + trigger_dis = 50 + length = i + 1 + trigger_dis + self.chip['SEQ'].SIZE = length + 1 + self.chip['SEQ']['TDC_IN'][trigger_dis:length + trigger_dis] = True + self.chip['SEQ']['TDC_TRIGGER_IN'][0:10] = True + self.chip['SEQ'].write(length) + self.chip['SEQ'].START + while not self.chip['SEQ'].is_ready: + pass + #self.assertEqual(self.chip['FIFO0'].get_FIFO_INT_SIZE(), 3 + write_timestamp) + + data = self.chip['FIFO0'].get_data() + data = [self.chip['TDC0'].disassemble_tdc_word(w) for w in data] + print(data); + self.assertEqual(data[0]['word_type'], 'TRIGGERED') + self.assertEqual(data[1]['word_type'], 'RISING') + self.assertEqual(data[1]['tdc_value'], trigger_dis) + self.assertEqual(data[2]['word_type'], 'FALLING') + self.assertEqual(data[2]['tdc_value'], trigger_dis + i + 1) + if write_timestamp: + self.assertEqual(data[3]['word_type'], 'TIMESTAMP') + self.asserEqual(data[3]['timestamp'], 42) + + +# def test_broadcasting(self): +# self.chip['TDC0'].ENABLE = 1 +# self.chip['TDC1'].ENABLE = 1 +# self.chip['TDC2'].ENABLE = 1 +# self.chip['TDC0'].EN_TRIGGER_DIST = 1 +# self.chip['TDC1'].EN_TRIGGER_DIST = 1 +# self.chip['TDC2'].EN_TRIGGER_DIST = 1 +# self.chip['SEQ'].REPEAT = 1 +# TDC_TRIG_DIST_MASK = 0x0FF00000 +# TDC_VALUE_MASK = 0x00000FFF +# +# for _, i in enumerate([1045, 1046, 1047]): +# offset = 50 # trigger distance +# length = i + 1 + offset +# self.chip['SEQ_GEN'].SIZE = length + 1 +# self.chip['SEQ']['TDC_IN'][offset:length + offset] = True +# self.chip['SEQ']['TDC_TRIGGER_IN'][0:10] = True +# self.chip['SEQ'].write(length) +# self.chip['SEQ'].START +# while not self.chip['SEQ_GEN'].is_ready: +# pass +# self.assertEqual(self.chip['FIFO0'].get_FIFO_INT_SIZE(), 1) +# self.assertEqual(self.chip['FIFO1'].get_FIFO_INT_SIZE(), 1) +# self.assertEqual(self.chip['FIFO2'].get_FIFO_INT_SIZE(), 1) +# +# data0 = self.chip['FIFO0'].get_data() +# data1 = self.chip['FIFO1'].get_data() +# data2 = self.chip['FIFO2'].get_data() +# +# # Check data from first TDC module +# self.assertEqual(data0[0] & TDC_VALUE_MASK, i + 1) # TDC value +# self.assertEqual((TDC_TRIG_DIST_MASK & data0[0]) >> 20, offset) # TDC trigger distance +# # Check if all TDC gave same data +# self.assertEqual(data0[0], data1[0]) # Compare TDC0 with TDC1 +# self.assertEqual(data0[0], data2[0]) # Compare TDC0 with TDC2 +# +# def test_tdc_delay(self): +# pass +# +# def test_tdc_delay_overflow(self): +# pass +# +# def test_tdc_delay_late_trigger(self): +# pass +# +# def test_tdc_arm(self): +# pass + + def tearDown(self): + self.chip.close() # let it close connection and stop simulator + cocotb_compile_clean() + + +if __name__ == '__main__': + unittest.main() diff --git a/tests/test_SimTdl_Tdc.v b/tests/test_SimTdl_Tdc.v new file mode 100644 index 00000000..1fa2e157 --- /dev/null +++ b/tests/test_SimTdl_Tdc.v @@ -0,0 +1,212 @@ +// /** +// * ------------------------------------------------------------ +// * Copyright (c) All rights reserved +// * SiLab, Institute of Physics, University of Bonn +// +// * ------------------------------------------------------------ +// */ + +`timescale 1ps / 1ps + +`include "utils/clock_multiplier.v" +`include "utils/clock_divider.v" + +`include "seq_gen/seq_gen.v" +`include "seq_gen/seq_gen_core.v" +`include "utils/ramb_8_to_n.v" + +`include "tdl_tdc/tdc.v" + +`include "bram_fifo/bram_fifo_core.v" +`include "bram_fifo/bram_fifo.v" + +`include "utils/bus_to_ip.v" + + +module tb ( + input wire BUS_CLK, + input wire BUS_RST, + input wire [31:0] BUS_ADD, + inout wire [31:0] BUS_DATA, + input wire BUS_RD, + input wire BUS_WR, + output wire BUS_BYTE_ACCESS +); + +localparam SEQ_GEN_BASEADDR = 32'h0000; +localparam SEQ_GEN_HIGHADDR = 32'h8000 - 1; + +localparam TDC_BASEADDR = 32'h8000; +localparam TDC_HIGHADDR = 32'h8100 - 1; + +localparam FIFO_BASEADDR = 32'h8300; +localparam FIFO_HIGHADDR = 32'h8400 - 1; + +localparam FIFO_BASEADDR_DATA = 32'h6000_0000; +localparam FIFO_HIGHADDR_DATA = 32'h7000_0000 - 1; + +localparam ABUSWIDTH = 32; +assign BUS_BYTE_ACCESS = BUS_ADD < 32'h6000_0000 ? 1'b1 : 1'b0; + +wire TDC_TRIGGER_IN, TDC_ARM, TDC_EXT_EN; +wire [2:0] TDC_IN; +wire [3:0] NOT_CONNECTED; +wire [7:0] SEQ_OUT; +assign NOT_CONNECTED = SEQ_OUT[7:4]; +assign TDC_TRIGGER_IN = SEQ_OUT[0]; +// Use same TDC for all TDC modules +assign TDC_IN[0] = SEQ_OUT[1]; +assign TDC_IN[1] = SEQ_OUT[1]; +assign TDC_IN[2] = SEQ_OUT[1]; +assign TDC_ARM = SEQ_OUT[2]; +assign TDC_EXT_EN = SEQ_OUT[3]; + +wire CLK_160, CLK_480, CLK_160_TO_DCM, + +DCM #( + .CLKFX_MULTIPLY(20), + .CLKFX_DIVIDE(3) +) i_dcm_1 ( + .CLK0(), .CLK180(), .CLK270(), .CLK2X(), .CLK2X180(), .CLK90(), + .CLKDV(), .CLKFX(CLK_160_TO_DCM), .CLKFX180(), .LOCKED(), .PSDONE(), .STATUS(), + .CLKFB(1'b0), .CLKIN(BUS_CLK), .DSSEN(1'b0), .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .RST(1'b0) +); + +DCM #( + .CLKFX_MULTIPLY(3), + .CLKFX_DIVIDE(1), + .CLKDV_DIVIDE(1) +) i_dcm_2 ( + .CLK0(), .CLK180(), .CLK270(), .CLK2X(), .CLK2X180(), .CLK90(), + .CLKDV(CLK_160), .CLKFX(CLK_480), .CLKFX180(), .LOCKED(), .PSDONE(), .STATUS(), + .CLKFB(1'b0), .CLKIN(CLK_160_TO_DCM), .DSSEN(1'b0), .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .RST(1'b0) +); + + +seq_gen #( + .BASEADDR(SEQ_GEN_BASEADDR), + .HIGHADDR(SEQ_GEN_HIGHADDR), + .ABUSWIDTH(ABUSWIDTH), + .MEM_BYTES(8 * 8 * 1024), + .OUT_BITS(8) +) i_seq_gen ( + .BUS_CLK(BUS_CLK), + .BUS_RST(BUS_RST), + .BUS_ADD(BUS_ADD), + .BUS_DATA(BUS_DATA[7:0]), + .BUS_RD(BUS_RD), + .BUS_WR(BUS_WR), + .SEQ_EXT_START(), + .SEQ_CLK(CLK_480), + .SEQ_OUT(SEQ_OUT) +); + + +wire [2:0] TDC_FIFO_EMPTY; +wire [31:0] TDC_FIFO_DATA [2:0]; +wire [2:0] TDC_FIFO_READ; +// First TDC module: creates fast sampled trigger signal to use it for other TDC modules. +tdc #( +.BASEADDR(TDC_BASEADDR), +.HIGHADDR(TDC_HIGHADDR), +.ABUSWIDTH(ABUSWIDTH), +.DATA_IDENTIFIER(4'b0000) +) i_tdc ( + .BUS_CLK(BUS_CLK), + .bus_add(BUS_ADD), + .bus_data(BUS_DATA[7:0]), + .bus_rst(BUS_RST), + .bus_wr(BUS_WR), + .bus_rd(BUS_RD), + + .CLK480(CLK480), + .CLK160(CLK160), + .CALIB_CLK(CLK125RX), + .tdc_in(TDC_IN[0]), + .trig_in(TDC_TRIGGER_IN), + + .timestamp(16'd42), + .ext_en(TDC_EXT_EN), + .arm_tdc(TDC_ARM), + .fifo_read(TDC_FIFO_READ[0]), + + .fifo_empty(TDC_FIFO_EMPTY[0]), + .fifo_data(TDC_FIFO_DATA[0]) +); +// Additional TDC modules: Use the fast sampled trigger signal from first TDC module. +genvar i; +generate + for (i = 1; i < 3; i = i + 1) begin: tdc_gen + tdc #( + .BASEADDR(TDC_BASEADDR + 32'h0100*i), + .HIGHADDR(TDC_HIGHADDR + 32'h0100*i), + .ABUSWIDTH(ABUSWIDTH), + .DATA_IDENTIFIER(4'b0000) + ) i_tdc ( + .BUS_CLK(BUS_CLK), + .bus_add(BUS_ADD), + .bus_data(BUS_DATA[7:0]), + .bus_rst(BUS_RST), + .bus_wr(BUS_WR), + .bus_rd(BUS_RD), + + .CLK480(CLK480), + .CLK160(CLK160), + .CALIB_CLK(CLK125RX), + .tdc_in(TDC_IN[i]), + .trig_in(TDC_TRIGGER_IN), + + .timestamp(16'd42), + .ext_en(TDC_EXT_EN), + .arm_tdc(TDC_ARM), + .fifo_read(TDC_FIFO_READ[i]), + + .fifo_empty(TDC_FIFO_EMPTY[i]), + .fifo_data(TDC_FIFO_DATA[i]) + ); + end +endgenerate + + +wire FIFO_READ [2:0], FIFO_EMPTY [2:0], FIFO_FULL [2:0]; +wire [31:0] FIFO_DATA [2:0]; +genvar k; +generate + for (k = 0; k < 3; k = k + 1) begin: bram_fifo_gen + assign FIFO_DATA[k] = TDC_FIFO_DATA[k]; + assign FIFO_EMPTY[k] = TDC_FIFO_EMPTY[k]; + assign TDC_FIFO_READ[k] = FIFO_READ[k]; + + bram_fifo #( + .BASEADDR(FIFO_BASEADDR + 32'h0100*k), + .HIGHADDR(FIFO_HIGHADDR + 32'h0100*k), + .BASEADDR_DATA(FIFO_BASEADDR_DATA + 32'h1000_0000*k), + .HIGHADDR_DATA(FIFO_HIGHADDR_DATA + 32'h1000_0000*k), + .ABUSWIDTH(ABUSWIDTH) + ) i_out_fifo ( + .BUS_CLK(BUS_CLK), + .BUS_RST(BUS_RST), + .BUS_ADD(BUS_ADD), + .BUS_DATA(BUS_DATA), + .BUS_RD(BUS_RD), + .BUS_WR(BUS_WR), + + .FIFO_READ_NEXT_OUT(FIFO_READ[k]), + .FIFO_EMPTY_IN(FIFO_EMPTY[k]), + .FIFO_DATA(FIFO_DATA[k]), + + .FIFO_NOT_EMPTY(), + .FIFO_FULL(FIFO_FULL[k]), + .FIFO_NEAR_FULL(), + .FIFO_READ_ERROR() + ); + end +endgenerate + + +initial begin + $dumpfile("tdc.vcd"); + $dumpvars(0); +end + +endmodule From 2926e452902a8ae9bb9709714a26df162d17d3ff Mon Sep 17 00:00:00 2001 From: rleiser1995 Date: Wed, 12 Jun 2024 10:08:39 +0200 Subject: [PATCH 02/13] started documentation --- Makefile | 8 +- basil/HL/tdl_tdc.py | 12 +- basil/TL/SiSim.py | 2 +- .../firmware/modules/tdl_tdc/.word_broker.sv | 94 ++++++++ basil/firmware/modules/tdl_tdc/Readme.rst | 118 +++++++++ basil/firmware/modules/tdl_tdc/controller.v | 26 +- .../tdl_tdc/counter/signal_clipper.vhdl | 11 +- .../counter/slimfast_multioption_counter.v | 174 +++++++------- .../delayline/carrysampler_spartan6_20ps.v | 17 ++ .../modules/tdl_tdc/delayline/sample_deser.v | 31 ++- basil/firmware/modules/tdl_tdc/sw_interface.v | 35 ++- basil/firmware/modules/tdl_tdc/tdc.v | 6 +- basil/firmware/modules/tdl_tdc/tdc_core.v | 34 +-- .../modules/tdl_tdc/tdl_supersampler.v | 23 +- basil/firmware/modules/tdl_tdc/tdl_tdc.v | 159 ++++++++++++ .../firmware/modules/tdl_tdc/utils/delay_n.v | 7 +- basil/firmware/modules/tdl_tdc/word_broker.v | 52 ++-- examples/tdc_bdaq/SiTCP.xdc | 1 - examples/tdc_bdaq/Vivado/tdc_bdaq.xpr | 227 +++--------------- examples/tdc_bdaq/bdaq53.xdc | 9 +- examples/tdc_bdaq/tdc_bdaq.py | 56 ++--- examples/tdc_bdaq/tdc_bdaq.xdc | 64 ++++- sim_build/cmds.f | 1 - tests/test_SimTdl_Tdc.py | 12 +- tests/test_SimTdl_Tdc.v | 2 +- 25 files changed, 732 insertions(+), 449 deletions(-) create mode 100644 basil/firmware/modules/tdl_tdc/.word_broker.sv create mode 100644 basil/firmware/modules/tdl_tdc/Readme.rst create mode 100644 basil/firmware/modules/tdl_tdc/tdl_tdc.v delete mode 100644 sim_build/cmds.f diff --git a/Makefile b/Makefile index 03405359..1787751d 100644 --- a/Makefile +++ b/Makefile @@ -1,17 +1,17 @@ SIMULATION_HOST?=localhost SIMULATION_PORT?=12345 -SIMULATION_BUS?=basil.utils.sim.BasilBusDriver +SIMULATION_BUS?=basil.utils.sim.BasilSbusDriver SIMULATION_END_ON_DISCONNECT?=1 -VERILOG_SOURCES = /users/rleiser/work/basil_branch/tests/test_SimTdc.v +VERILOG_SOURCES = /users/rleiser/work/basil_branch/tests/test_SimGpio.v TOPLEVEL = tb MODULE = basil.utils.sim.Test ICARUS_INCLUDE_DIRS = -I/users/rleiser/work/basil_branch/basil/firmware/modules -I/users/rleiser/work/basil_branch/basil/firmware/modules/includes -ICARUS_DEFINES += +ICARUS_DEFINES += -DBASIL_SBUS -NOT_ICARUS_DEFINES = +NOT_ICARUS_DEFINES = +define+BASIL_SBUS NOT_ICARUS_INCLUDE_DIRS=+incdir+./ +incdir+/users/rleiser/work/basil_branch/basil/firmware/modules +incdir+/users/rleiser/work/basil_branch/basil/firmware/modules/includes COMPILE_ARGS_DEFINES = BUILD_ARGS_DEFINES = diff --git a/basil/HL/tdl_tdc.py b/basil/HL/tdl_tdc.py index d5547138..56ace5a9 100644 --- a/basil/HL/tdl_tdc.py +++ b/basil/HL/tdl_tdc.py @@ -48,8 +48,7 @@ def __init__(self, intf, conf): def get_tdc_value(self, word): # The last 7 bit are tdl data, the first 7 bits are word type and source, so 18 bits are counter information - # Of these, the last two bits are timing wrt. the fast clock and the first 16 wrt. to the slow clock - return self.CLK_DIV*((word >> 9) & 0x0FFFF) + (((word >> 7) & 0x3)) + return word >> 7 & 0x3FFFF def get_word_type(self, word): return (word >> (32 - 7) & 0b111) @@ -68,7 +67,6 @@ def tdl_to_time(self, tdl_value) : return sample_proportion * 1/self.GHZ_S_FREQ def set_calib_values(self, calib_values) : - calib_values = np.append(calib_values,np.arange(92)) data_sort, value_counts = np.unique(calib_values % 128, return_counts = True) self.calib_vector = value_counts self.calib_sum = np.sum(value_counts) @@ -80,8 +78,8 @@ def tdc_word_to_time(self, word) : word_type = self.word_type_codes[self.get_word_type(word)] raise ValueError('can not convert tdc word of type %s to time' % word_type ) tdc_value = self.get_tdc_value(word) - tdc_time = 1/self.GHZ_S_FREQ * tdc_value - return tdc_time - self.tdl_to_time(self.get_raw_tdl_values(word)) + tdc_time = (tdc_value & 0b11) * 1/self.GHZ_S_FREQ + (tdc_value >> 2) * self.CLK_DIV/self.GHZ_S_FREQ + return tdc_time + self.tdl_to_time(self.get_raw_tdl_values(word)) def disassemble_tdc_word(self, word): # Shift away the 32 - 7 data bits and grab 3 bit word type @@ -90,8 +88,8 @@ def disassemble_tdc_word(self, word): return {'source_id' : (word >> (32 - 4)), 'word_type' : word_type, 'tdl_value' : word & 0b1111111, - 'fine_time_value' : self.get_tdc_value(word) % self.CLK_DIV, - 'fast_clk_value' : self.get_tdc_value(word), + 'counter_value' : self.get_tdc_value(word) >> 2, + 'fine_clk_value' : self.get_tdc_value(word) & 0b11, 'raw_word' : word} elif word_type == 'TIMESTAMP' : return {'source_id' : (word >> (32 - 4)), diff --git a/basil/TL/SiSim.py b/basil/TL/SiSim.py index 0964115a..6fa3e8c4 100644 --- a/basil/TL/SiSim.py +++ b/basil/TL/SiSim.py @@ -40,7 +40,7 @@ def init(self): port = self._init['port'] # try few times for simulator to setup - try_cnt = 120 + try_cnt = 15 if 'timeout' in self._init.keys(): try_cnt = self._init['timeout'] diff --git a/basil/firmware/modules/tdl_tdc/.word_broker.sv b/basil/firmware/modules/tdl_tdc/.word_broker.sv new file mode 100644 index 00000000..5c5a9cea --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/.word_broker.sv @@ -0,0 +1,94 @@ +module word_broker ( + input wire CLK, + input wire [counter_bits-1:0] corse_time, + input wire [fine_time_bits-1:0] fine_time, + input wire [encodebits-1:0] tdl_time, + input wire [state_bits-1:0] tdc_state, + input wire en_write_timestamp, + input wire en_write_trigger_distance, + input wire en_no_trig_err, // This is not implemented as there are no trig errors in this design. The tdl expects bubble errors. + input wire [15:0] timestamp, + + output reg out_valid, + output reg [32-1:0] out_word +); + + +localparam DATA_IDENTIFIER = 4'b0100; +localparam WORD_TYPE_BITS = 3; // TODO: This parameter can't be changed + +// Word type codes +localparam TRIGGERED_WORD = 3'd0; +localparam RISING_WORD = 3'd1; +localparam FALLING_WORD = 3'd2; +localparam TIMESTAMP_WORD = 3'd3; +localparam COUNTER_OVERFLOW_WORD = 3'd4; +localparam CALIB_WORD = 3'd5; +localparam MISS_WORD = 3'd6; +localparam RESET_WORD = 3'd7; + + +parameter state_bits = 4; +parameter counter_bits = 10; +parameter encodebits = 7; +parameter fine_time_bits = 2; + +reg [state_bits-1:0] previous_state; +always @(posedge CLK) begin + previous_state <= tdc_state; +end + +always @(posedge CLK) begin + case({previous_state, tdc_state}) + {IDLE, TRIGGERED}: begin + if(en_write_trigger_distance) begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, TRIGGERED_WORD, corse_time, fine_time, tdl_time}; + end + else begin + out_valid <= 0; + out_word <= 0; + end + end + {TRIGGERED,RIS_EDGE}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, RISING_WORD, corse_time, fine_time, tdl_time}; + end + {RIS_EDGE,FAL_EDGE}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, FALLING_WORD, corse_time, fine_time, tdl_time}; + end + {FAL_EDGE,IDLE}: begin + if(en_write_timestamp) begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, TIMESTAMP_WORD, timestamp, 9'b0}; + end + else begin + out_valid <= 0; + out_word <= 0; + end + end + {COUNTER_OVERFLOW, IDLE}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, COUNTER_OVERFLOW_WORD, 25'b0}; + end + {MISSED, IDLE}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, MISS_WORD, 25'b0}; + end + {RESET, IDLE}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, RESET_WORD, 25'b0}; + end + {CALIB, CALIB_HIT}: begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, CALIB_WORD,16'b0, fine_time, tdl_time}; + end + default: begin + out_valid <= 0; + out_word <= 0; + end + endcase +end + +endmodule diff --git a/basil/firmware/modules/tdl_tdc/Readme.rst b/basil/firmware/modules/tdl_tdc/Readme.rst new file mode 100644 index 00000000..2436d983 --- /dev/null +++ b/basil/firmware/modules/tdl_tdc/Readme.rst @@ -0,0 +1,118 @@ +========================================================================== +**Tdl Tdc** - Tapped Delay Line based Time to Digital Converter +========================================================================== + +---------------- +Required modules +---------------- + +* `utils/3_stage_synchronizer.v` +* `utils/flag_domain_crossing.v` +* `utils/generic_fifo.v` +* `utils/cdc_syncfifo.v` +* `utils/clock_divider.v` + +---------------- +Key TDC figures +---------------- + +* 30ps RMS accuracy +* 40ns shortest reliably detectable pulse length +* 400us dynamic range + + +---------------- +Usage +---------------- +Before use, the Tdc should be calibrated. This can be done as follows:: + + chip['TDL_TDC'].EN_CALIBRATION_MOD = 1 + time.sleep(1) + chip['TDL_TDC'].EN_CALIBRATION_MOD = 0 + + + + +This will cause the Tdc to write many ``CALIB`` words to the fifo. Subsequently any required configuration bits for the particular experiment may be set. During analysis the recorded +calibration stream is easily incorporated:: + + calib_data_indices = chip['TDL_TDC'].is_calib_word(collected_data) + + if any(calib_data_indices) : + calib_values = chip['TDL_TDC'].get_raw_tdl_values(np.array(collected_data[calib_data_indices])) + chip['TDL_TDC'].set_calib_values(calib_values) + logging.info("Calibration set using %s samples" % len(calib_values)) + +Optionally, you can view a histogram of the calibration using ``chip['TDL_TDC'].plot_calib_values(calib_values)``. + + If measurements are made over a longer time span, recalibration might be necessary, however note that the above example lumps all the calibration(s) in ``collected_data`` together. + +The calibrated basil module can then be used the following way:: + + time_word_indices = chip['TDL_TDC'].is_time_word(collected_data) + time_data = collected_data[time_word_indices] + if any(calib_data_indices) : + time_in_ns = chip['TDL_TDC'].tdc_word_to_time(time_data[0]) + + + +---------------- +Data Format +---------------- +The Tdc module uses a state machine to send various types of 32 bit data words, however the first seven bits always follow the same structure: + ++-------------------------+-------------------+---------------------------------------------------------+ +| DATA IDENTIFIER (4 bit) | WORD TYPE (3 bit) | Data (25 bits) | ++-------------------------+-------------------+---------------------------------------------------------+ + +The most important words are those carrying the measured time information. Those word types are issued in the following order:: + + [TRIGGERED] -> RISING -> FALLING -> [TIMESTAMP] + +``TRIGGERED`` is only sent if ``EN_TRIGGER_DIST``, and ``TIMESTAMP`` only if ``EN_WRITE_TIMESTAMP`` is set. +In the following, we list how the remaining 25 bits are allocated for the various words. + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +TRIGGERED, RISING, FALLING +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + + ++---------------------------------------------+---------------------------+-----------------------------+ +| 160 Mhz Counter (16 bits) | 480 Mhz Counter (2 bits) | Delay Line (7 bits) | ++---------------------------------------------+---------------------------+-----------------------------+ + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +TIMESTAMP +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +This word comes after the ``FALLING`` word, but the Timestamp is actually sampled two 160Mhz clock cycles after a measurement has been started. + + ++-------------------------------------------------------------------+-----------------------------------+ +| Timestamp (16 bits) | 0 (9 bits) | ++-------------------------------------------------------------------+-----------------------------------+ + + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +CALIB +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +If the Tdc is set for self-calibration using ``EN_CALIBRATION_MODE``, it will repeatedly send this word. + + + ++---------------------------------------------+---------------------------+-----------------------------+ +| 0 (16 bits) | 480 Mhz Counter (2 bits) | Delay Line (7 bits) | ++---------------------------------------------+---------------------------+-----------------------------+ + + +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +RESET +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +If a reset is issued to the Tdc, either as a global bus reset or through basil, this word is sent. It might be useful for resetting a state machine +decoding the words on the receiving end. The Timestamp included is sampled as soon as +the reset signal has passed the clock domain circuitry. + ++-------------------------------------------------------------------+-----------------------------------+ +| Timestamp (16 bits) | 0 (9 bits) | ++-------------------------------------------------------------------+-----------------------------------+ + diff --git a/basil/firmware/modules/tdl_tdc/controller.v b/basil/firmware/modules/tdl_tdc/controller.v index 84d2e8eb..0158b948 100644 --- a/basil/firmware/modules/tdl_tdc/controller.v +++ b/basil/firmware/modules/tdl_tdc/controller.v @@ -2,7 +2,10 @@ // multiplexer, controling the corse counter, arming, calibration // states and the trigger distance mode. Furthermore counts successful events // and tdl misses. -module controller ( +module controller #( + parameter state_bits = 4, + parameter mux_bits =2 +)( input wire CLK, input wire rst, input wire [1:0] hit_status, @@ -21,8 +24,6 @@ module controller ( output reg [mux_bits-1:0] mux_addr ); -parameter state_bits = 4; -parameter mux_bits =2; // 2 bit flag to store hit and miss information of the group of // samples. This needs to be in sync with the sample deser @@ -37,12 +38,12 @@ localparam SIG_IN = 1; localparam SIG_IN_B = 2; localparam CALIB_OSC = 3; -function [state_bits-1:0] int_to_gray; - input [state_bits-1:0] int; - begin - int_to_gray = int ^ (int >> 1); - end -endfunction +// function [state_bits-1:0] int_to_gray; +// input [state_bits-1:0] int; +// begin +// int_to_gray = int ^ (int >> 1); +// end +// endfunction // TDC states // These need to be in sync with the word broker. localparam [state_bits-1:0] IDLE = 0; @@ -64,6 +65,9 @@ end assign tdc_state = state; wire hit; +// Here we safeguard against really short (narrow) pulses triggering the +// sampling. Only if a hit was detected and on the next cycle the input is +// still a solid 1 do we count a hit. assign hit = (hit_status == TDL_HIT) && tdl_status; @@ -164,7 +168,7 @@ always @(posedge CLK) begin end else if (hit_status == TDL_MISSED) begin state <= MISSED; end else begin - // Regular state-dependent transition + // Regular state-dependent transition case(state) IDLE: begin if (en_calib_mode) begin @@ -219,7 +223,7 @@ always @(posedge CLK) begin end CALIB_HIT: state <= CALIB; MISSED: state <= IDLE_TRIG; - RESET: state <= IDLE_TRIG; + RESET: state <= IDLE; endcase end end diff --git a/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl b/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl index 917c88da..8b4565dd 100644 --- a/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl +++ b/basil/firmware/modules/tdl_tdc/counter/signal_clipper.vhdl @@ -1,4 +1,7 @@ -------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- ---- ---- Company: University of Bonn ---- ---- Engineer: John Bieling ---- @@ -21,12 +24,6 @@ ---- License along with this program; if not, see ---- ---- . ---- ---- ---- -------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. diff --git a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v index a887d8b6..e97d7719 100644 --- a/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v +++ b/basil/firmware/modules/tdl_tdc/counter/slimfast_multioption_counter.v @@ -1,5 +1,6 @@ //`include "tdl_tdc/counter/slimfast_multioption_counter.xdc" //`include "tdl_tdc/counter/signal_clipper.vhdl" +`include "utils/pulse_gen_rising.v" //`default_nettype none //--------------------------------------------------------------------- @@ -38,90 +39,87 @@ //-- !!! IMPORTANT !!! Include slimfast_multioption_counter.ucf -module slimfast_multioption_counter (countClock, - count, - reset, - countout); - - parameter clip_count = 1; - parameter clip_reset = 1; - parameter size = 31; - parameter outputwidth = 32; - - input wire countClock; - input wire count; - input wire reset; - - output wire [outputwidth-1:0] countout; - - wire [size-3:0] highbits_this; - wire [size-3:0] highbits_next; - - //-- Counter - slimfast_multioption_counter_core #(.clip_count(clip_count),.clip_reset(clip_reset),.size(size),.outputwidth(outputwidth)) counter( - .countClock(countClock), - .count(count), - .reset(reset), - .highbits_this(highbits_this), - .highbits_next(highbits_next), - .countout(countout) - ); - - //-- pure combinatorial +1 operation (multi cycle path, this may take up to 40ns without breaking the counter) - assign highbits_next = highbits_this + 1; - +module slimfast_multioption_counter #( + parameter clip_count = 1, + parameter clip_reset = 1, + parameter size = 31, + parameter outputwidth = 32 +)( + input wire countClock, + input wire count, + input wire reset, + output wire [outputwidth-1:0] countout); + + + + +wire [size-3:0] highbits_this; +wire [size-3:0] highbits_next; + +//-- Counter +slimfast_multioption_counter_core #(.clip_count(clip_count),.clip_reset(clip_reset),.size(size),.outputwidth(outputwidth)) counter( + .countClock(countClock), + .count(count), + .reset(reset), + .highbits_this(highbits_this), + .highbits_next(highbits_next), + .countout(countout) +); + +//-- pure combinatorial +1 operation (multi cycle path, this may take up to 40ns without breaking the counter) +assign highbits_next = highbits_this + 1; + endmodule module slimfast_multioption_counter_core (countClock, - count, - reset, - highbits_this, - highbits_next, - countout); - - parameter clip_count = 1; - parameter clip_reset = 1; - parameter size = 31; - parameter outputwidth = 32; - - - input wire countClock; - input wire count; - input wire reset; - - input wire [size-3:0] highbits_next; - output wire [size-3:0] highbits_this; - - output wire [outputwidth-1:0] countout; - - - wire final_count; - wire final_reset; - - reg [2:0] fast_counts = 3'b0; - (* KEEP = "true" *) reg [size-3:0] SFC_slow_counts = 'b0; //SFC_ prefix to make this name unique - wire [size-3:0] slow_counts_next; - - - - //-- if an if-statement compares a value to 1 (not 1'b1), it is a generate-if - generate - - //-- this is pure combinatorial - //-- after change of SFC_slow_counts, the update of slow_counts_next is allowed to take - //-- 16clk cycles of countClock - assign highbits_this = SFC_slow_counts; - assign slow_counts_next[size-4:0] = highbits_next[size-4:0]; - - //the overflow bit is counted like all the other bits, but it cannot fall back to zero - assign slow_counts_next[size-3] = highbits_next[size-3] || highbits_this[size-3]; - - if (clip_count == 0) assign final_count = count; else + count, + reset, + highbits_this, + highbits_next, + countout); + +parameter clip_count = 1; +parameter clip_reset = 1; +parameter size = 31; +parameter outputwidth = 32; + +input wire countClock; +input wire count; +input wire reset; + +input wire [size-3:0] highbits_next; +output wire [size-3:0] highbits_this; + +output wire [outputwidth-1:0] countout; + + +wire final_count; +wire final_reset; + +reg [2:0] fast_counts = 3'b0; +(* KEEP = "true" *) reg [size-3:0] SFC_slow_counts = 'b0; //SFC_ prefix to make this name unique +wire [size-3:0] slow_counts_next; + + + +//-- if an if-statement compares a value to 1 (not 1'b1), it is a generate-if +generate + + //-- this is pure combinatorial + //-- after change of SFC_slow_counts, the update of slow_counts_next is allowed to take + //-- 16clk cycles of countClock + assign highbits_this = SFC_slow_counts; + assign slow_counts_next[size-4:0] = highbits_next[size-4:0]; + + //the overflow bit is counted like all the other bits, but it cannot fall back to zero + assign slow_counts_next[size-3] = highbits_next[size-3] || highbits_this[size-3]; + + if (clip_count == 0) assign final_count = count; else if (clip_count == 1) begin wire clipped_count; - signal_clipper countclip ( .sig(count), .CLK(countClock), .clipped_sig(clipped_count)); + pulse_gen_rising countclip ( .in(count), .clk_in(countClock), .out(clipped_count)); assign final_count = clipped_count; end else begin // I added this, so that one could switch from "clipped" to "not clipped" without changing the number of flip flop stages reg piped_count; @@ -135,17 +133,17 @@ module slimfast_multioption_counter_core (countClock, if (clip_reset == 0) assign final_reset = reset; else begin wire clipped_reset; - signal_clipper resetclip ( .sig(reset), .CLK(countClock), .clipped_sig(clipped_reset)); + pulse_gen_rising resetclip ( .in(reset), .clk_in(countClock), .out(clipped_reset)); assign final_reset = clipped_reset; end - + always@(posedge countClock) begin - + if (final_reset == 1'b1) begin - + fast_counts <= 0; SFC_slow_counts <= 0; @@ -160,12 +158,12 @@ module slimfast_multioption_counter_core (countClock, if (final_count == 1'b1) fast_counts <= fast_counts + 1'b1; end - - end - endgenerate - - assign countout[outputwidth-1] = SFC_slow_counts[size-3]; - assign countout[outputwidth-2:0] = {'b0,SFC_slow_counts[size-4:0],fast_counts}; - + end + +endgenerate + +assign countout[outputwidth-1] = SFC_slow_counts[size-3]; +assign countout[outputwidth-2:0] = {SFC_slow_counts[size-4:0],fast_counts}; + endmodule diff --git a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v index d3dd21e9..192bd17a 100644 --- a/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v +++ b/basil/firmware/modules/tdl_tdc/delayline/carrysampler_spartan6_20ps.v @@ -62,6 +62,7 @@ module carry_sampler_spartan6 (d, q, CLK); input wire CLK; output wire [bits-1:0] q; +`ifndef SIMULATION wire [(bits*resolution/4)-1:0] connect; wire [bits*resolution-1:0] register_out; @@ -91,5 +92,21 @@ module carry_sampler_spartan6 (d, q, CLK); end endgenerate +`else + reg sim_buffer; + reg [bits-1:0] sim_out; + always @(posedge CLK) begin + sim_buffer <= d; + if (d & ~ sim_buffer) + sim_out <= 3'b001; + else if (~d & sim_buffer) + sim_out <= (1 << bits-1); + else if (d & sim_buffer) + sim_out <= {bits{1'b1}}; + else if (~d & ~sim_buffer) + sim_out <= 0; + end + assign q = sim_out; +`endif endmodule diff --git a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v index 287568dc..1392f696 100644 --- a/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v +++ b/basil/firmware/modules/tdl_tdc/delayline/sample_deser.v @@ -1,4 +1,9 @@ -module sample_deser( +module sample_deser #( +parameter dlyline_bits = 96, +parameter internally_rising = 1'b1, +parameter fine_time_bits = 2, +parameter clk_ratio = 3 // This parameter almost works, only the mux address generation below needs to be set manually +)( input wire CLK_FAST, input wire CLK_SLOW, input wire [dlyline_bits-1:0] sample_in, @@ -14,10 +19,6 @@ localparam HIT = 1; localparam MISSED = 2; -parameter dlyline_bits = 96; -parameter internally_rising = 1'b1; -parameter fine_time_bits = 2; -parameter clk_ratio = 3; // This parameter almost works, only the mux address generation below needs to be set manually // shift register of delay line samples on the fast clock integer i; @@ -30,10 +31,10 @@ always @(posedge CLK_FAST) begin end // transferring shift register contents to slow clock -reg [dlyline_bits-1:0] samples_slow [clk_ratio-1:0]; +reg [dlyline_bits-1:0] samples_160 [clk_ratio-1:0]; always @(posedge CLK_SLOW) begin for(i=0; i> 1); - end -endfunction +// function [state_bits-1:0] int_to_gray; +// input [state_bits-1:0] int; +// begin +// int_to_gray = int ^ (int >> 1); +// end +// endfunction // TDC states localparam [state_bits-1:0] IDLE = 0; localparam [state_bits-1:0] IDLE_TRIG = 1; @@ -51,6 +52,11 @@ localparam [state_bits-1:0] CALIB_HIT = 8; localparam [state_bits-1:0] RESET = 9; +wire counter_overflow; +assign counter_overflow = corse_count[counter_bits-1]; +wire [15:0] corse_time; +assign corse_time = corse_count[counter_bits-1:0]; + reg [state_bits-1:0] previous_state; always @(posedge CLK) begin @@ -72,19 +78,29 @@ always @(posedge CLK) begin if (~counter_overflow) out_word <= {DATA_IDENTIFIER, RISING_WORD, corse_time, fine_time, tdl_time}; else - out_word <= {DATA_IDENTIFIER, RISING_WORD, {counter_bits{1'b1}}, fine_time, tdl_time}; + out_word <= {DATA_IDENTIFIER, RISING_WORD, {(counter_bits-1){1'b1}}, {fine_time_bits{1'b1}}, tdl_time}; end {RIS_EDGE,FAL_EDGE}: begin out_valid <= 1; if (~counter_overflow) out_word <= {DATA_IDENTIFIER, FALLING_WORD, corse_time, fine_time, tdl_time}; else - out_word <= {DATA_IDENTIFIER, FALLING_WORD, {counter_bits{1'b1}}, fine_time, tdl_time}; + out_word <= {DATA_IDENTIFIER, FALLING_WORD, {(counter_bits-1){1'b1}}, {fine_time_bits{1'b1}}, tdl_time}; end {FAL_EDGE,IDLE}: begin if(en_write_timestamp) begin out_valid <= 1; - out_word <= {DATA_IDENTIFIER, TIMESTAMP_WORD, timestamp, 9'b0}; + out_word <= {DATA_IDENTIFIER, TIMESTAMP_WORD, signal_timestamp, 9'b0}; + end + else begin + out_valid <= 0; + out_word <= 0; + end + end + {FAL_EDGE,IDLE_TRIG}: begin + if(en_write_timestamp) begin + out_valid <= 1; + out_word <= {DATA_IDENTIFIER, TIMESTAMP_WORD, signal_timestamp, 9'b0}; end else begin out_valid <= 0; @@ -97,7 +113,7 @@ always @(posedge CLK) begin end {RESET, IDLE}: begin out_valid <= 1; - out_word <= {DATA_IDENTIFIER, RESET_WORD, timestamp, 9'b0}; + out_word <= {DATA_IDENTIFIER, RESET_WORD, reset_timestamp, 9'b0}; end {CALIB, CALIB_HIT}: begin out_valid <= 1; diff --git a/examples/tdc_bdaq/SiTCP.xdc b/examples/tdc_bdaq/SiTCP.xdc index 734543fa..8dd710bb 100644 --- a/examples/tdc_bdaq/SiTCP.xdc +++ b/examples/tdc_bdaq/SiTCP.xdc @@ -28,4 +28,3 @@ set_false_path -from [get_pins -hier -filter {name =~ */SiTCP_INT/SiTCP_RESET_OU - diff --git a/examples/tdc_bdaq/Vivado/tdc_bdaq.xpr b/examples/tdc_bdaq/Vivado/tdc_bdaq.xpr index a83236b4..796892d9 100644 --- a/examples/tdc_bdaq/Vivado/tdc_bdaq.xpr +++ b/examples/tdc_bdaq/Vivado/tdc_bdaq.xpr @@ -3,11 +3,11 @@ - + -