From 28f0f723d9e21953049a28146688db25ebeda9b9 Mon Sep 17 00:00:00 2001 From: ZiaCheemaGit Date: Sun, 21 Jun 2026 07:43:09 +0500 Subject: [PATCH 1/2] 2 stage pipelined cpu --- hardware/memories/boot_rom.v | 13 ++-- hardware/pc_one/pc_one.v | 2 +- .../five_stage_pipelined_rv32i_core.v | 77 +++++++++---------- hardware/processors/lib/if_id_reg.v | 27 +++++++ hardware/processors/lib/pc.v | 14 +--- software/BIOS/link.ld | 4 +- tests/hardware/pc_one/test.py | 57 ++------------ .../c-cpp_tests/test_aggressive_c.c | 52 +++++++------ 8 files changed, 111 insertions(+), 135 deletions(-) create mode 100644 hardware/processors/lib/if_id_reg.v diff --git a/hardware/memories/boot_rom.v b/hardware/memories/boot_rom.v index 931373f..12eb5ed 100644 --- a/hardware/memories/boot_rom.v +++ b/hardware/memories/boot_rom.v @@ -13,16 +13,13 @@ module boot_rom( reg [31:0] mem [0:WORDS-1]; - reg [31:0] read_word; - reg [31:0] word_index; - - always @(*) begin - read_word = mem[addr[31:2]]; - data = read_word; - word_index = pc[31:2]; - instruction = mem[word_index]; + always @(posedge clk) begin + instruction = mem[pc[31:2]]; end + assign data = mem[addr[31:2]]; + + `ifndef SYNTHESIS string program_file; initial begin diff --git a/hardware/pc_one/pc_one.v b/hardware/pc_one/pc_one.v index 190ad26..0ac1ee0 100644 --- a/hardware/pc_one/pc_one.v +++ b/hardware/pc_one/pc_one.v @@ -43,7 +43,7 @@ module pc_one( .mem_add_ram(mem_add_ram) ); - single_cycle_rv32i_core core_instance( + five_stage_pipelined_rv32i_core core_instance( .clk(clk_from_FPGA), .rst(rst_from_FPGA), .instruction_address(instr_add), diff --git a/hardware/processors/five_stage_pipelined_rv32i_core/five_stage_pipelined_rv32i_core.v b/hardware/processors/five_stage_pipelined_rv32i_core/five_stage_pipelined_rv32i_core.v index c18c70f..9a26379 100644 --- a/hardware/processors/five_stage_pipelined_rv32i_core/five_stage_pipelined_rv32i_core.v +++ b/hardware/processors/five_stage_pipelined_rv32i_core/five_stage_pipelined_rv32i_core.v @@ -1,26 +1,4 @@ `timescale 1ns / 1ps - -/** - -RV32I ISA -https://msyksphinz-self.github.io/riscv-isadoc/#_rv32i_rv64i_instructions - -Instructions which are not yet implemented but are mentioned for RV32I in the docs above -fence, fence.i -csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci -ecall, ebreak -sret, mret -wfi, sfence.vma - - -pc_mux inputs -pc + 4 -pc + immediate -for jalr pc = (rs1 + sign_extend(instruction[31:20])) << 1 -for jal pc = pc + offset sign_extend(instruction[31:12]) - -**/ - module five_stage_pipelined_rv32i_core( input clk, input rst, @@ -35,20 +13,40 @@ module five_stage_pipelined_rv32i_core( output [31:0] mem_data_to_mem ); - wire [31:0] pc_in_add, pc_out_add; + wire [31:0] pc_jump_add, pc_out_add; + assign instruction_address = pc_out_add; pc pc_instance( .clk(clk), .rst(rst), - .jump_address(pc_in_add), + .jump_address(pc_jump_add), .pc_next(pc_out_add) ); - assign instruction_address = pc_out_add; + + wire [31:0] pc_plus_4_fetch; + adder32 fetch_adder( + .in1(4), + .in2(pc_out_add), + .out(pc_plus_4_fetch) + ); + + wire [31:0] instruction_from_if_id, pc_out_add_from_if_id; + wire [1:0] pc_src_control; + if_id_reg if_id_reg_instance( + .clk(clk), + .rst(rst), + .en(1'b1), + .flush(pc_src_control != 2'b00), + .pc_in(pc_out_add), + .inst_in(instruction), + .pc_out(pc_out_add_from_if_id), + .inst_out(instruction_from_if_id) + ); wire [31:0] sign_ext_out_shifted; wire [31:0] sign_ext_out; wire [31:0] u_type_immediate, jal_offset, s_type_immediate, b_type_immediate; sign_ext_12_to_32 sign_ext_12_to_32_instance( - .instruction(instruction), + .instruction(instruction_from_if_id), .out(sign_ext_out), .b_type_immediate(b_type_immediate), .u_type_immediate(u_type_immediate), @@ -60,8 +58,8 @@ module five_stage_pipelined_rv32i_core( wire [1:0] alu_op_control, pc_src, alu_src_control; wire [2:0] mem_to_reg_control; control_unit control_unit_instance( - .opcode(instruction[6:0]), - .func3(instruction[14:12]), + .opcode(instruction_from_if_id[6:0]), + .func3(instruction_from_if_id[14:12]), .mem_read(mem_read), .mem_write(mem_write), .alu_src(alu_src_control), @@ -88,13 +86,12 @@ module five_stage_pipelined_rv32i_core( wire invert; alu_control alu_control_instance( .alu_op(alu_op_control), - .fun3(instruction[14:12]), - .fun7(instruction[31:25]), + .fun3(instruction_from_if_id[14:12]), + .fun7(instruction_from_if_id[31:25]), .out(alu_control_unit), .invert(invert) ); - wire [1:0] pc_src_control; wire zero_flag; pc_src_control pc_src_control_instance( .pc_mux_control(pc_src), @@ -106,9 +103,9 @@ module five_stage_pipelined_rv32i_core( reg_file reg_file_instance( .clk(clk), .rst(rst), - .dest_reg(instruction[11:7]), - .src1_reg(instruction[19:15]), - .src2_reg(instruction[24:20]), + .dest_reg(instruction_from_if_id[11:7]), + .src1_reg(instruction_from_if_id[19:15]), + .src2_reg(instruction_from_if_id[24:20]), .reg_write_data(reg_write_data), .reg_write_control(reg_write_control), .src1_reg_value(rs1), @@ -140,20 +137,20 @@ module five_stage_pipelined_rv32i_core( wire [31:0] pc_plus_4; adder32 adder32_instance_const4( .in1(4), - .in2(pc_out_add), + .in2(pc_out_add_from_if_id), .out(pc_plus_4) ); wire [31:0] pc_plus_immediate_out; adder32 adder32_instance_immediate( - .in1(pc_out_add), + .in1(pc_out_add_from_if_id), .in2(b_type_immediate), .out(pc_plus_immediate_out) ); wire [31:0] jal_pc; adder32 jal_adder( - .in1(pc_out_add), + .in1(pc_out_add_from_if_id), .in2(jal_offset), .out(jal_pc) ); @@ -162,18 +159,18 @@ module five_stage_pipelined_rv32i_core( assign jalr_pc = {alu_out[31:1], 1'b0}; mux_4X1 pc_mux( - .in0(pc_plus_4), + .in0(pc_plus_4_fetch), .in1(pc_plus_immediate_out), .in2(jal_pc), .in3(jalr_pc), .sel(pc_src_control), - .out(pc_in_add) + .out(pc_jump_add) ); wire [31:0] pc_plus_u_type_immediate; adder32 u_type_adder( .in1(u_type_immediate), - .in2(pc_out_add), + .in2(pc_out_add_from_if_id), .out(pc_plus_u_type_immediate) ); diff --git a/hardware/processors/lib/if_id_reg.v b/hardware/processors/lib/if_id_reg.v new file mode 100644 index 0000000..8334cab --- /dev/null +++ b/hardware/processors/lib/if_id_reg.v @@ -0,0 +1,27 @@ +module if_id_reg ( + input wire clk, + input wire rst, + input wire en, + input wire flush, + input wire [31:0] pc_in, + input wire [31:0] inst_in, + + output reg [31:0] pc_out, + output wire [31:0] inst_out +); + + reg flush_delay; + + always @(posedge clk or posedge rst) begin + if (rst) begin + pc_out <= 32'b0; + flush_delay <= 1'b0; + end else if (en) begin + pc_out <= pc_in; + flush_delay <= flush; + end + end + + assign inst_out = (flush_delay || rst) ? 32'b0 : inst_in; + +endmodule diff --git a/hardware/processors/lib/pc.v b/hardware/processors/lib/pc.v index 0093025..31c0c07 100644 --- a/hardware/processors/lib/pc.v +++ b/hardware/processors/lib/pc.v @@ -7,18 +7,12 @@ module pc( output reg [31:0] pc_next ); - reg [31:0] pc_value; - always @(posedge clk or posedge rst) begin if (rst) begin - pc_value <= 32'b0; + pc_next <= 32'b0; end else begin - pc_value <= jump_address; + pc_next <= jump_address; end end - - always @(*) begin - pc_next = pc_value; - end - -endmodule \ No newline at end of file + +endmodule diff --git a/software/BIOS/link.ld b/software/BIOS/link.ld index 384143a..9c2b5e1 100644 --- a/software/BIOS/link.ld +++ b/software/BIOS/link.ld @@ -7,8 +7,8 @@ ENTRY(_start) MEMORY { - ROM (rx) : ORIGIN = 0x0, LENGTH = 0x400 - RAM (rwx) : ORIGIN = 0x2000, LENGTH = 0x400 + ROM (rx) : ORIGIN = 0x0, LENGTH = 0x2000 + RAM (rwx) : ORIGIN = 0x2000, LENGTH = 0x2000 } /* Universal Variables */ diff --git a/tests/hardware/pc_one/test.py b/tests/hardware/pc_one/test.py index 16d4f0b..3480b09 100644 --- a/tests/hardware/pc_one/test.py +++ b/tests/hardware/pc_one/test.py @@ -67,13 +67,8 @@ async def test_basic_asm(dut): await RisingEdge(dut.clk_from_FPGA) if dut.boot_rom_instance.pc.value.to_unsigned() == 0x130: - logger.critical("Test ended control reached at label HALT") - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) await RisingEdge(dut.clk_from_FPGA) + logger.critical("Test ended control reached at label HALT") result = dut.core_instance.reg_file_instance.registers[1] try: @@ -124,12 +119,6 @@ async def test_load_asm(dut): if dut.boot_rom_instance.pc.value.to_unsigned() == 0x88: await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - logger.critical("Test Ended") test_ended = True @@ -184,13 +173,8 @@ async def test_load_neg_asm(dut): if dut.boot_rom_instance.pc.value.to_unsigned() == 0xa8: await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - - logger.critical("Test Ended") + + logger.critical("Test Ended Reached last address 0xa8") test_ended = True reg_1 = dut.core_instance.reg_file_instance.registers[1].value @@ -299,16 +283,9 @@ async def test_math_c(dut): address = 0x0 - if dut.boot_rom_instance.pc.value.to_unsigned() == 0x58: - - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) + if dut.boot_rom_instance.pc.value.to_unsigned() == 0x290: - logger.critical("Test ended PC reached 0x58") + logger.critical("Test ended PC reached 0x290") word_index = address >> 2 result = dut.ram_instance.mem[word_index].value.to_unsigned() @@ -347,7 +324,7 @@ async def test_aggressive_c(dut): logger.info("Reset released. CPU starting execution.") - threshold_clk_cycles = 10000 + threshold_clk_cycles = 2000 for _ in range(threshold_clk_cycles): @@ -358,27 +335,9 @@ async def test_aggressive_c(dut): address = 0x0 - if dut.boot_rom_instance.pc.value.to_unsigned() == 0x58: - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) + if dut.boot_rom_instance.pc.value.to_unsigned() == 0x3e4: - logger.critical("Test ended PC reached 0x58") + logger.critical("Test ended PC reached 0x3e4") result = dut.ram_instance.mem[address].value.to_unsigned() if result == 0xaaaaaaaa: diff --git a/tests/hardware/pc_one/test_cases/c-cpp_tests/test_aggressive_c.c b/tests/hardware/pc_one/test_cases/c-cpp_tests/test_aggressive_c.c index 4fe2465..38f8e0f 100644 --- a/tests/hardware/pc_one/test_cases/c-cpp_tests/test_aggressive_c.c +++ b/tests/hardware/pc_one/test_cases/c-cpp_tests/test_aggressive_c.c @@ -6,7 +6,7 @@ ram[0x0] == 0xBBBBBBBB FAIL #define G3_ADDR 0x2000 volatile int * const g3_addr = (int *)G3_ADDR; -void int_to_string(int num, char *str) { +void int_to_string_simple(int num, char *str) { int i = 0, temp = num; if (temp == 0) { @@ -39,33 +39,35 @@ void int_to_string(int num, char *str) { } } -// Function to debug -// void int_to_string(int num, char *str) { -// int i = 0, temp = num; -// if (num == 0) { -// str[i] = '0'; -// i++; -// str[i] = '\0'; -// return; -// } -// while (temp > 0) { -// str[i++] = (temp % 10) + '0'; -// temp /= 10; -// } -// str[i] = '\0'; -// // reverse string -// for (int j = 0; j < i/2; j++) { -// char t = str[j]; -// str[j] = str[i-j-1]; -// str[i-j-1] = t; -// } -// } +void int_to_string_complex(int num, char *str) { + int i = 0, temp = num; + if (num == 0) { + str[i] = '0'; + i++; + str[i] = '\0'; + return; + } + while (temp > 0) { + str[i++] = (temp % 10) + '0'; + temp /= 10; + } + str[i] = '\0'; + // reverse string + for (int j = 0; j < i/2; j++) { + char t = str[j]; + str[j] = str[i-j-1]; + str[i-j-1] = t; + } +} int bios(){ - char s[10]; - int_to_string(129, s); + char s[4]; + char c[4]; + int_to_string_simple(129, s); + int_to_string_complex(129, s); - if(s[0] == '1' && s[1] == '2' && s[2] == '9' && s[3] == '\0'){ + if (s[0] == '1' && s[1] == '2' && s[2] == '9' && s[3] == '\0' + && s[0] == c[0], s[1] == c[1], s[2] == c[2]) { *g3_addr = 0xAAAAAAAA; } else { *g3_addr = 0xBBBBBBBB; From e9f8d327da15bfa090e6091ba444536ce93fb282 Mon Sep 17 00:00:00 2001 From: ZiaCheemaGit Date: Sun, 21 Jun 2026 08:51:27 +0500 Subject: [PATCH 2/2] remove stale broken test --- tests/hardware/pc_one/test.py | 62 ----- .../test_cases/asm_tests/test_aggresive_asm.S | 219 ------------------ 2 files changed, 281 deletions(-) delete mode 100644 tests/hardware/pc_one/test_cases/asm_tests/test_aggresive_asm.S diff --git a/tests/hardware/pc_one/test.py b/tests/hardware/pc_one/test.py index 3480b09..3680efc 100644 --- a/tests/hardware/pc_one/test.py +++ b/tests/hardware/pc_one/test.py @@ -187,68 +187,6 @@ async def test_load_neg_asm(dut): assert False, "Test Ended Abnormally" -@program_test("test_aggresive_asm") -async def test_aggresive_asm(dut): - test_name = "test_aggresive_asm" - logger = logging.getLogger(test_name) - file_handler = logging.FileHandler(f"simulation_{test_name}.log", mode='w') - formatter = logging.Formatter('%(asctime)s - %(levelname)s - %(message)s') - file_handler.setFormatter(formatter) - logger.addHandler(file_handler) - logger.setLevel(logging.INFO) - - # run clock concurrently - cocotb.start_soon(Clock(dut.clk_from_FPGA, 1, unit="ns").start()) - - # reset cpu - dut.rst_from_FPGA.value = 1 - await RisingEdge(dut.clk_from_FPGA) - await RisingEdge(dut.clk_from_FPGA) - dut.rst_from_FPGA.value = 0 - await RisingEdge(dut.clk_from_FPGA) - - logger.info("Reset released. CPU starting execution.") - - threshold_clk_cycles = 10000 - - for _ in range(threshold_clk_cycles): - - if LOGGING_ON: - log_signals_pc_one_sync(logger, dut) - - await RisingEdge(dut.clk_from_FPGA) - - address = 0x0 - - if dut.boot_rom_instance.pc.value.to_unsigned() == 0x58: - logger.critical("Test ended PC reached 0x58") - result = dut.ram_instance.mem[address].value.to_unsigned() - - if result == 0xaaaaaaaa: - logger.critical("Test passed") - logger.critical(f"ram[0x{address}] = {result:08x}") - logger.critical("Test Passed") - - elif result == 0xbbbbbbbb: - logger.critical("Test failed with expected value") - logger.critical(f"ram[0x{address}] = {result:08x}") - - logger.critical(f"ram[0x{address + 1}] = {dut.ram_instance.mem[address+1].value.to_unsigned():08x}") - logger.critical(f"ram[0x{address + 2}] = {dut.ram_instance.mem[address+2].value.to_unsigned():08x}") - logger.critical(f"ram[0x{address + 3}] = {dut.ram_instance.mem[address+3].value.to_unsigned():08x}") - - raise Exception("Test failed with expected value") - - else: - logger.critical("Test failed with un-expected value") - logger.critical(f"ram[0x{address}] = {result:08x}") - raise Exception("Test failed with un-expected value") - - return - - raise Exception("Threshold cyles passed\nPC never reached end") - - @program_test("test_math_c") async def test_math_c(dut): diff --git a/tests/hardware/pc_one/test_cases/asm_tests/test_aggresive_asm.S b/tests/hardware/pc_one/test_cases/asm_tests/test_aggresive_asm.S deleted file mode 100644 index 6ec0a63..0000000 --- a/tests/hardware/pc_one/test_cases/asm_tests/test_aggresive_asm.S +++ /dev/null @@ -1,219 +0,0 @@ -.section .text - .globl bios - -int_to_string: - addi x2, x2, -48 - sw x1, 44(x2) - sw x8, 40(x2) - addi x8, x2, 48 - sw x10, -36(x8) - sw x11, -40(x8) - sw x0, -20(x8) - lw x15, -36(x8) - sw x15, -24(x8) - lw x15, -36(x8) - bne x15, x0, .L_int_to_string_110 - lw x15, -20(x8) - lw x14, -40(x8) - add x15, x14, x15 - addi x14, x0, 48 - sb x14, 0(x15) - lw x15, -20(x8) - addi x15, x15, 1 - sw x15, -20(x8) - lw x15, -20(x8) - lw x14, -40(x8) - add x15, x14, x15 - sb x0, 0(x15) - jal x0, .L_int_to_string_1b8 -.L_int_to_string_bc: - lw x15, -24(x8) - addi x11, x0, 10 - addi x10, x15, 0 - jal x1, __modsi3 - addi x15, x10, 0 - andi x14, x15, 255 - lw x15, -20(x8) - addi x13, x15, 1 - sw x13, -20(x8) - addi x13, x15, 0 - lw x15, -40(x8) - add x15, x15, x13 - addi x14, x14, 48 - andi x14, x14, 255 - sb x14, 0(x15) - lw x15, -24(x8) - addi x11, x0, 10 - addi x10, x15, 0 - jal x1, __divsi3 - addi x15, x10, 0 - sw x15, -24(x8) -.L_int_to_string_110: - lw x15, -24(x8) - blt x0, x15, .L_int_to_string_bc - lw x15, -20(x8) - lw x14, -40(x8) - add x15, x14, x15 - sb x0, 0(x15) - sw x0, -28(x8) - jal x0, .L_int_to_string_19c -.L_int_to_string_130: - lw x15, -28(x8) - lw x14, -40(x8) - add x15, x14, x15 - lbu x15, 0(x15) - sb x15, -29(x8) - lw x14, -20(x8) - lw x15, -28(x8) - sub x15, x14, x15 - addi x15, x15, -1 - lw x14, -40(x8) - add x14, x14, x15 - lw x15, -28(x8) - lw x13, -40(x8) - add x15, x13, x15 - lbu x14, 0(x14) - sb x14, 0(x15) - lw x14, -20(x8) - lw x15, -28(x8) - sub x15, x14, x15 - addi x15, x15, -1 - lw x14, -40(x8) - add x15, x14, x15 - lbu x14, -29(x8) - sb x14, 0(x15) - lw x15, -28(x8) - addi x15, x15, 1 - sw x15, -28(x8) -.L_int_to_string_19c: - lw x15, -20(x8) - srli x14, x15, 0x1f - add x15, x14, x15 - srai x15, x15, 0x1 - addi x14, x15, 0 - lw x15, -28(x8) - blt x15, x14, .L_int_to_string_130 -.L_int_to_string_1b8: - lw x1, 44(x2) - lw x8, 40(x2) - addi x2, x2, 48 - jalr x0, 0(x1) - -bios: - addi x2, x2, -32 - sw x1, 28(x2) - sw x8, 24(x2) - addi x8, x2, 32 - addi x15, x8, -28 - addi x11, x15, 0 - addi x10, x0, 129 - jal x1, int_to_string - lbu x14, -28(x8) - addi x15, x0, 49 - bne x14, x15, .L_bios_228 - lbu x14, -27(x8) - addi x15, x0, 50 - bne x14, x15, .L_bios_228 - lbu x14, -26(x8) - addi x15, x0, 57 - bne x14, x15, .L_bios_228 - lbu x15, -25(x8) - bne x15, x0, .L_bios_228 - lui x15, 0x2 - lui x14, 0xaaaab - addi x14, x14, -1366 # 0xaaaaaaaa - sw x14, 0(x15) - jal x0, .L_bios_268 -.L_bios_228: - lui x15, 0x2 - lui x14, 0xbbbbc - addi x14, x14, -1093 # 0xbbbbbbbb - sw x14, 0(x15) - lbu x14, -28(x8) - lui x15, 0x2 - addi x15, x15, 4 - sw x14, 0(x15) - lbu x14, -27(x8) - lui x15, 0x2 - addi x15, x15, 8 - sw x14, 0(x15) - lbu x14, -26(x8) - lui x15, 0x2 - addi x15, x15, 12 - sw x14, 0(x15) -.L_bios_268: - addi x15, x0, 0 - addi x10, x15, 0 - lw x1, 28(x2) - lw x8, 24(x2) - addi x2, x2, 32 - jalr x0, 0(x1) - -__divsi3: - blt x10, x0, .L_2e0 - blt x11, x0, .L_2f0 - -__hidden___udivsi3: - addi x12, x11, 0 - addi x11, x10, 0 - addi x10, x0, -1 - beq x12, x0, .L_2cc - addi x13, x0, 1 - bgeu x12, x11, .L_2b0 -.L_2a0: - bge x0, x12, .L_2b0 - slli x12, x12, 0x1 - slli x13, x13, 0x1 - bltu x12, x11, .L_2a0 -.L_2b0: - addi x10, x0, 0 -.L_2b4: - bltu x11, x12, .L_2c0 - sub x11, x11, x12 - or x10, x10, x13 -.L_2c0: - srli x13, x13, 0x1 - srli x12, x12, 0x1 - bne x13, x0, .L_2b4 -.L_2cc: - jalr x0, 0(x1) - -__umodsi3: - addi x5, x1, 0 - jal x1, __hidden___udivsi3 - addi x10, x11, 0 - jalr x0, 0(x5) -.L_2e0: - sub x10, x0, x10 - blt x0, x11, .L_2f4 - sub x11, x0, x11 - jal x0, __hidden___udivsi3 -.L_2f0: - sub x11, x0, x11 -.L_2f4: - addi x5, x1, 0 - jal x1, __hidden___udivsi3 - sub x10, x0, x10 - jalr x0, 0(x5) - -__modsi3: - addi x5, x1, 0 - blt x11, x0, .L_31c - blt x10, x0, .L_324 -.L_310: - jal x1, __hidden___udivsi3 - addi x10, x11, 0 - jalr x0, 0(x5) -.L_31c: - sub x11, x0, x11 - bge x10, x0, .L_310 -.L_324: - sub x10, x0, x10 - jal x1, __hidden___udivsi3 - sub x10, x0, x11 - jalr x0, 0(x5) - - .section .rodata - .align 2 -g3_addr: - .word 0x00002000 \ No newline at end of file