I presume that to write the migen wrapper for the fastvdma we need to make it use the same internal bus as the LiteX - Wishbone. Even though the original code is really well-written there is no documentation whatsoever on connecting it to the Wishbone bus.
I had no problems with the Verilog generation for the default AXI4, but I have truly no idea how to configure it for Wishbone
As @rw1nkler suggested here we can use the LiteX module to translate between the AXI and Wishbone, but creating wrapper on top of a wrapper is never a good idea.
I wasn't quite sure where to create this issue, but let's keep everything in one place for now.
I presume that to write the migen wrapper for the fastvdma we need to make it use the same internal bus as the LiteX - Wishbone. Even though the original code is really well-written there is no documentation whatsoever on connecting it to the Wishbone bus.
I had no problems with the Verilog generation for the default AXI4, but I have truly no idea how to configure it for Wishbone
As @rw1nkler suggested here we can use the LiteX module to translate between the AXI and Wishbone, but creating wrapper on top of a wrapper is never a good idea.
I wasn't quite sure where to create this issue, but let's keep everything in one place for now.