I explored the Armv7-M implementation using a STM32 Black Pill Microcontroller. By doing this, I discovered that by applying some changes the time performance of this algorithm is improved between 4.2% and 7.2% for Os flag, with it improving sa the message size increases.
The changes I implemented were:
- changing the functions ROR, KEYROT, NOTZERO, LOADBYTES and STOREBYTES
- Activating inlining
- Using local variables to reduce the amount of functions references for messages with more than 2 blocks.
Additionally, I adapted the protected version to work on a ChipWhisperer Nano which uses a Cortex-M0. As of now, the side channel protection is maintained for O0 flag.
These versions can be found on: https://github.com/lauram354/implementaciones_ascon.git
I explored the Armv7-M implementation using a STM32 Black Pill Microcontroller. By doing this, I discovered that by applying some changes the time performance of this algorithm is improved between 4.2% and 7.2% for Os flag, with it improving sa the message size increases.
The changes I implemented were:
Additionally, I adapted the protected version to work on a ChipWhisperer Nano which uses a Cortex-M0. As of now, the side channel protection is maintained for O0 flag.
These versions can be found on: https://github.com/lauram354/implementaciones_ascon.git