UPSTREAM PR #30787: RISC-V: Port dot-asm ChaCha20 assembly implementation with rv64gc and zbb#685
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UPSTREAM PR #30787: RISC-V: Port dot-asm ChaCha20 assembly implementation with rv64gc and zbb#685loci-dev wants to merge 1 commit into
loci-dev wants to merge 1 commit into
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… Zbb Current OpenSSL's RISC-V ChaCha20 only has vector implementation and C fallback. So we port dot-asm/cryptogams chacha-riscv.pl to provide assembly implementation with rv64gc and Zbb. Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
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Source pull request: openssl/openssl#30787
Current OpenSSL's RISC-V ChaCha20 only has vector implementation and C fallback. I ported dot-asm/cryptogams chacha-riscv.pl to provide an assembly implementation with rv64gc and Zbb.
Removed vector part since we already have a mix of scalar ALU and vector ALU implementation in OpenSSL.
Benchmark result: