-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathtranscript
More file actions
166 lines (166 loc) · 6.27 KB
/
transcript
File metadata and controls
166 lines (166 loc) · 6.27 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
# Errors: 12, Warnings: 0
# Errors: 0, Warnings: 0
# Compile of sharp_arith.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_control.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_linemem.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_slice.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sim_sharp.vhd was successful.
# Errors: 0, Warnings: 2
# Compile of sim_sharp_self-checking.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp.vhd was successful.
# Compile of sharp_arith.vhd was successful.
# Compile of sharp_control.vhd was successful.
# Compile of sharp_linemem.vhd was successful.
# Compile of sharp_slice.vhd was successful.
# Compile of sim_sharp.vhd was successful with warnings.
# Compile of sim_sharp_self-checking.vhd was successful with warnings.
# Compile of sharp.vhd was successful.
# 7 compiles, 0 failed with no errors.
# Compile of sim_sharp.vhd was successful with warnings.
# Errors: 0, Warnings: 0
# Compile of sharp_arith.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_control.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_linemem.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_slice.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sim_sharp.vhd was successful.
# Errors: 0, Warnings: 2
# Compile of sim_sharp_self-checking.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp.vhd was successful.
# Compile of sharp_arith.vhd was successful.
# Compile of sharp_control.vhd was successful.
# Compile of sharp_linemem.vhd was successful.
# Compile of sharp_slice.vhd was successful.
# Compile of sim_sharp.vhd was successful with warnings.
# Compile of sim_sharp_self-checking.vhd was successful with warnings.
# Compile of sharp.vhd was successful.
# 7 compiles, 0 failed with no errors.
vsim work.sim_sharp(sim)
# vsim work.sim_sharp(sim)
# Start time: 15:12:31 on Jan 22,2025
# ** Note: (vsim-3812) Design is being optimized...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.sim_sharp(sim)#1
# Loading work.sharp_slice(behave)#1
add wave -position insertpoint \
sim:/sim_sharp/b_in \
sim:/sim_sharp/de_in \
sim:/sim_sharp/g_in \
sim:/sim_sharp/hs_in \
sim:/sim_sharp/r_in \
sim:/sim_sharp/vs_in
run
# ** Fatal: (vsim-7) Failed to open VHDL file "Lindau_Harbour_720p.ppm" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ns Iteration: 0 Process: /sim_sharp/stimuli_process File: C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd
# Fatal error in Process stimuli_process at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd line 90
#
# HDL call sequence:
# Stopped at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd 90 Process stimuli_process
#
run
# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd 90 Process stimuli_process
#
run
# Cannot continue because of fatal error.
# HDL call sequence:
# Stopped at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp_self-checking.vhd 90 Process stimuli_process
#
quit -sim
# End time: 15:15:20 on Jan 22,2025, Elapsed time: 0:02:49
# Errors: 1, Warnings: 10
# Errors: 0, Warnings: 0
# Compile of sharp_arith.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_control.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_linemem.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_slice.vhd was successful.
# Errors: 0, Warnings: 2
# Compile of sim_sharp.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp.vhd was successful.
# Compile of sharp_arith.vhd was successful.
# Compile of sharp_control.vhd was successful.
# Compile of sharp_linemem.vhd was successful.
# Compile of sharp_slice.vhd was successful.
# Compile of sim_sharp.vhd was successful.
# Compile of sharp.vhd was successful.
# 6 compiles, 0 failed with no errors.
vsim work.sim_sharp(sim)
# vsim work.sim_sharp(sim)
# Start time: 15:16:15 on Jan 22,2025
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.sim_sharp(sim)#1
# Loading work.sharp_slice(behave)#1
add wave -position insertpoint \
sim:/sim_sharp/b_in \
sim:/sim_sharp/de_in \
sim:/sim_sharp/g_in \
sim:/sim_sharp/hs_in \
sim:/sim_sharp/r_in
run
run -continue
run -continue
run -continue
run
run
run
run
run
run
run -all
# Break key hit
# Simulation stop requested.
quit -sim
# End time: 15:21:58 on Jan 22,2025, Elapsed time: 0:05:43
# Errors: 0, Warnings: 4
# Errors: 0, Warnings: 0
# Compile of sharp.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_linemem.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_arith.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_slice.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sharp_control.vhd was successful.
# Errors: 0, Warnings: 0
# Compile of sim_sharp.vhd was successful.
vsim work.sim_sharp
# vsim work.sim_sharp
# Start time: 15:23:12 on Jan 22,2025
# ** Note: (vsim-8009) Loading existing optimized design _opt
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.std_logic_textio(body)
# Loading work.sim_sharp(sim)#1
# Loading work.sharp_slice(behave)#1
add wave -position insertpoint sim:/sim_sharp/*
run -all
# ** Failure: Simulation completed
# Time: 8902120 ns Iteration: 0 Process: /sim_sharp/stimuli_process File: C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp.vhd
# Break in Process stimuli_process at C:/Users/jonel/OneDrive/Desktop/VHDL Projects/FPGA-FIR-Filter-master/FPGA-FIR-Filter-master/Verification/sim_sharp.vhd line 164