Enhance VBlank and HBlank polling

[bit-hack]

Currently every 15 cycles the CPU emulator invokes a timing routine to update port 03DAh (bits 3 and 0). This gives poor granularity of updates, and pro-active updates can be wasted.
Re-calculate these fields only when the register is read, using the current cycle number as a guide.
This would give cycle exact granularity and reduce the computational cost overall.
This can be integrated into the new video system, but can be back ported into the old one too.
At the same time we can update the screen buffer when we enter the vblank period, for better synchronization with our emulation and avoid tearing.