diff --git a/package/kernel/qca-ppe/src/qca_ppe_main.c b/package/kernel/qca-ppe/src/qca_ppe_main.c
index 52d1c016a8f1f5..969c3d7801cb71 100644
--- a/package/kernel/qca-ppe/src/qca_ppe_main.c
+++ b/package/kernel/qca-ppe/src/qca_ppe_main.c
@@ -652,6 +652,8 @@ static void qca_ppe_phylink_get_caps(struct dsa_switch *ds, int port,
 			MAC_1000FD | MAC_100FD | MAC_10FD |
 			MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
 
+		__set_bit(PHY_INTERFACE_MODE_QSGMII,
+			  config->supported_interfaces);
 		__set_bit(PHY_INTERFACE_MODE_PSGMII,
 			  config->supported_interfaces);
 		__set_bit(PHY_INTERFACE_MODE_SGMII,
diff --git a/package/kernel/qca-ppe/src/qualcomm,ipq-ppe.yaml b/package/kernel/qca-ppe/src/qualcomm,ipq-ppe.yaml
index f6ecaf2bf53b30..ddd727df6267b0 100644
--- a/package/kernel/qca-ppe/src/qualcomm,ipq-ppe.yaml
+++ b/package/kernel/qca-ppe/src/qualcomm,ipq-ppe.yaml
@@ -15,9 +15,9 @@ description: |
   scheduling. It is driven as a DSA switch, using an EDMA network device as the
   CPU port conduit and UNIPHY PCS instances for SerDes link management.
 
-  IPQ6018 provides 7 ports (CPU port 0, user ports 1-4 via PSGMII on uniphy0,
+  IPQ6018 provides 7 ports (CPU port 0, user ports 1-4 via QSGMII/PSGMII on uniphy0,
   and port 5 via uniphy1). IPQ8074 provides 8 ports (CPU port 0, user ports
-  1-4 via PSGMII on uniphy0, and ports 5-6 via uniphy1/uniphy2).
+  1-4 via QSGMII/PSGMII on uniphy0, and ports 5-6 via uniphy1/uniphy2).
 
 $ref: dsa.yaml#
 
diff --git a/package/kernel/qca-uniphy/src/qca_uniphy.c b/package/kernel/qca-uniphy/src/qca_uniphy.c
index 31859c4c3b04b1..14dcec344d2698 100644
--- a/package/kernel/qca-uniphy/src/qca_uniphy.c
+++ b/package/kernel/qca-uniphy/src/qca_uniphy.c
@@ -208,6 +208,7 @@ qca_uniphy_pcs_inband_caps(struct phylink_pcs *pcs,
 			     phy_interface_t interface)
 {
 	switch (interface) {
+	case PHY_INTERFACE_MODE_QSGMII:
 	case PHY_INTERFACE_MODE_PSGMII:
 	case PHY_INTERFACE_MODE_SGMII:
 		return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
@@ -275,6 +276,7 @@ static int qca_uniphy_pcs_config(struct phylink_pcs *pcs,
 	case PHY_INTERFACE_MODE_PSGMII:
 		return qca_uniphy_psgmii_calibrate(uniphy);
 	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_QSGMII:
 	case PHY_INTERFACE_MODE_2500BASEX:
 		if (interface == uniphy->current_mode)
 			return 0;
@@ -284,7 +286,12 @@ static int qca_uniphy_pcs_config(struct phylink_pcs *pcs,
 				UNIPHY_MISC2_SGMII,
 				UNIPHY_SG_MODE | UNIPHY_SG_AUTONEG,
 				125000000);
-		else
+		else if (interface == PHY_INTERFACE_MODE_QSGMII)
+			qca_uniphy_sgmii_setup(uniphy,
+				UNIPHY_MISC2_SGMII,
+				UNIPHY_CH0_QSGMII_SGMII | UNIPHY_SG_AUTONEG,
+				125000000);
+		else if (interface == PHY_INTERFACE_MODE_2500BASEX)
 			qca_uniphy_sgmii_setup(uniphy,
 				UNIPHY_MISC2_SGMIIPLUS,
 				UNIPHY_SGPLUS_MODE | UNIPHY_SG_AUTONEG,
diff --git a/package/kernel/qca-uniphy/src/qca_uniphy.h b/package/kernel/qca-uniphy/src/qca_uniphy.h
index 8a092c327867c1..882126ccce9843 100644
--- a/package/kernel/qca-uniphy/src/qca_uniphy.h
+++ b/package/kernel/qca-uniphy/src/qca_uniphy.h
@@ -18,6 +18,7 @@
 #define   UNIPHY_MISC2_SGMIIPLUS	0x50
 
 #define UNIPHY_MODE_CTRL		0x46c
+#define   UNIPHY_CH0_QSGMII_SGMII	BIT(8)
 #define   UNIPHY_CH0_PSGMII_QSGMII	BIT(9)
 #define   UNIPHY_SG_MODE		BIT(10)
 #define   UNIPHY_SGPLUS_MODE		BIT(11)