From 0e8977a05b4a5a9f95a7752aee7c5b9387baff33 Mon Sep 17 00:00:00 2001 From: S0urceror Date: Tue, 12 Dec 2023 17:08:01 +0100 Subject: [PATCH 1/2] hardware CTS and RTS working and tested --- src/serial.asm | 5 +++-- src/uart.c | 8 ++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/serial.asm b/src/serial.asm index faedd36..b0179c4 100644 --- a/src/serial.asm +++ b/src/serial.asm @@ -75,8 +75,9 @@ UART_LSR_RDY EQU %01 ; Data ready ; Check whether we're clear to send (UART0 only) ; -UART0_wait_CTS: GET_GPIO PD_DR, 8 ; Check Port D, bit 3 (CTS) - JR NZ, UART0_wait_CTS +UART0_wait_CTS: in0 a, (UART0_REG_MSR) + bit 4,a ; check inverted CTS bit, 1 = CTS, 0 = NOT CTS (clear to send) + JR Z, UART0_wait_CTS RET UART1_wait_CTS: GET_GPIO PC_DR, 8 ; Check Port C, bit 3 (CTS) diff --git a/src/uart.c b/src/uart.c index ebf2a78..3fa84ae 100644 --- a/src/uart.c +++ b/src/uart.c @@ -74,9 +74,9 @@ BYTE open_UART0(UART * pUART) { SETREG(PD_ALT2, pins); if(pUART->flowControl == FCTL_HW) { - SETREG(PD_DDR, PORTPIN_THREE); // Set Port D bit 3 (CTS) for input - RESETREG(PD_ALT1, PORTPIN_THREE); - RESETREG(PD_ALT2, PORTPIN_THREE); + SETREG(PD_DDR, PORTPIN_THREE|PORTPIN_TWO); // Set Port D bit 3 and 2 (CTS,RTS) to alternate function + RESETREG(PD_ALT1, PORTPIN_THREE|PORTPIN_TWO); + SETREG(PD_ALT2, PORTPIN_THREE|PORTPIN_TWO); serialFlags |= 0x02; } @@ -84,7 +84,7 @@ BYTE open_UART0(UART * pUART) { UART0_BRG_L = (br & 0xFF); // Load divisor low UART0_BRG_H = (CHAR)(( br & 0xFF00 ) >> 8); // Load divisor high UART0_LCTL &= (~UART_LCTL_DLAB); // Reset DLAB; dont disturb other bits - UART0_MCTL = 0x00; // Bring modem control register to reset value + UART0_MCTL = 0x02; // Multidrop, loopback, DTR disabled, RTS enabled UART0_FCTL = 0x07; // Enable and clear hardware FIFOs UART0_IER = pUART->interrupts; // Set interrupts From cc4089979a32364d99a7e9863841038b9bf82066 Mon Sep 17 00:00:00 2001 From: S0urceror Date: Tue, 9 Jan 2024 22:10:02 +0100 Subject: [PATCH 2/2] full-duplex mode is signalled by PACKET_GP > 1 --- .gitignore | 3 ++- MOS.wsp | 26 ++++++++++++++++++++++++++ main.c | 2 +- 3 files changed, 29 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 6f5d8ad..8e0f07b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ Debug/ -Release/ \ No newline at end of file +Release/ +.DS_Store \ No newline at end of file diff --git a/MOS.wsp b/MOS.wsp index 8d67b4c..5c8be8e 100644 --- a/MOS.wsp +++ b/MOS.wsp @@ -4,3 +4,29 @@ ptn_Child1=Frames [WorkState_v1_2.Frames] ptn_Child1=ChildFrames +[WorkState_v1_2.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 + +[WorkState_v1_2.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 + +[WorkState_v1_2.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=src\uart.c +DocTemplateIndex=0 +DocumentString=IDE.Document +IsActiveChildFrame=False +IsFrameVisible=True +WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPIPPPPPPPBOPPPPPPOEAAAAAAOEAAAAAAJCFAAAAABLBAAAAA + +[WorkState_v1_2.Frames.ChildFrames.Document-1] +ptn_Child1=ViewFrame-0 + +[WorkState_v1_2.Frames.ChildFrames.Document-1.ViewFrame-0] +DocPathName=.\main.c +DocTemplateIndex=0 +DocumentString=IDE.Document +IsActiveChildFrame=True +IsFrameVisible=True +WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPIPPPPPPPBOPPPPPPIGAAAAAAIGAAAAAAHEFAAAAAPMBAAAAA + diff --git a/main.c b/main.c index 49cbc65..b13aacc 100644 --- a/main.c +++ b/main.c @@ -82,7 +82,7 @@ int wait_ESP32(UART * pUART, UINT24 baudRate) { putch(23); // Send a general poll packet putch(0); putch(VDP_gp); - putch(1); + putch(2); // 2 = full-duplex-mode, 1 = half-duplex-mode (default) for(i = 0; i < 5; i++) { // Wait 50ms wait_timer0(); }