Hello,
Does marss-riscv support multiple execution threads in the same time domain as SystemC. For instance, can I add a custom peripheral counter that increments every 1ms and then let the CPU and the timer peripheral run in “parallel”. If my CPU would run approximately 1 mips, I would expect then that the counter peripheral increments approximately every 1000 instructions executed by the CPU since every instruction takes 1us.
In my understanding https://marss-riscv-docs.readthedocs.io/en/latest/sections/memory-hierarchy.html describes that a write requests to the memory controller is executed in this fashion. The CPU continues the execution while the memory controller waits for the delay. Is this also possible for own custom peripherals?
Many regards and many thanks in advance
Felix Böseler
Hello,
Does marss-riscv support multiple execution threads in the same time domain as SystemC. For instance, can I add a custom peripheral counter that increments every 1ms and then let the CPU and the timer peripheral run in “parallel”. If my CPU would run approximately 1 mips, I would expect then that the counter peripheral increments approximately every 1000 instructions executed by the CPU since every instruction takes 1us.
In my understanding https://marss-riscv-docs.readthedocs.io/en/latest/sections/memory-hierarchy.html describes that a write requests to the memory controller is executed in this fashion. The CPU continues the execution while the memory controller waits for the delay. Is this also possible for own custom peripherals?
Many regards and many thanks in advance
Felix Böseler