Assignment inside for loop causes SEGV

[matsud224]

Following foo module causes SEGV while read_systemverilog command.

// bad.v
module foo
(
  output wire [1:0] out
);

  function [1:0] func1(input [1:0] a);
    reg [3:0] state[4];
    integer i;
    begin
      for (i = 0; i < 4; i = i + 1) begin
        state[i] = 2'b0;
        state[i][i] = 1'b1;
      end

      func1 = state[0] ^ a;
    end
  endfunction

  assign out = func1(2'd3);

endmodule

This is an output of read_systemverilog -I. -debug -dump_rtlil bad.v:
log.txt

It seems that SEGV is caused by Synlig's simplify process because read_verilog can read successfully.

Environment

OS: Ubuntu 24.04 LTS
Synlig version: 10efd31 (installed from source)

[alaindargelas]

@matsud224 This is supported here alainmarcel/uhdm2rtlil#174