break doesn't compile within a case statement.
Test case:
module test ( input logic clock);
logic [2:0] state, random;
always_ff @(posedge clock) begin
for (int i=0;i<16;i++) begin // do it a bunch of times...
unique case (state)
0: if (random == 0) break;
1: if (random == 1) break;
endcase
end // for
end // always
endmodule
Error Message (only the relevant parts included):
Generating RTLIL representation for module `\test'.
ERROR: Abort in /root/synlig/synlig/third_party/yosys/frontends/ast/genrtlil.cc:871.
break doesn't compile within a case statement.
Test case:
module test ( input logic clock);
logic [2:0] state, random;
always_ff @(posedge clock) begin
for (int i=0;i<16;i++) begin // do it a bunch of times...
unique case (state)
0: if (random == 0) break;
1: if (random == 1) break;
endcase
end // for
end // always
endmodule
Error Message (only the relevant parts included):
Generating RTLIL representation for module `\test'.
ERROR: Abort in /root/synlig/synlig/third_party/yosys/frontends/ast/genrtlil.cc:871.