Port is connected to constants: { $auto$hierarchy.cc:1462:execute$1 1'0 }

[L3odr0id]

Executing HIERARCHY pass of the following module results in an error: Output port b.a_inst.a1 (a) is connected to constants: { $auto$hierarchy.cc:1462:execute$1 1'0 }

module a (output logic [4:2] a1, output logic a2);
endmodule: a

module b (output logic b1);

  a a_inst(.a1(b2), .a2(b1));

  assign b2 = 'b0;

endmodule: b

Command: synlig -f systemverilog -o output.blif -S test.sv

Expected Behavior

The hierarchy pass must complete successfully, or a human-readable error should be thrown (should $auto$hierarchy.cc:1462:execute$ be a part of the error message?)

This issue occurs in Synlig (git sha1 2d838edc9, c++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)

Found by a verilog model using deptycheck

[alaindargelas]

@L3odr0id this is supported here: alainmarcel/uhdm2rtlil#173