chipsalliance · kamilrakoczy · Apr 24, 2023
diff --git a/.github/workflows/large-designs.yml b/.github/workflows/large-designs.yml
@@ -487,13 +487,18 @@ jobs:
             **/plot_*.svg
 
   blackparrot_synth:
-    name: Black Parrot (synthesis)
     runs-on: [self-hosted, Linux, X64]
     container: ubuntu:jammy
+    strategy:
+      matrix:
+        vars: [ {cfg: e_bp_unicore_cfg, machine: n2-highmem-8}, {cfg: e_bp_multicore_1_cfg, machine: n2-highmem-8}, {cfg: e_bp_multicore_1_cce_ucode_cfg, machine: n2-highmem-8}, {cfg: e_bp_multicore_4_cfg, machine: n2-highmem-32}, {cfg: e_bp_multicore_4_cce_ucode_cfg, machine: n2-highmem-32} ]
+      fail-fast: false
+    name: Black Parrot (${{ matrix.vars.cfg }} - synthesis)
     env:
       CC: gcc-9
       CXX: g++-9
       DEBIAN_FRONTEND: noninteractive
+      GHA_MACHINE_TYPE: ${{ matrix.vars.machine }}
 
     steps:
       - uses: actions/checkout@v3
@@ -540,11 +545,12 @@ jobs:
         env:
           TARGET: uhdm/yosys/synth-blackparrot-build
           TEST_CASE: tests/black-parrot
+          BLACKPARROT_CFG: ${{ matrix.vars.cfg }}
 
       - uses: actions/upload-artifact@v2
         with:
-          name: bp_unicore.edif
-          path: uhdm-tests/black-parrot/black-parrot/bp_top/syn/bp_unicore.edif
+          name: bp_${{ matrix.vars.cfg }}.edif
+          path: UHDM-integration-tests/build/bp_${{ matrix.vars.cfg }}.edif
 
       - name: Upload load graphs
         if: ${{ always() }}

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
@@ -155,6 +155,7 @@ jobs:
       - name: Build binaries
         run: |
           export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+          cd yosys && git apply ../0001-Add-typedef-support-to-detectSignWidthWorker.patch && cd -
           ./build_binaries.sh
           # By default actions/upload-artifact@v2 do not preserve file permissions
           # tar directory to workaround this issue

diff --git a/0001-Add-typedef-support-to-detectSignWidthWorker.patch b/0001-Add-typedef-support-to-detectSignWidthWorker.patch
@@ -0,0 +1,14 @@
+diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
+index eaf6553ce..ee7121548 100644
+--- a/frontends/ast/genrtlil.cc
++++ b/frontends/ast/genrtlil.cc
+@@ -841,6 +841,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
+ 		}
+ 		if (!id_ast)
+ 			log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str());
++		if (id_ast->type == AST_TYPEDEF) {
++			id_ast = id_ast->children[0];
++		}
+ 		if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {
+ 			if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
+ 				this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
diff --git a/uhdm-tests/black-parrot/Makefile.in b/uhdm-tests/black-parrot/Makefile.in
@@ -2,18 +2,27 @@ curr_dir:=$(dir $(lastword $(MAKEFILE_LIST)))
 ###################
 ### BLACKPARROT ###
 ###################
-VENV_BLACKPARROT_SYNTH = ${root_dir}/venv-blackparrot-synth
 BLACKPARROT = ${curr_dir}/black-parrot
+BLACKPARROT_PATCHES_DIR = ${curr_dir}/black-parrot-patches/black-parrot/
+BLACKPARROT_BASEJUMP = ${BLACKPARROT}/external/basejump_stl/
+BLACKPARROT_BASEJUMP_PATCHES_DIR = ${curr_dir}/black-parrot-patches/basejump_stl
+BLACKPARROT_CFG ?= e_bp_unicore_cfg
+BLACKPARROT_UHDM = ${root_dir}/build/surelog/bp_tethered.${BLACKPARROT_CFG}.none.parse/out/slpp_unit/surelog.uhdm
 
-${VENV_BLACKPARROT_SYNTH}:
-	virtualenv ${VENV_BLACKPARROT_SYNTH}
-	(. ${VENV_BLACKPARROT_SYNTH}/bin/activate)
+${BLACKPARROT_BASEJUMP}/.gitpatch:
+	cd ${BLACKPARROT_BASEJUMP} && git apply ${BLACKPARROT_BASEJUMP_PATCHES_DIR}/*.patch && touch $@
 
-uhdm/yosys/synth-blackparrot-build: clean-build | ${VENV_BLACKPARROT_SYNTH}
+${BLACKPARROT}/.gitpatch: | ${BLACKPARROT_BASEJUMP}/.gitpatch
+	cd ${BLACKPARROT}/ && git apply ${BLACKPARROT_PATCHES_DIR}/*.patch && touch $@
+
+${BLACKPARROT_UHDM}: clean-build | ${BLACKPARROT}/.gitpatch
+	(export PATH=${root_dir}/../image/bin:${PATH} && \
+		cd ${BLACKPARROT}/bp_top/syn/ && SURELOG_OPTS=-synth $(MAKE) parse.surelog CFG=${BLACKPARROT_CFG} RESULTS_PATH=${root_dir}/build)
+
+uhdm/yosys/synth-blackparrot-build: | ${BLACKPARROT_UHDM}
 	(export PATH=${root_dir}/../image/bin:${PATH} && \
-		. ${VENV_BLACKPARROT_SYNTH}/bin/activate && \
-		cd ${BLACKPARROT}/bp_top/syn/ && SURELOG_OPTS=-synth $(MAKE) parse.surelog CFG=e_bp_unicore_cfg && \
+		cd ${root_dir}/build && \
 		yosys -p "plugin -i systemverilog" \
-		      -p "read_uhdm ./results/surelog/bp_tethered.e_bp_unicore_cfg.none.parse/out/slpp_unit/surelog.uhdm" \
+		      -p "read_uhdm ${BLACKPARROT_UHDM}" \
 		      -p "synth_xilinx -iopad -family xc7" \
-		      -p "write_edif bp_unicore.edif")
+		      -p "write_edif bp_${BLACKPARROT_CFG}.edif")
diff --git a/...ts/black-parrot/black-parrot-patches/basejump_stl/0003-WIP-start-wires-from-index-0.patch b/...ts/black-parrot/black-parrot-patches/basejump_stl/0003-WIP-start-wires-from-index-0.patch
@@ -0,0 +1,93 @@
+From 638f88f8ea7f28d8f10d502033214ca6cc8cc696 Mon Sep 17 00:00:00 2001
+From: Kamil Rakoczy <krakoczy@antmicro.com>
+Date: Wed, 26 Apr 2023 15:06:28 +0200
+Subject: [PATCH 3/3] WIP: start wires from index 0
+
+Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
+---
+ bsg_noc/bsg_mesh_stitch.v | 51 ++++++++++++++++++++++-----------------
+ 1 file changed, 29 insertions(+), 22 deletions(-)
+
+diff --git a/bsg_noc/bsg_mesh_stitch.v b/bsg_noc/bsg_mesh_stitch.v
+index 6ccb8383..201dce61 100644
+--- a/bsg_noc/bsg_mesh_stitch.v
++++ b/bsg_noc/bsg_mesh_stitch.v
+@@ -14,15 +14,22 @@ module bsg_mesh_stitch
+     , x_max_p = "inv"
+     , y_max_p = "inv"
+     , nets_p  = 1 // optional parameter that allows for multiple networks to be routed together
++    //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs;
++    // recalculate assuming W = 0 and S = 0
++   , parameter logic [2:0] W2 = 0 /*W-W*/
++   , parameter logic [2:0] E2 = E-W
++   , parameter logic [2:0] S2 = 0 /*S-S*/
++   , parameter logic [2:0] N2 = S-N /*S is larger*/
++   , parameter logic [2:0] SW2 = S-W /*S is larger*/
+     )
+-   (input    [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] outs_i // for each node, each direction
+-    , output [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] ins_o
++   (input    [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][SW:0][width_p-1:0] outs_i // for each node, each direction
++    , output [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][SW:0][width_p-1:0] ins_o
+
+     // these are the edge of the greater tile
+-    , input  [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_i
+-    , output [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_o
+-    , input  [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_i
+-    , output [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_o
++    , input  [E2:W2][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_i
++    , output [E2:W2][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_o
++    , input  [N2:S2][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_i
++    , output [N2:S2][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_o
+     );
+
+    genvar r,c,net;
+@@ -32,30 +39,30 @@ module bsg_mesh_stitch
+
+         for (r = 0; r < y_max_p; r=r+1)
+           begin: _r
+-             assign hor_o[E][r][net] = outs_i[r][x_max_p-1][net][E];
+-             assign hor_o[W][r][net] = outs_i[r][0        ][net][W];
++             assign hor_o[E2-1][r][net] = outs_i[r][x_max_p-1][net][E2-1];
++             assign hor_o[W2][r][net] = outs_i[r][0        ][net][W2];
+
+              for (c = 0; c < x_max_p; c=c+1)
+                begin: _c
+-                 assign ins_o[r][c][net][S] = (r == y_max_p-1)
+-                                            ? ver_i[S][c][net]
+-                                            : outs_i[(r == y_max_p-1) ? r : r+1][c][net][N]; // ?: for warning
+-                 assign ins_o[r][c][net][N] = (r == 0)
+-                                            ? ver_i[N][c][net]
+-                                            : outs_i[r ? r-1: 0][c][net][S]; // ?: to eliminate warning
+-                 assign ins_o[r][c][net][E] = (c == x_max_p-1)
+-                                            ? hor_i[E][r][net]
+-                                            : outs_i[r][(c == x_max_p-1) ? c : (c+1)][net][W]; // ?: for warning
+-                 assign ins_o[r][c][net][W] = (c == 0)
+-                                            ? hor_i[W][r][net]
+-                                            : outs_i[r][c ? (c-1) :0][net][E]; // ?: to eliminate warning
++                 assign ins_o[r][c][net][N2] = (r == y_max_p-1)
++                                            ? ver_i[N2][c][net]
++                                            : outs_i[(r == y_max_p-1) ? r : r+1][c][net][S2]; // ?: for warning
++                 assign ins_o[r][c][net][S2] = (r == 0)
++                                            ? ver_i[S2][c][net]
++                                            : outs_i[r ? r-1: 0][c][net][N2]; // ?: to eliminate warning
++                 assign ins_o[r][c][net][E2-1] = (c == x_max_p-1)
++                                            ? hor_i[E2-1][r][net]
++                                            : outs_i[r][(c == x_max_p-1) ? c : (c+1)][net][W2]; // ?: for warning
++                 assign ins_o[r][c][net][W2] = (c == 0)
++                                            ? hor_i[W2][r][net]
++                                            : outs_i[r][c ? (c-1) :0][net][E2-1]; // ?: to eliminate warning
+                end // block: c
+           end // block: r
+
+         for (c = 0; c < x_max_p; c=c+1)
+           begin: _c
+-             assign ver_o[S][c][net] = outs_i[y_max_p-1][c][net][S];
+-             assign ver_o[N][c][net] = outs_i[0        ][c][net][N];
++             assign ver_o[N2][c][net] = outs_i[y_max_p-1][c][net][N2];
++             assign ver_o[S2][c][net] = outs_i[0        ][c][net][S2];
+           end
+      end // block: _n
+
+-- 
+2.39.0
+
diff --git a/...rrot/black-parrot-patches/black-parrot/0002-Add-workaround-for-unsupported-typespec.patch b/...rrot/black-parrot-patches/black-parrot/0002-Add-workaround-for-unsupported-typespec.patch
@@ -0,0 +1,33 @@
+From 0a5300004fc90bae4b0dbc214ff331e5a25cd5a6 Mon Sep 17 00:00:00 2001
+From: Kamil Rakoczy <krakoczy@antmicro.com>
+Date: Wed, 26 Apr 2023 09:17:48 +0200
+Subject: [PATCH 2/4] Add workaround for unsupported typespec
+
+Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
+---
+ bp_common/src/include/bp_common_bedrock_if.svh | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/bp_common/src/include/bp_common_bedrock_if.svh b/bp_common/src/include/bp_common_bedrock_if.svh
+index ac7acf8f..5118d0ee 100644
+--- a/bp_common/src/include/bp_common_bedrock_if.svh
++++ b/bp_common/src/include/bp_common_bedrock_if.svh
+@@ -196,10 +196,14 @@
+     `declare_bp_bedrock_header_width(addr_width_mp, mem_fwd_payload_width_lp, mem_fwd)  \
+     `declare_bp_bedrock_header_width(addr_width_mp, mem_rev_payload_width_lp, mem_rev)
+
++    //declare_bp_bedrock_mem_payload_s macro defines `bp_bedrock_mem_fwd_payload_s` struct,
++    //and creates typedef `bp_bedrock_mem_rev_payload_s` that is equal to
++    //`bp_bedrock_mem_fwd_payload_s` but Surelog doesn't see it. Use
++    //`bp_bedrock_mem_fwd_payload_s` directly for now.
+   `define declare_bp_bedrock_mem_if(addr_width_mp, did_width_mp, lce_id_width_mp, lce_assoc_mp) \
+     `declare_bp_bedrock_mem_payload_s(did_width_mp, lce_id_width_mp, lce_assoc_mp); \
+     `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_fwd_payload_s, mem_fwd); \
+-    `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_rev_payload_s, mem_rev) \
++    `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_fwd_payload_s, mem_rev) \
+
+   `define declare_bp_bedrock_if_widths(addr_width_mp, payload_width_mp, name_mp) \
+     , localparam ``name_mp``_msg_payload_width_lp = payload_width_mp \
+-- 
+2.39.0
+