[HDL] Compile-Time RTL Interpreters

[sahandKashani]

Author(s): Sahand Kashani and James R. Larus
Paper PDF: https://capra.cs.cornell.edu/latte21/paper/17.pdf
Talk Recording: https://youtu.be/OAKiMHiPu1g

[stephenneuendorffer]

If you're trying to pipeline at the level of LUTs, are you able to do this well in practice before place and route? I'd expect logic synthesis and physical synthesis to interact heavily with this approach heavily and perhaps get in the way of design optimization?

[renau]

An issue of automatic repipelining is that the number of FLOPS can significantly increase. The cut for max frequency can cut lots of wires.
Do you consider the number of flops in the cut?
(Is the code available?)

[sahandKashani]

If you're trying to pipeline at the level of LUTs, are you able to do this well in practice before place and route? I'd expect logic synthesis and physical synthesis to interact heavily with this approach heavily and perhaps get in the way of design optimization?

Hi Stephen. Thanks for the question. Yes, physical synthesis would get in the way if the circuit is ingested as-is and I've occasionally seen some design logic encoded in LUTs be completely pruned and replaced by control inputs on registers. To prevent PS from intervening, I basically remove registers and look at the functionality of the circuit at a higher (untimed) level that I can then lower again. This creates pipelines that do not have control logic other than at loop boundaries (which I have not handled yet). So I do not expect PS to have much effect in the datapaths themselves following such transforms.

[sahandKashani]

An issue of automatic repipelining is that the number of FLOPS can significantly increase. The cut for max frequency can cut lots of wires.
Do you consider the number of flops in the cut?
(Is the code available?)

You are correct. In a traditional FPGA, the number of wires would indeed increase dramatically with fine-grained pipelining. But the registers come for "free" in HyperFlex-based FPGAs as they have hard registers on all interconnect wires. This is the type of FPGA used in this project as they can reach very high frequencies and are built with pipelining in mind. But the algorithm can be applied to any type of FPGA and one should easily be able to bound how fine-grained partitioning should be done on other FPGAs to prevent register explosion.

The code is not currently open, but will be released once we send out a paper with the end-to-end workflow.