4-Bit-ALU/example.sch at main · divy3988/4-Bit-ALU · GitHub

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DSCH 3.5
VERSION 11-11-2024 16:55:12
BB(-15,0,175,60)
SYM  #and2
BB(5,0,40,20)
TITLE 17 11  #and2_1
MODEL 402
PROP
REC(0,0,0,0, )
VIS 0
PIN(5,15,0.000,0.000)b
PIN(5,5,0.000,0.000)a
PIN(40,10,0.009,0.002)s
LIG(5,15,13,15)
LIG(13,0,13,20)
LIG(33,10,40,10)
LIG(32,12,29,16)
LIG(33,10,32,12)
LIG(32,8,33,10)
LIG(29,4,32,8)
LIG(24,1,29,4)
LIG(29,16,24,19)
LIG(24,19,13,20)
LIG(13,0,24,1)
LIG(5,5,13,5)
VLG and and2(out,a,b);
FSYM
SYM  #clock
BB(-15,42,0,48)
TITLE -10 45  #clock3
MODEL 69
PROP   40.00 40.00
REC(-13,43,6,4,r)
VIS 1
PIN(0,45,0.150,0.002)clk3
LIG(-5,45,0,45)
LIG(-10,43,-12,43)
LIG(-6,43,-8,43)
LIG(-5,42,-5,48)
LIG(-15,48,-15,42)
LIG(-10,47,-10,43)
LIG(-8,43,-8,47)
LIG(-8,47,-10,47)
LIG(-12,47,-14,47)
LIG(-12,43,-12,47)
LIG(-5,48,-15,48)
LIG(-5,42,-15,42)
FSYM
SYM  #and2
BB(5,30,40,50)
TITLE 17 41  #and2_2
MODEL 402
PROP
REC(-15,-15,0,0, )
VIS 0
PIN(5,45,0.000,0.000)b
PIN(5,35,0.000,0.000)a
PIN(40,40,0.009,0.002)s
LIG(5,45,13,45)
LIG(13,30,13,50)
LIG(33,40,40,40)
LIG(32,42,29,46)
LIG(33,40,32,42)
LIG(32,38,33,40)
LIG(29,34,32,38)
LIG(24,31,29,34)
LIG(29,46,24,49)
LIG(24,49,13,50)
LIG(13,30,24,31)
LIG(5,35,13,35)
VLG and and2(out,a,b);
FSYM
SYM  #or2
BB(45,15,80,35)
TITLE 65 25  #or2_3
MODEL 502
PROP
REC(0,0,0,0, )
VIS 0
PIN(45,20,0.000,0.000)a
PIN(45,30,0.000,0.000)b
PIN(80,25,0.009,0.002)s
LIG(45,30,58,30)
LIG(57,32,53,35)
LIG(73,25,80,25)
LIG(72,27,69,31)
LIG(73,25,72,27)
LIG(72,23,73,25)
LIG(69,19,72,23)
LIG(64,16,69,19)
LIG(69,31,64,34)
LIG(64,34,53,35)
LIG(53,15,64,16)
LIG(59,28,57,32)
LIG(53,15,57,18)
LIG(57,18,59,22)
LIG(59,22,60,25)
LIG(60,25,59,28)
LIG(45,20,58,20)
VLG or or2(s,a,b);
FSYM
SYM  #and2
BB(90,40,125,60)
TITLE 102 51  #and2_4
MODEL 402
PROP
REC(0,0,0,0, )
VIS 0
PIN(90,55,0.000,0.000)b
PIN(90,45,0.000,0.000)a
PIN(125,50,0.009,0.002)s
LIG(90,55,98,55)
LIG(98,40,98,60)
LIG(118,50,125,50)
LIG(117,52,114,56)
LIG(118,50,117,52)
LIG(117,48,118,50)
LIG(114,44,117,48)
LIG(109,41,114,44)
LIG(114,56,109,59)
LIG(109,59,98,60)
LIG(98,40,109,41)
LIG(90,45,98,45)
VLG and and2(out,a,b);
FSYM
SYM  #inv
BB(140,40,175,60)
TITLE 155 50  #inv_5
MODEL 101
PROP
REC(0,0,0,0, )
VIS 0
PIN(140,50,0.000,0.000)in
PIN(175,50,0.003,0.000)out
LIG(140,50,150,50)
LIG(150,40,150,60)
LIG(150,40,165,50)
LIG(150,60,165,50)
LIG(167,50,167,50)
LIG(169,50,175,50)
VLG not not1(out,in);
FSYM
SYM  #clock
BB(65,52,80,58)
TITLE 70 55  #clock1
MODEL 69
PROP   10.00 10.00
REC(67,53,6,4,r)
VIS 1
PIN(80,55,0.150,0.002)clk1
LIG(75,55,80,55)
LIG(70,53,68,53)
LIG(74,53,72,53)
LIG(75,52,75,58)
LIG(65,58,65,52)
LIG(70,57,70,53)
LIG(72,53,72,57)
LIG(72,57,70,57)
LIG(68,57,66,57)
LIG(68,53,68,57)
LIG(75,58,65,58)
LIG(75,52,65,52)
FSYM
SYM  #vss
BB(-10,22,0,30)
TITLE -6 27  #vss
MODEL 0
PROP
REC(-10,20,0,0,b)
VIS 0
PIN(-5,20,0.000,0.000)vss
LIG(-5,20,-5,25)
LIG(-10,25,0,25)
LIG(-10,28,-8,25)
LIG(-8,28,-6,25)
LIG(-6,28,-4,25)
LIG(-4,28,-2,25)
FSYM
SYM  #clock
BB(-15,2,0,8)
TITLE -10 5  #clock2
MODEL 69
PROP   20.00 20.00
REC(-13,3,6,4,r)
VIS 1
PIN(0,5,0.150,0.002)clk2
LIG(-5,5,0,5)
LIG(-10,3,-12,3)
LIG(-6,3,-8,3)
LIG(-5,2,-5,8)
LIG(-15,8,-15,2)
LIG(-10,7,-10,3)
LIG(-8,3,-8,7)
LIG(-8,7,-10,7)
LIG(-12,7,-14,7)
LIG(-12,3,-12,7)
LIG(-5,8,-15,8)
LIG(-5,2,-15,2)
FSYM
LIG(40,10,40,20)
LIG(40,20,45,20)
LIG(40,40,40,30)
LIG(40,30,45,30)
LIG(80,25,85,25)
LIG(85,25,85,45)
LIG(85,45,90,45)
LIG(125,50,140,50)
LIG(80,55,90,55)
LIG(0,15,0,35)
LIG(-5,20,0,20)
LIG(0,15,5,15)
LIG(0,45,5,45)
LIG(0,5,5,5)
LIG(0,35,5,35)
FFIG C:\Users\divyo\OneDrive - Indian Institute of Information Technology, Nagpur\Desktop\cmos\layout\example.sch