From 0d9eb9b8e320d79a485f65085445b62ac52fcedb Mon Sep 17 00:00:00 2001 From: David Plass Date: Mon, 26 Jan 2026 12:33:31 -0800 Subject: [PATCH] [Proc-scoped channels] Build all targets in zstd/memory with Codegen 1.5 and proc-scoped channels. PiperOrigin-RevId: 861308637 --- xls/modules/zstd/memory/BUILD | 91 ++++++++++++++--------------------- 1 file changed, 36 insertions(+), 55 deletions(-) diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD index 9ffabd741e..358f1d1b60 100644 --- a/xls/modules/zstd/memory/BUILD +++ b/xls/modules/zstd/memory/BUILD @@ -51,12 +51,15 @@ xls_dslx_library( xls_dslx_test( name = "common_dslx_test", library = ":common_dslx", - tags = ["manual"], ) +COMMON_IR_CONV_ARGS = {"lower_to_proc_scoped_channels": "true"} + CLOCK_PERIOD_PS = "750" -common_codegen_args = { +CODEGEN_VERSION = "1.5" + +COMMON_CODEGEN_ARGS = { "delay_model": "asap7", "reset": "rst", "worst_case_throughput": "1", @@ -71,6 +74,7 @@ common_codegen_args = { # TODO: This should be adjusted when per channel separation of IO options is enabled "flop_inputs_kind": "skid", "flop_outputs_kind": "skid", + "codegen_version": CODEGEN_VERSION, } xls_dslx_library( @@ -86,31 +90,29 @@ xls_dslx_library( xls_dslx_test( name = "axi_reader_dslx_test", library = ":axi_reader_dslx", - tags = ["manual"], ) # FIXME: Improve the proc to achieve CLOCK_PERIOD_PS AXI_READER_CLOCK_PERIOD_PS = "1700" -axi_reader_codegen_args = common_codegen_args | { +AXI_READER_CODEGEN_ARGS = COMMON_CODEGEN_ARGS | { "clock_period_ps": AXI_READER_CLOCK_PERIOD_PS, "module_name": "axi_reader", } xls_dslx_verilog( name = "axi_reader_verilog", - codegen_args = axi_reader_codegen_args, + codegen_args = AXI_READER_CODEGEN_ARGS, dslx_top = "AxiReaderInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":axi_reader_dslx", - tags = ["manual"], verilog_file = "axi_reader.v", ) xls_benchmark_ir( name = "axi_reader_opt_ir_benchmark", src = ":axi_reader_verilog.opt.ir", - benchmark_ir_args = axi_reader_codegen_args, - tags = ["manual"], + benchmark_ir_args = AXI_READER_CODEGEN_ARGS, ) verilog_library( @@ -118,7 +120,6 @@ verilog_library( srcs = [ ":axi_reader.v", ], - tags = ["manual"], ) synthesize_rtl( @@ -161,15 +162,14 @@ xls_dslx_library( xls_dslx_test( name = "axi_stream_remove_empty_dslx_test", library = ":axi_stream_remove_empty_dslx", - tags = ["manual"], ) xls_dslx_verilog( name = "axi_stream_remove_empty_verilog", - codegen_args = common_codegen_args | {"module_name": "axi_stream_remove_empty"}, + codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "axi_stream_remove_empty"}, dslx_top = "AxiStreamRemoveEmptyInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":axi_stream_remove_empty_dslx", - tags = ["manual"], verilog_file = "axi_stream_remove_empty.v", ) @@ -178,7 +178,6 @@ verilog_library( srcs = [ ":axi_stream_remove_empty.v", ], - tags = ["manual"], ) synthesize_rtl( @@ -212,18 +211,17 @@ place_and_route( xls_dslx_verilog( name = "remove_empty_bytes_verilog", - codegen_args = common_codegen_args | {"module_name": "remove_empty_bytes"}, + codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "remove_empty_bytes"}, dslx_top = "RemoveEmptyBytesInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":axi_stream_remove_empty_dslx", - tags = ["manual"], verilog_file = "remove_empty_bytes.v", ) xls_benchmark_ir( name = "remove_empty_bytes_opt_ir_benchmark", src = ":remove_empty_bytes_verilog.opt.ir", - benchmark_ir_args = common_codegen_args, - tags = ["manual"], + benchmark_ir_args = COMMON_CODEGEN_ARGS, ) verilog_library( @@ -231,7 +229,6 @@ verilog_library( srcs = [ ":remove_empty_bytes.v", ], - tags = ["manual"], ) synthesize_rtl( @@ -274,23 +271,21 @@ xls_dslx_library( xls_dslx_test( name = "axi_stream_downscaler_dslx_test", library = ":axi_stream_downscaler_dslx", - tags = ["manual"], ) xls_dslx_verilog( name = "axi_stream_downscaler_verilog", - codegen_args = common_codegen_args | {"module_name": "axi_stream_downscaler"}, + codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "axi_stream_downscaler"}, dslx_top = "AxiStreamDownscalerInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":axi_stream_downscaler_dslx", - tags = ["manual"], verilog_file = "axi_stream_downscaler.v", ) xls_benchmark_ir( name = "axi_stream_downscaler_opt_ir_benchmark", src = ":axi_stream_downscaler_verilog.opt.ir", - benchmark_ir_args = common_codegen_args, - tags = ["manual"], + benchmark_ir_args = COMMON_CODEGEN_ARGS, ) verilog_library( @@ -298,7 +293,6 @@ verilog_library( srcs = [ ":axi_stream_downscaler.v", ], - tags = ["manual"], ) synthesize_rtl( @@ -348,25 +342,25 @@ xls_dslx_test( # FIXME: Improve the proc to achieve CLOCK_PERIOD_PS AXI_RAM_READER_CLOCK_PERIOD_PS = "850" -axi_ram_reader_codegen_args = common_codegen_args | { +AXI_RAM_READER_CODEGEN_ARGS = COMMON_CODEGEN_ARGS | { "module_name": "axi_ram_reader", "clock_period_ps": AXI_RAM_READER_CLOCK_PERIOD_PS, "ram_configurations": "{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format( latency = 1, ram_name = "ram", - rd_req = "axi_ram_reader__rd_req_s", - rd_resp = "axi_ram_reader__rd_resp_r", - wr_req = "axi_ram_reader__wr_req_s", - wr_resp = "axi_ram_reader__wr_resp_r", + rd_req = "_rd_req_s", + rd_resp = "_rd_resp_r", + wr_req = "_wr_req_s", + wr_resp = "_wr_resp_r", ), } xls_dslx_verilog( name = "axi_ram_reader_verilog", - codegen_args = axi_ram_reader_codegen_args, + codegen_args = AXI_RAM_READER_CODEGEN_ARGS, dslx_top = "AxiRamReaderInstWithEmptyWrites", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":axi_ram_reader_dslx", - tags = ["manual"], verilog_file = "axi_ram_reader.v", ) @@ -375,14 +369,12 @@ verilog_library( srcs = [ ":axi_ram_reader.v", ], - tags = ["manual"], ) xls_benchmark_ir( name = "axi_ram_reader_opt_ir_benchmark", src = ":axi_ram_reader_verilog.opt.ir", - benchmark_ir_args = axi_ram_reader_codegen_args, - tags = ["manual"], + benchmark_ir_args = AXI_RAM_READER_CODEGEN_ARGS, ) synthesize_rtl( @@ -429,13 +421,12 @@ xls_dslx_library( xls_dslx_test( name = "mem_reader_dslx_test", library = ":mem_reader_dslx", - tags = ["manual"], ) # FIXME: Improve the proc to achieve CLOCK_PERIOD_PS MEM_READER_CLOCK_PERIOD_PS = "2600" -mem_reader_codegen_args = common_codegen_args | { +mem_reader_codegen_args = COMMON_CODEGEN_ARGS | { "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS, "module_name": "mem_reader", } @@ -444,8 +435,8 @@ xls_dslx_verilog( name = "mem_reader_verilog", codegen_args = mem_reader_codegen_args, dslx_top = "MemReaderInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":mem_reader_dslx", - tags = ["manual"], verilog_file = "mem_reader.v", ) @@ -454,14 +445,12 @@ verilog_library( srcs = [ ":mem_reader.v", ], - tags = ["manual"], ) xls_benchmark_ir( name = "mem_reader_opt_ir_benchmark", src = ":mem_reader_verilog.opt.ir", benchmark_ir_args = mem_reader_codegen_args, - tags = ["manual"], ) synthesize_rtl( @@ -497,8 +486,8 @@ xls_dslx_verilog( name = "mem_reader_adv_verilog", codegen_args = mem_reader_codegen_args | {"module_name": "mem_reader_adv"}, dslx_top = "MemReaderAdvInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":mem_reader_dslx", - tags = ["manual"], verilog_file = "mem_reader_adv.v", ) @@ -506,7 +495,6 @@ xls_benchmark_ir( name = "mem_reader_adv_opt_ir_benchmark", src = ":mem_reader_adv_verilog.opt.ir", benchmark_ir_args = mem_reader_codegen_args, - tags = ["manual"], ) verilog_library( @@ -514,7 +502,6 @@ verilog_library( srcs = [ ":mem_reader_adv.v", ], - tags = ["manual"], ) synthesize_rtl( @@ -559,23 +546,21 @@ xls_dslx_library( xls_dslx_test( name = "axi_writer_dslx_test", library = ":axi_writer_dslx", - tags = ["manual"], ) xls_dslx_verilog( name = "axi_writer_verilog", - codegen_args = common_codegen_args | {"module_name": "axi_writer"}, + codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "axi_writer"}, dslx_top = "AxiWriterInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":axi_writer_dslx", - tags = ["manual"], verilog_file = "axi_writer.v", ) xls_benchmark_ir( name = "axi_writer_opt_ir_benchmark", src = ":axi_writer_verilog.opt.ir", - benchmark_ir_args = common_codegen_args, - tags = ["manual"], + benchmark_ir_args = COMMON_CODEGEN_ARGS, ) verilog_library( @@ -583,7 +568,6 @@ verilog_library( srcs = [ ":axi_writer.v", ], - tags = ["manual"], ) synthesize_rtl( @@ -631,7 +615,7 @@ xls_dslx_test( library = ":axi_stream_add_empty_dslx", ) -axi_stream_add_empty_codegen_args = common_codegen_args | { +axi_stream_add_empty_codegen_args = COMMON_CODEGEN_ARGS | { "module_name": "axi_stream_add_empty", "pipeline_stages": "2", "streaming_channel_data_suffix": "_data", @@ -641,8 +625,8 @@ xls_dslx_verilog( name = "axi_stream_add_empty_verilog", codegen_args = axi_stream_add_empty_codegen_args, dslx_top = "AxiStreamAddEmptyInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":axi_stream_add_empty_dslx", - tags = ["manual"], verilog_file = "axi_stream_add_empty.v", ) @@ -650,7 +634,6 @@ xls_benchmark_ir( name = "axi_stream_add_empty_opt_ir_benchmark", src = ":axi_stream_add_empty_verilog.opt.ir", benchmark_ir_args = axi_stream_add_empty_codegen_args, - tags = ["manual"], ) verilog_library( @@ -658,7 +641,6 @@ verilog_library( srcs = [ ":axi_stream_add_empty.v", ], - tags = ["manual"], ) synthesize_rtl( @@ -710,10 +692,10 @@ xls_dslx_test( xls_dslx_verilog( name = "mem_writer_verilog", - codegen_args = common_codegen_args | {"module_name": "mem_writer"}, + codegen_args = COMMON_CODEGEN_ARGS | {"module_name": "mem_writer"}, dslx_top = "MemWriterInst", + ir_conv_args = COMMON_IR_CONV_ARGS, library = ":mem_writer_dslx", - tags = ["manual"], verilog_file = "mem_writer.v", ) @@ -722,7 +704,6 @@ verilog_library( srcs = [ ":mem_writer.v", ], - tags = ["manual"], ) synthesize_rtl(