Convert the core to Verilog

[mithro]

VHDL is poorly supported by the open source toolchains. Verilog is much better supported.

It would be really awesome if this core was in Verilog instead of VHDL :-P

Then lots of the DisplayPort core could be simulated in Icarus or Verilator to formally proven with something like Yosys.

This is probably a prerequisite for #2.

[mithro]

(I wouldn't mind if it was converted to LiteX / Migen -- or even MyHDL -- instead. They all generates Verilog :-)