I am trying to build a CPU entirely from 1 bit gates, but I'm coming across some performance issues with massive amounts of wires. I think this is a normal issue across Register files where the MUX's traces pretty much define its size. I am asking that some sort of frustrum culling be implemented.
At zoomed in levels, I believe that it should not lag as most wires/components are off frame and do not need to be rendered. I understand there may be overhead in computing wire bounds, but even a simple viewport check per component/wire would help significantly at typical zoom levels.
Here is the (incomplete) register file. There will be 32 separate 16 bit sources. (the image has 28 registers for now). The top contains the registers, The bottom is the wire expensive OR reduction to form the data busses.
There is a lot of wires, and this lags when I pan around, but 90% of the time I am zoomed in when panning around, still experiencing lag.
Unimportant side note: Another thing that could also help is the feature where copy and pasting automatically increments a label, but on tunnels. I would use 1024 tunnels If I could but I do not want to name 512 manually. But, of course, the large catch is tunnels are most often copy and pasted for the second one with the same label. To this, I say that Q should be reserved for preserving labels while copy and paste should increment.
I am trying to build a CPU entirely from 1 bit gates, but I'm coming across some performance issues with massive amounts of wires. I think this is a normal issue across Register files where the MUX's traces pretty much define its size. I am asking that some sort of frustrum culling be implemented.
At zoomed in levels, I believe that it should not lag as most wires/components are off frame and do not need to be rendered. I understand there may be overhead in computing wire bounds, but even a simple viewport check per component/wire would help significantly at typical zoom levels.
Here is the (incomplete) register file. There will be 32 separate 16 bit sources. (the image has 28 registers for now). The top contains the registers, The bottom is the wire expensive OR reduction to form the data busses.
There is a lot of wires, and this lags when I pan around, but 90% of the time I am zoomed in when panning around, still experiencing lag.
Unimportant side note: Another thing that could also help is the feature where copy and pasting automatically increments a label, but on tunnels. I would use 1024 tunnels If I could but I do not want to name 512 manually. But, of course, the large catch is tunnels are most often copy and pasted for the second one with the same label. To this, I say that Q should be reserved for preserving labels while copy and paste should increment.