Hello! I've been experimenting with HardCaml and reviewing the reference projects in the README.
One question arose: How can we conveniently construct a Decoupled IO interface (i.e., the data/ready/valid pattern)?
The key issue seems to be that the directions of ready and valid are inverted. From my current understanding, this might require defining them separately in module I and module O for input/output directions. However, I'm unsure if this is the intended approach or if there’s a more streamlined way to handle such interfaces.
It would be extremely helpful if a minimal implementing provided.
Thank you for your time and support!
Hello! I've been experimenting with HardCaml and reviewing the reference projects in the README.
One question arose: How can we conveniently construct a Decoupled IO interface (i.e., the data/ready/valid pattern)?
The key issue seems to be that the directions of
readyandvalidare inverted. From my current understanding, this might require defining them separately inmodule Iandmodule Ofor input/output directions. However, I'm unsure if this is the intended approach or if there’s a more streamlined way to handle such interfaces.It would be extremely helpful if a minimal implementing provided.
Thank you for your time and support!