From f2c24de2c764b9c9c3d7c33d09645c464fa02095 Mon Sep 17 00:00:00 2001 From: Kent McLeod Date: Tue, 16 Dec 2025 20:35:29 +1100 Subject: [PATCH 1/5] aarch64,hyp: Add support for 1GiB kernel window Add a feature flag that uses a different kernel window map function during boot that maps the kernel window with 1GiB pages instead of 2MiB pages. This enables higher coverage of the memory space to enable access to high untypeds when the platform splits low-mem and high-mem ranges over a distance larger than 512GiB covered by the current window. --- include/arch/arm/arch/64/mode/hardware.h | 8 +++ .../arch/arm/arch/64/mode/model/statedata.h | 5 ++ src/arch/arm/64/kernel/vspace.c | 51 +++++++++++++++++++ src/arch/arm/64/model/statedata.c | 5 ++ src/arch/arm/config.cmake | 11 ++++ 5 files changed, 80 insertions(+) diff --git a/include/arch/arm/arch/64/mode/hardware.h b/include/arch/arm/arch/64/mode/hardware.h index 7b3eff08fb5..e9b1b4ac954 100644 --- a/include/arch/arm/arch/64/mode/hardware.h +++ b/include/arch/arm/arch/64/mode/hardware.h @@ -180,7 +180,11 @@ /* Top of the physical memory window */ #ifdef CONFIG_ARM_HYPERVISOR_SUPPORT +#ifdef CONFIG_ARM_KERNEL_WINDOW_1GIB_PAGES +#define PPTR_TOP UL_CONST(0x0000ffffc0000000) +#else #define PPTR_TOP UL_CONST(0x000000ffc0000000) +#endif #else #define PPTR_TOP UL_CONST(0xffffffffc0000000) #endif @@ -198,7 +202,11 @@ /* This is a page table mapping at the end of the virtual address space * to map objects with 4KiB pages rather than 4MiB large pages. */ #ifdef CONFIG_ARM_HYPERVISOR_SUPPORT +#ifdef CONFIG_ARM_KERNEL_WINDOW_1GIB_PAGES +#define KERNEL_PT_BASE UL_CONST(0x0000ffffffe00000) +#else #define KERNEL_PT_BASE UL_CONST(0x000000ffffe00000) +#endif #else #define KERNEL_PT_BASE UL_CONST(0xffffffffffe00000) #endif diff --git a/include/arch/arm/arch/64/mode/model/statedata.h b/include/arch/arm/arch/64/mode/model/statedata.h index 9f54afaffdb..d966f277a0d 100644 --- a/include/arch/arm/arch/64/mode/model/statedata.h +++ b/include/arch/arm/arch/64/mode/model/statedata.h @@ -28,8 +28,13 @@ extern asid_pool_t *armKSASIDTable[BIT(asidHighBits)] VISIBLE; extern vspace_root_t armKSGlobalUserVSpace[BIT(seL4_VSpaceIndexBits)] VISIBLE; extern pte_t armKSGlobalKernelPGD[BIT(PT_INDEX_BITS)] VISIBLE; +#ifdef CONFIG_ARM_KERNEL_WINDOW_1GIB_PAGES +extern pte_t armKSGlobalKernelPUDs[BIT(PT_INDEX_BITS)-1][BIT(PT_INDEX_BITS)] VISIBLE; +extern pte_t armKSGlobalKernelPD[BIT(PT_INDEX_BITS)] VISIBLE; +#else extern pte_t armKSGlobalKernelPUD[BIT(PT_INDEX_BITS)] VISIBLE; extern pte_t armKSGlobalKernelPDs[BIT(PT_INDEX_BITS)][BIT(PT_INDEX_BITS)] VISIBLE; +#endif extern pte_t armKSGlobalKernelPT[BIT(PT_INDEX_BITS)] VISIBLE; #ifdef CONFIG_ARM_HYPERVISOR_SUPPORT diff --git a/src/arch/arm/64/kernel/vspace.c b/src/arch/arm/64/kernel/vspace.c index fed090bd58e..f8369c51040 100644 --- a/src/arch/arm/64/kernel/vspace.c +++ b/src/arch/arm/64/kernel/vspace.c @@ -233,6 +233,55 @@ BOOT_CODE void map_kernel_frame(paddr_t paddr, pptr_t vaddr, vm_rights_t vm_righ attr_index); } +#ifdef CONFIG_ARM_KERNEL_WINDOW_1GIB_PAGES + +BOOT_CODE void map_kernel_window(void) +{ + + paddr_t paddr; + word_t idx; + + /* verify that the kernel window as at the second entry of the PGD */ + assert(GET_KPT_INDEX(PPTR_BASE, KLVL_FRM_ARM_PT_LVL(0)) == 1); + assert(IS_ALIGNED(PPTR_BASE, seL4_HugePageBits)); + /* verify that the kernel device window is 1gb aligned and 1gb in size */ + assert(GET_KPT_INDEX(PPTR_TOP, KLVL_FRM_ARM_PT_LVL(1)) == BIT(PT_INDEX_BITS) - 1); + assert(IS_ALIGNED(PPTR_TOP, seL4_HugePageBits)); + + // First we map 511 PUDs into the PGD: + for (idx = 1; idx < 512; idx++) { + armKSGlobalKernelPGD[idx] = pte_pte_table_new(addrFromKPPtr(armKSGlobalKernelPUDs[(idx-1)])); + } + + // Next we create a lot of 1GiB PTE mappings but leave the last 1GiB entry empty. + for (idx = 0; idx < ((512*511) - 1); idx++) { + // Mapping in 1GiB increments: + paddr = PADDR_BASE + (idx * (1 << 30)); + + armKSGlobalKernelPUDs[idx / 512][idx % 512] = pte_pte_page_new( +#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT + 0, // XN +#else + 1, // UXN +#endif + paddr, + 0, /* global */ + 1, /* access flag */ + SMP_TERNARY(SMP_SHARE, 0), /* Inner-shareable if SMP enabled, otherwise unshared */ + 0, /* VMKernelOnly */ + NORMAL + ); + } + + // Now need to map the kernel device mappings into the last entry + armKSGlobalKernelPUDs[511 - 1][511] = pte_pte_table_new(addrFromKPPtr(armKSGlobalKernelPD)); + armKSGlobalKernelPD[511] = pte_pte_table_new(addrFromKPPtr(armKSGlobalKernelPT)); + + map_kernel_devices(); +} + +#else /* CONFIG_ARM_KERNEL_WINDOW_1GIB_PAGES */ + BOOT_CODE void map_kernel_window(void) { @@ -297,6 +346,8 @@ BOOT_CODE void map_kernel_window(void) map_kernel_devices(); } +#endif + /* When the hypervisor support is enabled, the stage-2 translation table format * is used for applications. * The global bit is always 0. diff --git a/src/arch/arm/64/model/statedata.c b/src/arch/arm/64/model/statedata.c index 7da4065fa80..bdedfc79c31 100644 --- a/src/arch/arm/64/model/statedata.c +++ b/src/arch/arm/64/model/statedata.c @@ -85,8 +85,13 @@ asid_pool_t *armKSASIDTable[BIT(asidHighBits)]; vspace_root_t armKSGlobalUserVSpace[BIT(seL4_VSpaceIndexBits)] ALIGN_BSS(BIT(seL4_VSpaceBits)); pte_t armKSGlobalKernelPGD[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits)); +#ifdef CONFIG_ARM_KERNEL_WINDOW_1GIB_PAGES +pte_t armKSGlobalKernelPUDs[BIT(PT_INDEX_BITS)-1][BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits)); +pte_t armKSGlobalKernelPD[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits)); +#else pte_t armKSGlobalKernelPUD[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits)); pte_t armKSGlobalKernelPDs[BIT(PT_INDEX_BITS)][BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits)); +#endif pte_t armKSGlobalKernelPT[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits)); #ifdef CONFIG_KERNEL_LOG_BUFFER diff --git a/src/arch/arm/config.cmake b/src/arch/arm/config.cmake index fd9d4e65075..49192e17734 100644 --- a/src/arch/arm/config.cmake +++ b/src/arch/arm/config.cmake @@ -229,6 +229,17 @@ config_choice( "tpidruro;KernelArmTLSRegTPIDRURO;ARM_TLS_REG_TPIDRURO;KernelArchARM" ) +config_option( + KernelArmKernelWindow1GiBPages + ARM_KERNEL_WINDOW_1GIB_PAGES + "Use 1 GiB pages for mapping the bulk of the kernel window. On machines that \ + have large gaps between low and high mappings of DRAM, a 2MiB mapped kernel window \ + that covers 512GiB of address space may not be large enough. A 1GiB mapped kernel \ + window can cover > 255TiB of address space (511 entries in the top level)." + DEFAULT OFF + DEPENDS "KernelSel4ArchAarch64;KernelArmHypervisorSupport" +) + if(KernelArmTLSRegTPIDRURO) set(KernelSetTLSBaseSelf ON) endif() From 384d6c2a2e5f870cd6dd3178085eac037ab77e03 Mon Sep 17 00:00:00 2001 From: Kent McLeod Date: Mon, 24 Nov 2025 12:53:55 +1100 Subject: [PATCH 2/5] gic_v3: Add special LPI handling LPI are a 4th kind of interrupt for "message signalled interrupts". If they are supported by a GICv3 implementation then they may be coupled with an interrupt translation service(ITS). With this set of changes, the seL4 irq handling model can still support physical LPI interrupts provided that the LPI redistributor and ITS service are correctly managed by another system component. A safe way to do this is to statically configure before the kernel boots and the lack of untypeds to the resources used can prevent any other access during runtime. --- include/arch/arm/arch/machine/gic_common.h | 2 +- include/arch/arm/arch/machine/gic_v3.h | 10 ++++++++++ include/object/structures_32.bf | 5 ----- include/object/structures_64.bf | 5 ----- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/arch/arm/arch/machine/gic_common.h b/include/arch/arm/arch/machine/gic_common.h index 584d1b5088c..f19ed7d6052 100644 --- a/include/arch/arm/arch/machine/gic_common.h +++ b/include/arch/arm/arch/machine/gic_common.h @@ -61,7 +61,7 @@ irq_t irqInvalid = (uint16_t) -1; /* Setters/getters helpers for hardware irqs */ #define IRQ_REG(IRQ) ((IRQ) >> 5u) #define IRQ_BIT(IRQ) ((IRQ) & 0x1f) -#define IS_IRQ_VALID(X) (((X) & IRQ_MASK) < SPECIAL_IRQ_START) +#define IS_IRQ_VALID(X) (((X) & IRQ_MASK) != IRQ_NONE) /* * The only sane way to get an GIC IRQ number that can be properly diff --git a/include/arch/arm/arch/machine/gic_v3.h b/include/arch/arm/arch/machine/gic_v3.h index 035ffdeb9fa..2212c06a69e 100644 --- a/include/arch/arm/arch/machine/gic_v3.h +++ b/include/arch/arm/arch/machine/gic_v3.h @@ -295,6 +295,10 @@ static inline bool_t isIRQPending(void) static inline void maskInterrupt(bool_t disable, irq_t irq) { + if (irq > 8192) { + // Cannot enable or disable LPI interrupts + return; + } #if defined ENABLE_SMP_SUPPORT assert(!(IRQ_IS_PPI(irq)) || (IRQT_TO_CORE(irq) == getCurrentCPUIndex())); #endif @@ -307,6 +311,12 @@ static inline void maskInterrupt(bool_t disable, irq_t irq) } +// From the spec: "PPIs, SGIs, and SPIs have an active state in the IRI and must be deactivated." +// And: "A valid write to ICC_EOIR0_EL1 or ICC_EOIR1_EL1 to perform a priority drop is required for each +// acknowledged interrupt, even for LPIs which do not have an active state." +// We use Split EOIMode and perform a priority drop for all interrupts received in handleInterrupt. +// deactivateInterrupt does not need to be called for LPIs. +// This means userspace does not need to perform an ack invocation for LPI interrupts. static inline void deactivateInterrupt(irq_t irq) { word_t hw_irq = IRQT_TO_IRQ(irq); diff --git a/include/object/structures_32.bf b/include/object/structures_32.bf index c1ff7af181a..f07080d363f 100644 --- a/include/object/structures_32.bf +++ b/include/object/structures_32.bf @@ -99,12 +99,7 @@ block irq_control_cap { } block irq_handler_cap { -#ifdef ENABLE_SMP_SUPPORT field capIRQ 32 -#else - padding 24 - field capIRQ 8 -#endif padding 24 field capType 8 diff --git a/include/object/structures_64.bf b/include/object/structures_64.bf index b642d0af8c0..28db185d831 100644 --- a/include/object/structures_64.bf +++ b/include/object/structures_64.bf @@ -147,12 +147,7 @@ block irq_control_cap { } block irq_handler_cap { -#ifdef ENABLE_SMP_SUPPORT field capIRQ 64 -#else - padding 52 - field capIRQ 12 -#endif field capType 5 padding 59 From 66c867f0a2ad2b3d283c54a78d683474e59bd36f Mon Sep 17 00:00:00 2001 From: Kent McLeod Date: Tue, 16 Dec 2025 20:06:03 +1100 Subject: [PATCH 3/5] vcpu,aarch64: Allow injection of up to 65536 irqs This check was too narrow for the platform configuration. The hardware can support injecting much larger interrupt numbers. --- src/arch/arm/object/vcpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/arch/arm/object/vcpu.c b/src/arch/arm/object/vcpu.c index d91a8aeb6bf..90ff1b427fb 100644 --- a/src/arch/arm/object/vcpu.c +++ b/src/arch/arm/object/vcpu.c @@ -424,7 +424,11 @@ exception_t decodeVCPUInjectIRQ(cap_t cap, word_t length, word_t *buffer) #endif /* Check IRQ parameters */ +#if defined(CONFIG_ARM_GIC_V3_SUPPORT) && defined(CONFIG_ARCH_AARCH64) + if (vid > (1U << 16) - 1) { +#else if (vid > (1U << 10) - 1) { +#endif current_syscall_error.type = seL4_RangeError; current_syscall_error.rangeErrorMin = 0; current_syscall_error.rangeErrorMax = (1U << 10) - 1; From 50b897015bc3737a3a22213ad13abcec9f75fc8a Mon Sep 17 00:00:00 2001 From: Kent McLeod <1759184+kent-mcleod@users.noreply.github.com> Date: Wed, 8 Oct 2025 15:28:47 +1100 Subject: [PATCH 4/5] Arm, Neoverse: Add support for N1 core families This adds initial build support for NeoverseN1 cores --- configs/seL4Config.cmake | 4 ++++ include/arch/arm/armv/armv8-a/64/armv/vcpu.h | 4 ++++ .../aarch64/sel4/sel4_arch/constants.h | 2 ++ src/arch/arm/config.cmake | 12 +++++++++++- 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/configs/seL4Config.cmake b/configs/seL4Config.cmake index 64321918965..920efb9a560 100644 --- a/configs/seL4Config.cmake +++ b/configs/seL4Config.cmake @@ -147,6 +147,7 @@ foreach( KernelArmCortexA55 KernelArmCortexA57 KernelArmCortexA72 + KernelArmNeoverseN1 KernelArchArmV7a KernelArchArmV7ve KernelArchArmV8a @@ -194,6 +195,7 @@ config_set(KernelArmCortexA53 ARM_CORTEX_A53 "${KernelArmCortexA53}") config_set(KernelArmCortexA55 ARM_CORTEX_A55 "${KernelArmCortexA55}") config_set(KernelArmCortexA57 ARM_CORTEX_A57 "${KernelArmCortexA57}") config_set(KernelArmCortexA72 ARM_CORTEX_A72 "${KernelArmCortexA72}") +config_set(KernelArmNeoverseN1 ARM_NEOVERSE_N1 "${KernelArmNeoverseN1}") config_set(KernelArchArmV7a ARCH_ARM_V7A "${KernelArchArmV7a}") config_set(KernelArchArmV7ve ARCH_ARM_V7VE "${KernelArchArmV7ve}") config_set(KernelArchArmV8a ARCH_ARM_V8A "${KernelArchArmV8a}") @@ -227,6 +229,8 @@ elseif(KernelArmCortexA57) set(KernelArmCPU "cortex-a57" CACHE INTERNAL "") elseif(KernelArmCortexA72) set(KernelArmCPU "cortex-a72" CACHE INTERNAL "") +elseif(KernelArmNeoverseN1) + set(KernelArmCPU "neoverse-n1" CACHE INTERNAL "") endif() if(KernelArchARM) config_set(KernelArmMach ARM_MACH "${KernelArmMach}") diff --git a/include/arch/arm/armv/armv8-a/64/armv/vcpu.h b/include/arch/arm/armv/armv8-a/64/armv/vcpu.h index ff5813182e6..6263afae2cb 100644 --- a/include/arch/arm/armv/armv8-a/64/armv/vcpu.h +++ b/include/arch/arm/armv/armv8-a/64/armv/vcpu.h @@ -596,6 +596,10 @@ static inline void vcpu_init_vtcr(void) vtcr_el2 = VTCR_EL2_T0SZ(24); // 40-bit input IPA vtcr_el2 |= VTCR_EL2_PS(PS_1T); // 40-bit PA size vtcr_el2 |= VTCR_EL2_SL0(SL0_4K_L1); // 4KiB, start at level 1 +#elif defined(CONFIG_ARM_PA_SIZE_BITS_48) + vtcr_el2 = VTCR_EL2_T0SZ(16); // 48-bit input IPA + vtcr_el2 |= VTCR_EL2_PS(PS_256T); // 48-bit PA size + vtcr_el2 |= VTCR_EL2_SL0(SL0_4K_L0); // 4KiB, start at level 0 #else vtcr_el2 = VTCR_EL2_T0SZ(20); // 44-bit input IPA vtcr_el2 |= VTCR_EL2_PS(PS_16T); // 44-bit PA size diff --git a/libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/constants.h b/libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/constants.h index f99e2f28e68..9ae9a32d1e6 100644 --- a/libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/constants.h +++ b/libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/constants.h @@ -247,6 +247,8 @@ SEL4_SIZE_SANITY(seL4_VSpaceEntryBits, seL4_VSpaceIndexBits, seL4_VSpaceBits); #define seL4_UserTop 0x00000fffffffffff #elif defined(CONFIG_ARM_PA_SIZE_BITS_40) #define seL4_UserTop 0x000000ffffffffff +#elif defined(CONFIG_ARM_PA_SIZE_BITS_48) +#define seL4_UserTop 0x0000ffffffffffff #else #error "Unknown physical address width" #endif diff --git a/src/arch/arm/config.cmake b/src/arch/arm/config.cmake index 49192e17734..2ac6ada0489 100644 --- a/src/arch/arm/config.cmake +++ b/src/arch/arm/config.cmake @@ -12,6 +12,7 @@ endif() set(KernelArmPASizeBits40 OFF) set(KernelArmPASizeBits44 OFF) +set(KernelArmPASizeBits48 OFF) if(KernelArmCortexA35) set(KernelArmICacheVIPT ON) set(KernelArmPASizeBits40 ON) @@ -32,9 +33,17 @@ elseif(KernelArmCortexA72) # (https://developer.arm.com/documentation/100095/0001/memory-management-unit/about-the-mmu) set(KernelArmPASizeBits44 ON) math(EXPR KernelPaddrUserTop "(1 << 44)") +elseif(KernelArmNeoverseN1) + # For Neoverse N1 in AArch64 state, the physical address range is 48 bits + set(KernelArmPASizeBits48 ON) + # The max physical address for kernel untypeds is still capped at 1 << 47 + # because the kernel window isn't the full 48 bits. + math(EXPR KernelPaddrUserTop "(1 << 47)") endif() + config_set(KernelArmPASizeBits40 ARM_PA_SIZE_BITS_40 "${KernelArmPASizeBits40}") config_set(KernelArmPASizeBits44 ARM_PA_SIZE_BITS_44 "${KernelArmPASizeBits44}") +config_set(KernelArmPASizeBits48 ARM_PA_SIZE_BITS_48 "${KernelArmPASizeBits48}") config_set(KernelArmICacheVIPT ARM_ICACHE_VIPT "${KernelArmICacheVIPT}") if(KernelSel4ArchAarch32) @@ -86,7 +95,7 @@ config_option( "Build as Hypervisor. Utilise ARM virtualisation extensions to build the kernel as a hypervisor" DEFAULT ${KernelSel4ArchArmHyp} DEPENDS - "KernelArmCortexA15 OR KernelArmCortexA35 OR KernelArmCortexA57 OR KernelArmCortexA53 OR KernelArmCortexA55 OR KernelArmCortexA72" + "KernelArmCortexA15 OR KernelArmCortexA35 OR KernelArmCortexA57 OR KernelArmCortexA53 OR KernelArmCortexA55 OR KernelArmCortexA72 OR KernelArmNeoverseN1" ) config_option(KernelArmGicV3 ARM_GIC_V3_SUPPORT "Build support for GICv3" DEFAULT OFF) @@ -257,6 +266,7 @@ if( OR KernelArmCortexA55 OR KernelArmCortexA57 OR KernelArmCortexA72 + OR KernelArmNeoverseN1 ) # According to https://developer.arm.com/documentation/100095/0001/functional-description/about-the-cortex-a72-processor-functions/components-of-the-processor # the L1 instruction on the Cortex-A72 cache has a 64-byte cache line. From 7303978c42fb8fce4c28599c4f4cce2f4d41ecef Mon Sep 17 00:00:00 2001 From: Kent McLeod <1759184+kent-mcleod@users.noreply.github.com> Date: Tue, 7 Oct 2025 08:27:01 +1100 Subject: [PATCH 5/5] altra: Add initial platform details --- .../altra/sel4/plat/api/constants.h | 9 + src/plat/altra/config.cmake | 32 + src/plat/altra/overlay-altra.dts | 18 + tools/dts/altra.dts | 756 ++++++++++++++++++ 4 files changed, 815 insertions(+) create mode 100644 libsel4/sel4_plat_include/altra/sel4/plat/api/constants.h create mode 100644 src/plat/altra/config.cmake create mode 100644 src/plat/altra/overlay-altra.dts create mode 100644 tools/dts/altra.dts diff --git a/libsel4/sel4_plat_include/altra/sel4/plat/api/constants.h b/libsel4/sel4_plat_include/altra/sel4/plat/api/constants.h new file mode 100644 index 00000000000..49e76072bea --- /dev/null +++ b/libsel4/sel4_plat_include/altra/sel4/plat/api/constants.h @@ -0,0 +1,9 @@ +/* + * Copyright 2025, Kry10 Limited. + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#pragma once + +#include diff --git a/src/plat/altra/config.cmake b/src/plat/altra/config.cmake new file mode 100644 index 00000000000..0fd940dff39 --- /dev/null +++ b/src/plat/altra/config.cmake @@ -0,0 +1,32 @@ +# +# Copyright 2025, Kry10 Limited. +# +# SPDX-License-Identifier: GPL-2.0-only +# + +declare_platform(altra KernelPlatformAltra PLAT_ALTRA KernelArchARM) + +if(KernelPlatformAltra) + declare_seL4_arch(aarch64) + # TODO update this to neoverse when needed + set(KernelArmNeoverseN1 ON) + set(KernelArchArmV8a ON) + set(KernelArmGicV3 ON) + config_set(KernelARMPlatform ARM_PLAT ${KernelPlatform}) + list(APPEND KernelDTSList "tools/dts/${KernelPlatform}.dts") + list(APPEND KernelDTSList "src/plat/altra/overlay-${KernelPlatform}.dts") + declare_default_headers( + TIMER_FREQUENCY 25000000 + TIMER drivers/timer/arm_generic.h + TIMER_OVERHEAD_TICKS 1 + NUM_PPI 32 + MAX_IRQ 16383 + INTERRUPT_CONTROLLER arch/machine/gic_v3.h + KERNEL_WCET 10u + ) +endif() + +add_sources( + DEP "KernelPlatformAltra" + CFILES src/arch/arm/machine/gic_v3.c src/arch/arm/machine/l2c_nop.c +) diff --git a/src/plat/altra/overlay-altra.dts b/src/plat/altra/overlay-altra.dts new file mode 100644 index 00000000000..8da87713aa1 --- /dev/null +++ b/src/plat/altra/overlay-altra.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2025, Kry10 Limited. + * + * SPDX-License-Identifier: GPL-2.0-only + */ + +/ { + chosen { + seL4,elfloader-devices = + &{/timer}; + + seL4,kernel-devices = + &{/armpl011@100002600000}, + &{/intc@gic}, + &{/timer}; + }; + +}; diff --git a/tools/dts/altra.dts b/tools/dts/altra.dts new file mode 100644 index 00000000000..fa7d48ffead --- /dev/null +++ b/tools/dts/altra.dts @@ -0,0 +1,756 @@ +/* + * Copyright 2025, Kry10 Limited. + * + * SPDX-License-Identifier: GPL-2.0-only + */ + +/* Generated from uefi dumping tools */ +/dts-v1/; + +/ { + type = "device-tree"; + #address-cells = <2>; + #size-cells = <2>; + compatible = "linux,dummy-virt"; + interrupt-parent = <&intc>; + chosen { + type = "chosen"; + stdout-path = "/armpl011@100002600000"; + bootargs = "console=ttyAMA0"; + }; + timer { + type = "timer"; + compatible = "arm,armv8-timer"; + interrupts = <0x1 0xd 0xf08 0x1 0xe 0xf08 0x1 0xb 0xf08 0x1 0xa 0xf08>; + }; + armpl011@100002600000 { + type = "serial"; + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000 0x2600000 0x0 0x1000>; + interrupts = <0 98 4>; + // clocks = <&apb_pclk>; + // clock-names = "apb_pclk"; + current-speed = <115200>; + }; + serial@100002620000 { + type = "serial"; + compatible = "arm,sbsa-uart"; + reg = <0x1000 0x2620000 0x0 0x1000>; + current-speed = <115200>; + }; + pcie_seg12@33fff0000000 { + type = "pci"; + device_type = "pci"; + reg = <0x33ff 0xf0000000 0x0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + linux,pci-domain = <12>; + numa-node-id = <0>; + status = "okay"; + }; + pcie_seg13@37fff0000000 { + type = "pci"; + device_type = "pci"; + reg = <0x37ff 0xf0000000 0x0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + linux,pci-domain = <13>; + numa-node-id = <1>; + status = "okay"; + }; + pcie_seg1@3bfff0000000 { + type = "pci"; + device_type = "pci"; + reg = <0x3bff 0xf0000000 0x0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + linux,pci-domain = <1>; + numa-node-id = <2>; + status = "okay"; + }; + pcie@3ffff0000000 { + type = "pci"; + device_type = "pci"; + reg = <0x3fff 0xf0000000 0x0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + numa-node-id = <3>; + status = "okay"; + }; + pcie_seg2@23fff0000000 { + type = "pci"; + device_type = "pci"; + reg = <0x23ff 0xf0000000 0x0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + linux,pci-domain = <2>; + numa-node-id = <4>; + status = "okay"; + }; + pcie_seg3@27fff0000000 { + type = "pci"; + device_type = "pci"; + reg = <0x27ff 0xf0000000 0x0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + linux,pci-domain = <3>; + numa-node-id = <5>; + status = "okay"; + }; + pcie_seg4@2bfff0000000 { + type = "pci"; + device_type = "pci"; + reg = <0x2bff 0xf0000000 0x0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + linux,pci-domain = <4>; + numa-node-id = <6>; + status = "okay"; + }; + pcie_seg5@2ffff0000000 { + type = "pci"; + device_type = "pci"; + reg = <0x2fff 0xf0000000 0x0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + linux,pci-domain = <5>; + numa-node-id = <7>; + status = "okay"; + }; + apb-pclk { + type = "clock"; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk24mhz"; + // phandle = <&apb_pclk>; + }; + cpus { + type = "cpus"; + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0>; + enable-method = "psci"; + }; + cpu@1 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <1>; + enable-method = "psci"; + }; + cpu@2 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <2>; + enable-method = "psci"; + }; + cpu@3 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <3>; + enable-method = "psci"; + }; + cpu@4 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <4>; + enable-method = "psci"; + }; + cpu@5 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <5>; + enable-method = "psci"; + }; + cpu@6 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <6>; + enable-method = "psci"; + }; + cpu@7 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <7>; + enable-method = "psci"; + }; + cpu@8 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <8>; + enable-method = "psci"; + }; + cpu@9 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <9>; + enable-method = "psci"; + }; + cpu@10 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <10>; + enable-method = "psci"; + }; + cpu@11 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <11>; + enable-method = "psci"; + }; + cpu@12 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <12>; + enable-method = "psci"; + }; + cpu@13 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <13>; + enable-method = "psci"; + }; + cpu@14 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <14>; + enable-method = "psci"; + }; + cpu@15 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <15>; + enable-method = "psci"; + }; + cpu@16 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <16>; + enable-method = "psci"; + }; + cpu@17 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <17>; + enable-method = "psci"; + }; + cpu@18 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <18>; + enable-method = "psci"; + }; + cpu@19 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <19>; + enable-method = "psci"; + }; + cpu@20 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <20>; + enable-method = "psci"; + }; + cpu@21 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <21>; + enable-method = "psci"; + }; + cpu@22 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <22>; + enable-method = "psci"; + }; + cpu@23 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <23>; + enable-method = "psci"; + }; + cpu@24 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <24>; + enable-method = "psci"; + }; + cpu@25 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <25>; + enable-method = "psci"; + }; + cpu@26 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <26>; + enable-method = "psci"; + }; + cpu@27 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <27>; + enable-method = "psci"; + }; + cpu@28 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <28>; + enable-method = "psci"; + }; + cpu@29 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <29>; + enable-method = "psci"; + }; + cpu@30 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <30>; + enable-method = "psci"; + }; + cpu@31 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <31>; + enable-method = "psci"; + }; + cpu@32 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <32>; + enable-method = "psci"; + }; + cpu@33 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <33>; + enable-method = "psci"; + }; + cpu@34 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <34>; + enable-method = "psci"; + }; + cpu@35 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <35>; + enable-method = "psci"; + }; + cpu@36 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <36>; + enable-method = "psci"; + }; + cpu@37 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <37>; + enable-method = "psci"; + }; + cpu@38 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <38>; + enable-method = "psci"; + }; + cpu@39 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <39>; + enable-method = "psci"; + }; + cpu@40 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <40>; + enable-method = "psci"; + }; + cpu@41 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <41>; + enable-method = "psci"; + }; + cpu@42 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <42>; + enable-method = "psci"; + }; + cpu@43 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <43>; + enable-method = "psci"; + }; + cpu@44 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <44>; + enable-method = "psci"; + }; + cpu@45 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <45>; + enable-method = "psci"; + }; + cpu@46 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <46>; + enable-method = "psci"; + }; + cpu@47 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <47>; + enable-method = "psci"; + }; + cpu@48 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <48>; + enable-method = "psci"; + }; + cpu@49 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <49>; + enable-method = "psci"; + }; + cpu@50 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <50>; + enable-method = "psci"; + }; + cpu@51 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <51>; + enable-method = "psci"; + }; + cpu@52 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <52>; + enable-method = "psci"; + }; + cpu@53 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <53>; + enable-method = "psci"; + }; + cpu@54 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <54>; + enable-method = "psci"; + }; + cpu@55 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <55>; + enable-method = "psci"; + }; + cpu@56 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <56>; + enable-method = "psci"; + }; + cpu@57 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <57>; + enable-method = "psci"; + }; + cpu@58 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <58>; + enable-method = "psci"; + }; + cpu@59 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <59>; + enable-method = "psci"; + }; + cpu@60 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <60>; + enable-method = "psci"; + }; + cpu@61 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <61>; + enable-method = "psci"; + }; + cpu@62 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <62>; + enable-method = "psci"; + }; + cpu@63 { + type = "cpu"; + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <63>; + enable-method = "psci"; + }; + }; + intc: intc@gic { + type = "interrupt-controller"; + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <0x01 0x09 0x04>; + interrupt-parent = <0x01>; + phandle = <0x01>; + reg = <0x1001 0x0 0x0 0x10000 0x1001 0x740000 0x0 0x1000000>; + }; + its@100100040000 { + type = "msi-controller"; + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x1001 0x40000 0x0 0x20000>; + // phandle = <&its>; + }; + memory@0 { + type = "memory"; + device_type = "memory"; + reg = <0x802 0x0 0x2 0x0>; + + reserved-memory { + type = "reserved-memory"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reserved@88300000 { + type = "reserved"; + reg = <0x0 0x88300000 0x0 0x100000>; + no-map; + }; + reserved@91cf0000 { + type = "reserved"; + reg = <0x0 0x91cf0000 0x0 0x100000>; + no-map; + }; + reserved@92000000 { + type = "reserved"; + reg = <0x0 0x92000000 0x0 0x780000>; + no-map; + }; + reserved@e60e0000 { + type = "reserved"; + reg = <0x0 0xe60e0000 0x0 0x1010000>; + no-map; + }; + reserved@e9310000 { + type = "reserved"; + reg = <0x0 0xe9310000 0x0 0x50000>; + no-map; + }; + reserved@e9370000 { + type = "reserved"; + reg = <0x0 0xe9370000 0x0 0x30000>; + no-map; + }; + reserved@e93d0000 { + type = "reserved"; + reg = <0x0 0xe93d0000 0x0 0x10000>; + no-map; + }; + reserved@e97b0000 { + type = "reserved"; + reg = <0x0 0xe97b0000 0x0 0x10000>; + no-map; + }; + reserved@e9940000 { + type = "reserved"; + reg = <0x0 0xe9940000 0x0 0x10000>; + no-map; + }; + reserved@e9b8c000 { + type = "reserved"; + reg = <0x0 0xe9b8c000 0x0 0x91000>; + no-map; + }; + reserved@e9d00000 { + type = "reserved"; + reg = <0x0 0xe9d00000 0x0 0x1010000>; + no-map; + }; + reserved@ec5a0000 { + type = "reserved"; + reg = <0x0 0xec5a0000 0x0 0x10000>; + no-map; + }; + reserved@ec6c0000 { + type = "reserved"; + reg = <0x0 0xec6c0000 0x0 0x10000>; + no-map; + }; + reserved@f3280000 { + type = "reserved"; + reg = <0x0 0xf3280000 0x0 0x1010000>; + no-map; + }; + reserved@f4290000 { + type = "reserved"; + reg = <0x0 0xf4290000 0x0 0x10000>; + no-map; + }; + reserved@f4670000 { + type = "reserved"; + reg = <0x0 0xf4670000 0x0 0x1010000>; + no-map; + }; + reserved@f57d0000 { + type = "reserved"; + reg = <0x0 0xf57d0000 0x0 0x2020000>; + no-map; + }; + reserved@f7a50000 { + type = "reserved"; + reg = <0x0 0xf7a50000 0x0 0x30000>; + no-map; + }; + reserved@f7ad0000 { + type = "reserved"; + reg = <0x0 0xf7ad0000 0x0 0x90000>; + no-map; + }; + reserved@f7d80000 { + type = "reserved"; + reg = <0x0 0xf7d80000 0x0 0x10000>; + no-map; + }; + reserved@f8390000 { + type = "reserved"; + reg = <0x0 0xf8390000 0x0 0x2010000>; + no-map; + }; + reserved@faeae000 { + type = "reserved"; + reg = <0x0 0xfaeae000 0x0 0x2000>; + no-map; + }; + reserved@faeb0000 { + type = "reserved"; + reg = <0x0 0xfaeb0000 0x0 0x10000>; + no-map; + }; + reserved@faf00000 { + type = "reserved"; + reg = <0x0 0xfaf00000 0x0 0x20000>; + no-map; + }; + reserved@fb350000 { + type = "reserved"; + reg = <0x0 0xfb350000 0x0 0x22e0000>; + no-map; + }; + reserved@ff610000 { + type = "reserved"; + reg = <0x0 0xff610000 0x0 0x730000>; + no-map; + }; + }; +};