Note section 4.1Link status of Section 1 of the doc states:
The link status of each port is available in the ESC DL status register (0x0110:0x0111), most
important are the “communication established” bits 15, 13, 11, and 9.
Further more in section 5.6.1.3 MI link detection and configuration it says that physical link can be established but the com may not be active (just a scenarios where physical link is up but communication is NOT established):
Since the MI link detection does not solely rely on the PHY link status bit (register 1[2]), the local PHY
and the remote PHY may indicate a link, but the ESC refuses it because it does not fulfill EtherCAT
requirements.
I think to determine open port or more important the topology we need to consider both ESC DL status register (0x0110[15,13,11,9] – Communication established), and ESC DL status register (0x0110[14,12,10,8] – loop open/closed).
Note section 4.1Link status of Section 1 of the doc states:
The link status of each port is available in the ESC DL status register (0x0110:0x0111), most
important are the “communication established” bits 15, 13, 11, and 9.
Further more in section 5.6.1.3 MI link detection and configuration it says that physical link can be established but the com may not be active (just a scenarios where physical link is up but communication is NOT established):
Since the MI link detection does not solely rely on the PHY link status bit (register 1[2]), the local PHY
and the remote PHY may indicate a link, but the ESC refuses it because it does not fulfill EtherCAT
requirements.
I think to determine open port or more important the topology we need to consider both ESC DL status register (0x0110[15,13,11,9] – Communication established), and ESC DL status register (0x0110[14,12,10,8] – loop open/closed).