I want to add a verilator-generated uart model to RISCV-TLM project, but running dhrystone gives an error.

[Alan-19950616]

error message

nuclei@nuclei-v:~/FastModel/RISC-V-TLM/build$ ./RISCV_TLM ../tests/C/dhrystone/dhrystone.hex 

        SystemC 2.3.4-Accellera --- Aug 17 2023 19:11:19
        Copyright (c) 1996-2022 by all Contributors,
        ALL RIGHTS RESERVED
file: ../tests/C/dhrystone/dhrystone.hex
02 extended address 0x10000
03 PC set to 0x100a6
Created CPURV32 CPU

Warning: (W116) channel doesn't have a default event
In file: /home/nuclei/FastModel/systemc-2.3.4/src/sysc/communication/sc_interface.cpp:54
pure virtual method called
terminate called without an active exception

Warning: (W116) channel doesn't have a default event
In file: /home/nuclei/FastModel/systemc-2.3.4/src/sysc/communication/sc_interface.cpp:54
pure virtual method called
terminate called without an active exception
Aborted (core dumped)

code changes

1. Added files and directories
   ├── model
   │   ├── Vapb_uart_sv.a
   │   └── Vapb_uart_sv.h
   ├── inc
   │   ├── Uart.h
   ├── src
   │   ├── Uart.cpp

• Vapb_uart_sv.h

// Verilated -*- SystemC -*-
// DESCRIPTION: Verilator output: Primary model header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.

#ifndef VERILATED_VAPB_UART_SV_H_
#define VERILATED_VAPB_UART_SV_H_  // guard

#include "systemc.h"
#include "verilated_sc.h"
#include "verilated.h"

class Vapb_uart_sv__Syms;
class Vapb_uart_sv___024root;

// This class is the main interface to the Verilated model
class alignas(VL_CACHE_LINE_BYTES) Vapb_uart_sv VL_NOT_FINAL : public ::sc_core::sc_module, public VerilatedModel {
  private:
    // Symbol table holding complete model state (owned by this class)
    Vapb_uart_sv__Syms* const vlSymsp;

  public:

    // PORTS
    // The application code writes and reads these signals to
    // propagate new values into/out from the Verilated model.
    sc_in<bool> &CLK;
    sc_in<bool> &RSTN;
    sc_in<bool> &PWRITE;
    sc_in<bool> &PSEL;
    sc_in<bool> &PENABLE;
    sc_out<bool> &PREADY;
    sc_out<bool> &PSLVERR;
    sc_in<bool> &rx_i;
    sc_out<bool> &tx_o;
    sc_out<bool> &event_o;
    sc_in<uint32_t> &PADDR;
    sc_in<uint32_t> &PWDATA;
    sc_out<uint32_t> &PRDATA;

    // CELLS
    // Public to allow access to /* verilator public */ items.
    // Otherwise the application code can consider these internals.

    // Root instance pointer to allow access to model internals,
    // including inlined /* verilator public_flat_* */ items.
    Vapb_uart_sv___024root* const rootp;

    // CONSTRUCTORS
    SC_CTOR(Vapb_uart_sv);
    virtual ~Vapb_uart_sv();
  private:
    VL_UNCOPYABLE(Vapb_uart_sv);  ///< Copying not allowed

  public:
    // API METHODS
  private:
    void eval() { eval_step(); }
    void eval_step();
  public:
    void final();
    /// Are there scheduled events to handle?
    bool eventsPending();
    /// Returns time at next time slot. Aborts if !eventsPending()
    uint64_t nextTimeSlot();

    // Abstract methods from VerilatedModel
    const char* hierName() const override final;
    const char* modelName() const override final;
    unsigned threads() const override final;
};

#endif  // guard

• Uart.h

/*!
 \file Uart.h
 \brief Basic TLM-2 Uart module
 \author wangyanwen@nucleisys.com
 \date 2023/8/14
 */
// SPDX-License-Identifier: GPL-3.0-or-later

#ifndef __UART_H__
#define __UART_H__

#include <iostream>
#include <fstream>

#define SC_INCLUDE_DYNAMIC_PROCESSES

#include "systemc"

#include "tlm.h"
#include "tlm_utils/simple_target_socket.h"

#include "BusCtrl.h"

#include "Vapb_uart_sv.h"

namespace riscv_tlm::peripherals {
/**
 * @brief Nuclei Uart peripheral
 */
    class Uart : sc_core::sc_module {
    public:
        // TLM-2 socket, defaults to 32-bits wide, base protocol
        tlm_utils::simple_target_socket<Uart> socket;

        tlm_utils::simple_initiator_socket<Uart> irq_line;

        /**
         *
         * @brief Constructor
         * @param name module name
         */
        explicit Uart(sc_core::sc_module_name const &name);

        /**
        * @brief Destructor
        */
        ~Uart() override;

        /**
         * @brief Waits for event timer_event and triggers an IRQ
         *
         * Waits for event timer_event and triggers an IRQ (if it is not already
         * triggered).
         * After that, it posts the timer_event to 20 ns in the future to clear the IRQ
         * line.
         *
         */
        [[noreturn]] void run();

        /**
         *
         * @brief TLM-2.0 socket implementation
         * @param trans TLM-2.0 transaction
         * @param delay transaction delay time
         */
        virtual void b_transport(tlm::tlm_generic_payload &trans,
                                 sc_core::sc_time &delay);

    private:
        Vapb_uart_sv* uart;
        sc_signal<bool> RSTN;
        sc_signal<bool> PWRITE;
        sc_signal<bool> PSEL;
        sc_signal<bool> PENABLE;
        sc_signal<bool> PREADY;
        sc_signal<bool> PSLVERR;
        sc_signal<bool> rx_i;
        sc_signal<bool> tx_o;
        sc_signal<bool> event_o;
        sc_signal<uint32_t> PADDR;
        sc_signal<uint32_t> PWDATA;
        sc_signal<uint32_t> PRDATA;
        sc_core::sc_event uart_event; /**< event */
    };
}
#endif

• Uart.cpp

/*!
 \file Uart.cpp
 \brief Basic TLM-2 Uart module
 \author wangyanwen@nucleisys.com
 \date 2023/8/14
 */
// SPDX-License-Identifier: GPL-3.0-or-later

#include "Uart.h"

namespace riscv_tlm::peripherals {

    SC_HAS_PROCESS(Uart);

    Uart::Uart(sc_core::sc_module_name const &name) :
            sc_module(name), socket("uart_socket") {

        socket.register_b_transport(this, &Uart::b_transport);

        SC_THREAD(run);

        uart = new Vapb_uart_sv{"apb_uart_sv"};
        sc_clock CLK{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
        RSTN.write(0);

        uart->CLK(CLK);
        uart->RSTN(RSTN);
        uart->PWRITE(PWRITE);
        uart->PSEL(PSEL);
        uart->PENABLE(PENABLE);
        uart->PREADY(PREADY);//output
        uart->PSLVERR(PSLVERR);//output
        uart->rx_i(rx_i);
        uart->tx_o(tx_o);//output
        uart->event_o(event_o);//output
        uart->PADDR(PADDR);
        uart->PWDATA(PWDATA);
        uart->PRDATA(PRDATA);//output
    }

    Uart::~Uart() {
        delete uart;
    }

    [[noreturn]] void Uart::run() {

        RSTN.write(1);

        auto *irq_trans = new tlm::tlm_generic_payload;
        sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
        std::uint32_t cause = 1 << 31 | 0x08;     // Machine uart interrupt
        irq_trans->set_command(tlm::TLM_WRITE_COMMAND);
        irq_trans->set_data_ptr(reinterpret_cast<unsigned char *>(&cause));
        irq_trans->set_data_length(4);
        irq_trans->set_streaming_width(4);
        irq_trans->set_byte_enable_ptr(nullptr);
        irq_trans->set_dmi_allowed(false);
        irq_trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
        irq_trans->set_address(0);

        while (true) {
            wait(uart_event);
            irq_line->b_transport(*irq_trans, delay);
        }
    }

    void Uart::b_transport(tlm::tlm_generic_payload &trans,
                            sc_core::sc_time &delay) {

        tlm::tlm_command cmd = trans.get_command();
        unsigned char *ptr = trans.get_data_ptr();
        unsigned int len = trans.get_data_length();
        std::uint32_t aux_value = 0;

        delay = sc_core::SC_ZERO_TIME;

        if(event_o.read()) {
            uart_event.notify();
        }

        if (PREADY.read()) {
            PADDR.write(trans.get_address());
            PSEL.write(1);
            PENABLE.write(1);
            if (cmd == tlm::TLM_WRITE_COMMAND) {
                PWRITE.write(1);
                memcpy(&aux_value, ptr, len);
                PWDATA.write(aux_value);
            } else { // TLM_READ_COMMAND
                PWRITE.write(0);
                aux_value = PRDATA.read();
                memcpy(ptr, &aux_value, len);
            }
            trans.set_response_status(tlm::TLM_OK_RESPONSE);
        } else {
            trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
        }
    }
}

2. Changed files
   ├── CMakeLists.txt
   ├── inc
   │   ├── CPU.h
   ├── src
   │   ├── CPU.cpp
   │   ├── Simulator.cpp

• CMakeLists.txt

+++ include_directories(./model/)
+++ include_directories(/usr/local/share/verilator-5.014/share/verilator/include/)
+++ target_link_libraries(RISCV_TLM ${PROJECT_SOURCE_DIR}/model/Vapb_uart_sv.a)

• CPU.h

--- tlm_utils::simple_target_socket<CPU> irq_line_socket;
+++ tlm_utils::simple_target_socket<CPU> irq_line_socket[2];

• CPU.cpp

--- irq_line_socket.register_b_transport(this, &CPU::call_interrupt);
+++ irq_line_socket[0].register_b_transport(this, &CPU::call_interrupt);
+++ irq_line_socket[1].register_b_transport(this, &CPU::call_interrupt);

• Simulator.cpp

--- timer->irq_line.bind(cpu->irq_line_socket);
+++ timer->irq_line.bind(cpu->irq_line_socket[0]);
+++ uart->irq_line.bind(cpu->irq_line_socket[1]);

[Alan-19950616]

I sent an issue to systemc and verilator too.

accellera-official/systemc#57

verilator/verilator#4434

[AmeyaVS]

Did you try to back trace by using a debugger to locate the source location in your code from where this exception is being triggered?

[Alan-19950616]

Yes, I tried debugging with gdb.

riscv_tlm::peripherals::Trace::Trace (this=this@entry=0x55555575acf0, name=...) at /home/nuclei/FastModel/RISC-V-TLM/src/Trace.cpp:92
92	    Trace::Trace(sc_core::sc_module_name const &name) :
(gdb) n
93	            sc_module(name), socket("socket") {
(gdb) 
95	        socket.register_b_transport(this, &Trace::b_transport);
(gdb) 
93	            sc_module(name), socket("socket") {
(gdb) 
95	        socket.register_b_transport(this, &Trace::b_transport);
(gdb) 
93	            sc_module(name), socket("socket") {
(gdb) 
95	        socket.register_b_transport(this, &Trace::b_transport);
(gdb) 
97	        xtermSetup();
(gdb) s
64	    void Trace::xtermSetup() {
(gdb) n
65	        ptMaster = open("/dev/ptmx", O_RDWR);
(gdb) 
67	        if (ptMaster != -1) {
(gdb) 
68	            grantpt(ptMaster);
(gdb) 
70	            unlockpt(ptMaster);
(gdb) 
72	            char *ptSlaveName = ptsname(ptMaster);
(gdb) 
73	            ptSlave = open(ptSlaveName, O_RDWR);    // In and out are the same
(gdb) 
75	            struct termios termInfo{};
(gdb) 
76	            tcgetattr(ptSlave, &termInfo);
(gdb) 
79	            termInfo.c_lflag &= ~ICANON;
(gdb) 
80	            tcsetattr(ptSlave, TCSADRAIN, &termInfo);
(gdb) 
82	            xtermPid = fork();
(gdb) 
[Detaching after fork from child process 4954]
84	            if (xtermPid == 0) {
Warning: (W116) channel doesn't have a default event
In file: /home/nuclei/FastModel/systemc-2.3.4/src/sysc/communication/sc_interface.cpp:54
pure virtual method called
terminate called without an active exception

[AmeyaVS]

Can you try it without calling xtermSetup? With limited source information it will be difficult to root cause it.
If possible can you recreate a minimal setup which has this issue?

[Alan-19950616]

The error message doesn't change after not calling xtermSetup, but I can't find the exact trigger location. I can provide Vapb_uart_sv.a for you to debug.
Vapb_uart_sv.zip

[AmeyaVS]

What are the build/compilation flags being used to build this model? With the static library it will involve additional effort to just replicate the setup.

[Alan-19950616]

Build/compile flags for build this model

SIM_OPTIONS   := -sc --exe --build -j --top-module $(TOP_MODULE) -Wno-fatal
CXX_FLAGS     := -CFLAGS -fPIE