Problem
NucleusRV lacks support for RISC-V Control Status Registers (CSR) and system instructions (ECALL, EBREAK, MRET). This prevents:
- Exception handling and system calls
- Performance monitoring
- Operating system development
- Full RISC-V compliance
🎯 Proposed Solution
Implement complete CSR system including:
Instructions
- CSR Instructions: CSRRW, CSRRS, CSRRC + immediate variants
- System Instructions: ECALL, EBREAK, MRET
CSR Registers
- Machine Info: MHARTID, MISA, MVENDORID, MARCHID, MIMPID
- Trap Setup: MSTATUS, MIE, MTVEC
- Trap Handling: MEPC, MCAUSE, MSCRATCH, MTVAL, MIP
- Performance: MCYCLE, MINSTRET (64-bit counters)
Exception Handling
- Trap entry/exit mechanism
- Privilege mode management (Machine mode)
- Exception cause detection
Implementation
Files to modify:
- Add
CSR.scala and CSRUnit.scala
- Extend
Control.scala for system instruction decode
- Update
Core.scala for pipeline integration
- Add CSR constants to
Constants.scala
Testing:
- Unit tests for CSR operations
- Assembly test programs
- Exception handling validation
Benefits
- ✅ Major step toward RISC-V compliance
- ✅ Enables system software development
- ✅ Adds performance monitoring capabilities
- ✅ Foundation for future OS/interrupt support
🤝 Contribution
I can implement this...
Problem
NucleusRV lacks support for RISC-V Control Status Registers (CSR) and system instructions (ECALL, EBREAK, MRET). This prevents:
🎯 Proposed Solution
Implement complete CSR system including:
Instructions
CSR Registers
Exception Handling
Implementation
Files to modify:
CSR.scalaandCSRUnit.scalaControl.scalafor system instruction decodeCore.scalafor pipeline integrationConstants.scalaTesting:
Benefits
🤝 Contribution
I can implement this...