From 4b913eed7b043d192be5dfa5f84b5fc38ca389eb Mon Sep 17 00:00:00 2001 From: evnoj Date: Thu, 30 Apr 2026 09:19:37 -0600 Subject: [PATCH] bring DAC sample rate closer to 48kHz The DAC is driven by the I2S peripheral. The STM32F72 reference manual describes the formula for the sample rate of the I2S in PCM mode with MCLK enabled on pg. 991. To have 4 channels outputting at the desired 48kHz, our I2S sample frequency must be 48kHz*4=192kHz. To achieve this, we need to set PLLI2SN and PLLI2SR such that a divider can be found that gets the sample rate as close to 192kHz as possible. The best values are N=344 and R=2, which results in an actual sample rate of 191.964kHz, so a per-output sample rate of 47.992kHz --- ll/dac8565.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ll/dac8565.c b/ll/dac8565.c index a8e8cf4a..8fca993d 100644 --- a/ll/dac8565.c +++ b/ll/dac8565.c @@ -180,7 +180,7 @@ void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) // I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR RCC_ExCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S; RCC_ExCLKInitStruct.I2sClockSelection = RCC_I2SCLKSOURCE_PLLI2S; - RCC_ExCLKInitStruct.PLLI2S.PLLI2SN = 384; // mul factor: 50~432 + RCC_ExCLKInitStruct.PLLI2S.PLLI2SN = 344; // mul factor: 50~432 RCC_ExCLKInitStruct.PLLI2S.PLLI2SR = 2; // div factor: 2~7 HAL_RCCEx_PeriphCLKConfig(&RCC_ExCLKInitStruct);