Bug: Top module detection fails if Verilog module contains a parameter block

[swittlich]

There is an issue with the node exporter where a Verilog module is not correctly detected/recognized as the top module if it contains a parameter declaration block before the port list.

When the parser encounters a module with parameterized inputs/outputs or a local parameter block at the module declaration level, the top module exporter seems to skip or misclassify it.

Steps to Reproduce

module my_custom_top #(
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 8
)(
    input wire clk,
    input wire rst,
    input wire [DATA_WIDTH-1:0] data_in,
    output reg [DATA_WIDTH-1:0] data_out
);
endmodule