From cc5809d3673292ef79db623936593f1b649af71c Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Wed, 18 Feb 2026 14:24:52 +0300 Subject: [PATCH 01/17] Edit: gitignore Reason: need to use local dir --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index f0a0ea2c2d2a..740f24c4d692 100644 --- a/.gitignore +++ b/.gitignore @@ -66,3 +66,5 @@ coverage /tools/commit_slider/slider_cache/* /src/plugins/intel_cpu/thirdparty/ComputeLibrary/build/arm_compute_version.embed .github/GITHUB_OUTPUT +/onnx_models +/reports \ No newline at end of file From fe1ad6ac16e31cedf2d43f76c012607001f6dc5a Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Fri, 13 Mar 2026 15:09:23 +0300 Subject: [PATCH 02/17] [CPU] rv64: Add rvv gemm conv --- src/plugins/intel_cpu/thirdparty/onednn | 2 +- src/plugins/intel_cpu/thirdparty/shl | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) create mode 160000 src/plugins/intel_cpu/thirdparty/shl diff --git a/src/plugins/intel_cpu/thirdparty/onednn b/src/plugins/intel_cpu/thirdparty/onednn index 107c977ddc5c..461218e81407 160000 --- a/src/plugins/intel_cpu/thirdparty/onednn +++ b/src/plugins/intel_cpu/thirdparty/onednn @@ -1 +1 @@ -Subproject commit 107c977ddc5cec7131cbb61bca7b65f835d75f01 +Subproject commit 461218e8140747fe84426088ce764ff835a610a8 diff --git a/src/plugins/intel_cpu/thirdparty/shl b/src/plugins/intel_cpu/thirdparty/shl new file mode 160000 index 000000000000..27992eaf41ef --- /dev/null +++ b/src/plugins/intel_cpu/thirdparty/shl @@ -0,0 +1 @@ +Subproject commit 27992eaf41ef967ed228ea8d801b1aa489ea8997 From bc6a5f52d020dbb08810f7b1f71e662368773c28 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Fri, 20 Mar 2026 08:51:41 +0300 Subject: [PATCH 03/17] [CPU][RV64] Edit: convolution_implementations.cpp - add gemm_conv --- .gitignore | 5 ++- .../executors/convolution_implementations.cpp | 40 ++++++++++++++++++- .../riscv64/jit_add_bias_executor.cpp | 0 .../riscv64/jit_add_bias_executor.hpp | 0 src/plugins/intel_cpu/thirdparty/onednn | 2 +- src/plugins/intel_cpu/thirdparty/shl | 1 - 6 files changed, 42 insertions(+), 6 deletions(-) create mode 100644 src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.cpp create mode 100644 src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.hpp delete mode 160000 src/plugins/intel_cpu/thirdparty/shl diff --git a/.gitignore b/.gitignore index 740f24c4d692..5ab032023259 100644 --- a/.gitignore +++ b/.gitignore @@ -66,5 +66,6 @@ coverage /tools/commit_slider/slider_cache/* /src/plugins/intel_cpu/thirdparty/ComputeLibrary/build/arm_compute_version.embed .github/GITHUB_OUTPUT -/onnx_models -/reports \ No newline at end of file +/models +/reports +/jit_riscv_demo diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 8c219f782114..108eac27f156 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -276,8 +276,27 @@ const std::vector>& getImplementations() { AcceptsAnyShape, CreateDnnlDefault{} ) + + + // OV_CPU_INSTANCE_RISCV64( + // "jit_rvv_1x1_convolution_fwd_t", ExecutorType::Dnnl, OperationType::Convolution, + // // supports + // [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { + // VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); + // VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); + // return MatchesMemoryFormatFilter(config.descs, + // LayoutConfig{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}, + // memoryFormatFilter, + // dnnlConvolutionMappingNotation); + // }, + // // createOptimalConfig + // CreateOptimalConfigDefault{{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}}, + // AcceptsAnyShape, + // CreateDnnlDefault{} + // ) + OV_CPU_INSTANCE_RISCV64( - "convolution_dnnl_ref_ncsp", ExecutorType::Dnnl, OperationType::Convolution, + "riscv_gemm_convolution_fwd_t", ExecutorType::Dnnl, OperationType::Convolution, // supports [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); @@ -292,8 +311,25 @@ const std::vector>& getImplementations() { AcceptsAnyShape, CreateDnnlDefault{} ) + + // OV_CPU_INSTANCE_RISCV64( + // "convolution_dnnl_ref_ncsp", ExecutorType::Dnnl, OperationType::Convolution, + // // supports + // [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { + // VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); + // VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); + // return MatchesMemoryFormatFilter(config.descs, + // LayoutConfig{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}, + // memoryFormatFilter, + // dnnlConvolutionMappingNotation); + // }, + // // createOptimalConfig + // CreateOptimalConfigDefault{{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}}, + // AcceptsAnyShape, + // CreateDnnlDefault{} + // ) }; - + std::cout << "Registered " << convolutionImplementations.size() << " convolution implementations." << std::endl; return convolutionImplementations; } // clang-format on diff --git a/src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.cpp b/src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.cpp new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.hpp b/src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.hpp new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/src/plugins/intel_cpu/thirdparty/onednn b/src/plugins/intel_cpu/thirdparty/onednn index 461218e81407..6e5fca86fca1 160000 --- a/src/plugins/intel_cpu/thirdparty/onednn +++ b/src/plugins/intel_cpu/thirdparty/onednn @@ -1 +1 @@ -Subproject commit 461218e8140747fe84426088ce764ff835a610a8 +Subproject commit 6e5fca86fca17ff81097930144e5471b60d1f369 diff --git a/src/plugins/intel_cpu/thirdparty/shl b/src/plugins/intel_cpu/thirdparty/shl deleted file mode 160000 index 27992eaf41ef..000000000000 --- a/src/plugins/intel_cpu/thirdparty/shl +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 27992eaf41ef967ed228ea8d801b1aa489ea8997 From f9edc4f94fca56ea4b7b4bc98215cf896e8b7095 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Mon, 23 Mar 2026 19:31:00 +0000 Subject: [PATCH 04/17] [CPU][RV64] Bugfix: jit_conv_1x1 --- .../executors/convolution_implementations.cpp | 32 +++++++++---------- src/plugins/intel_cpu/thirdparty/onednn | 2 +- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 108eac27f156..a3d4f14803a7 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -278,22 +278,22 @@ const std::vector>& getImplementations() { ) - // OV_CPU_INSTANCE_RISCV64( - // "jit_rvv_1x1_convolution_fwd_t", ExecutorType::Dnnl, OperationType::Convolution, - // // supports - // [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { - // VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); - // VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); - // return MatchesMemoryFormatFilter(config.descs, - // LayoutConfig{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}, - // memoryFormatFilter, - // dnnlConvolutionMappingNotation); - // }, - // // createOptimalConfig - // CreateOptimalConfigDefault{{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}}, - // AcceptsAnyShape, - // CreateDnnlDefault{} - // ) + OV_CPU_INSTANCE_RISCV64( + "jit_rvv_1x1_convolution_fwd_t", ExecutorType::Dnnl, OperationType::Convolution, + // supports + [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { + VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); + VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); + return MatchesMemoryFormatFilter(config.descs, + LayoutConfig{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}, + memoryFormatFilter, + dnnlConvolutionMappingNotation); + }, + // createOptimalConfig + CreateOptimalConfigDefault{{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}}, + AcceptsAnyShape, + CreateDnnlDefault{} + ) OV_CPU_INSTANCE_RISCV64( "riscv_gemm_convolution_fwd_t", ExecutorType::Dnnl, OperationType::Convolution, diff --git a/src/plugins/intel_cpu/thirdparty/onednn b/src/plugins/intel_cpu/thirdparty/onednn index 6e5fca86fca1..231fcc0f7609 160000 --- a/src/plugins/intel_cpu/thirdparty/onednn +++ b/src/plugins/intel_cpu/thirdparty/onednn @@ -1 +1 @@ -Subproject commit 6e5fca86fca17ff81097930144e5471b60d1f369 +Subproject commit 231fcc0f76097c11249e05eb7d3ee1c7c47e96a3 From 2387986dd7fdd5151f885e0a087a18da97eb2dfa Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Wed, 22 Apr 2026 15:50:14 +0000 Subject: [PATCH 05/17] [CPU][RV64] Return ref + Add 1x1 conv --- .gitignore | 5 +++ .../executors/convolution_implementations.cpp | 32 +++++++++---------- src/plugins/intel_cpu/thirdparty/onednn | 2 +- 3 files changed, 22 insertions(+), 17 deletions(-) diff --git a/.gitignore b/.gitignore index 5ab032023259..66b39255b01a 100644 --- a/.gitignore +++ b/.gitignore @@ -66,6 +66,11 @@ coverage /tools/commit_slider/slider_cache/* /src/plugins/intel_cpu/thirdparty/ComputeLibrary/build/arm_compute_version.embed .github/GITHUB_OUTPUT + + /models /reports /jit_riscv_demo +/datasets +/packages +/python_libs diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index a3d4f14803a7..64d21bf128eb 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -312,22 +312,22 @@ const std::vector>& getImplementations() { CreateDnnlDefault{} ) - // OV_CPU_INSTANCE_RISCV64( - // "convolution_dnnl_ref_ncsp", ExecutorType::Dnnl, OperationType::Convolution, - // // supports - // [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { - // VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); - // VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); - // return MatchesMemoryFormatFilter(config.descs, - // LayoutConfig{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}, - // memoryFormatFilter, - // dnnlConvolutionMappingNotation); - // }, - // // createOptimalConfig - // CreateOptimalConfigDefault{{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}}, - // AcceptsAnyShape, - // CreateDnnlDefault{} - // ) + OV_CPU_INSTANCE_RISCV64( + "convolution_dnnl_ref_ncsp", ExecutorType::Dnnl, OperationType::Convolution, + // supports + [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { + VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); + VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); + return MatchesMemoryFormatFilter(config.descs, + LayoutConfig{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}, + memoryFormatFilter, + dnnlConvolutionMappingNotation); + }, + // createOptimalConfig + CreateOptimalConfigDefault{{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}}, + AcceptsAnyShape, + CreateDnnlDefault{} + ) }; std::cout << "Registered " << convolutionImplementations.size() << " convolution implementations." << std::endl; return convolutionImplementations; diff --git a/src/plugins/intel_cpu/thirdparty/onednn b/src/plugins/intel_cpu/thirdparty/onednn index 231fcc0f7609..3f044236329a 160000 --- a/src/plugins/intel_cpu/thirdparty/onednn +++ b/src/plugins/intel_cpu/thirdparty/onednn @@ -1 +1 @@ -Subproject commit 231fcc0f76097c11249e05eb7d3ee1c7c47e96a3 +Subproject commit 3f044236329a3f848f25e707ad2c09319cd964b9 From 0aaa56c286e885415c33c7ef8688e4b6ec15219e Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Sun, 26 Apr 2026 14:43:46 +0000 Subject: [PATCH 06/17] [CPU][RV64] clean whitespace changes & rename impl at convolution_implementations.cpp --- .../executors/convolution_implementations.cpp | 14 +++++++------- .../executors/riscv64/jit_add_bias_executor.cpp | 0 .../executors/riscv64/jit_add_bias_executor.hpp | 0 src/plugins/intel_cpu/thirdparty/onednn | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) delete mode 100644 src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.cpp delete mode 100644 src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.hpp diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 64d21bf128eb..5701e2a90401 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -279,11 +279,11 @@ const std::vector>& getImplementations() { OV_CPU_INSTANCE_RISCV64( - "jit_rvv_1x1_convolution_fwd_t", ExecutorType::Dnnl, OperationType::Convolution, + "convolution_dnnl_ncsp_ncsp", ExecutorType::Dnnl, OperationType::Convolution, // supports [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); - VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); + VERIFY(!hasPostOp(config.attrs.postOps), UNSUPPORTED_POST_OPS); return MatchesMemoryFormatFilter(config.descs, LayoutConfig{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}, memoryFormatFilter, @@ -296,22 +296,22 @@ const std::vector>& getImplementations() { ) OV_CPU_INSTANCE_RISCV64( - "riscv_gemm_convolution_fwd_t", ExecutorType::Dnnl, OperationType::Convolution, + "convolution_dnnl_nspc_nspc", ExecutorType::Dnnl, OperationType::Convolution, // supports [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); return MatchesMemoryFormatFilter(config.descs, - LayoutConfig{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}, + LayoutConfig{LayoutType::nspc, LayoutType::ncsp, LayoutType::nspc, LayoutType::nspc}, memoryFormatFilter, dnnlConvolutionMappingNotation); }, // createOptimalConfig - CreateOptimalConfigDefault{{LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp, LayoutType::ncsp}}, + CreateOptimalConfigDefault{{LayoutType::nspc, LayoutType::ncsp, LayoutType::nspc, LayoutType::nspc}}, AcceptsAnyShape, CreateDnnlDefault{} ) - + OV_CPU_INSTANCE_RISCV64( "convolution_dnnl_ref_ncsp", ExecutorType::Dnnl, OperationType::Convolution, // supports @@ -329,7 +329,7 @@ const std::vector>& getImplementations() { CreateDnnlDefault{} ) }; - std::cout << "Registered " << convolutionImplementations.size() << " convolution implementations." << std::endl; + return convolutionImplementations; } // clang-format on diff --git a/src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.cpp b/src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.cpp deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.hpp b/src/plugins/intel_cpu/src/nodes/executors/riscv64/jit_add_bias_executor.hpp deleted file mode 100644 index e69de29bb2d1..000000000000 diff --git a/src/plugins/intel_cpu/thirdparty/onednn b/src/plugins/intel_cpu/thirdparty/onednn index 3f044236329a..a551c01f76e8 160000 --- a/src/plugins/intel_cpu/thirdparty/onednn +++ b/src/plugins/intel_cpu/thirdparty/onednn @@ -1 +1 @@ -Subproject commit 3f044236329a3f848f25e707ad2c09319cd964b9 +Subproject commit a551c01f76e8d2c2d8a254805ca9246f8ed0bd1b From 3d4c8ef9d5ff4d3f70c7f9ebffd239a2cf60df40 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:23:56 +0000 Subject: [PATCH 07/17] [CPU][RV64] Return ref and edit choose impl --- .../executors/convolution_implementations.cpp | 16 ---------------- .../dnnl/dnnl_convolution_primitive.cpp | 2 ++ .../intel_cpu/src/onednn/iml_type_mapper.cpp | 6 ++++++ src/plugins/intel_cpu/thirdparty/onednn | 2 +- 4 files changed, 9 insertions(+), 17 deletions(-) diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 5701e2a90401..213b8cd40819 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -295,22 +295,6 @@ const std::vector>& getImplementations() { CreateDnnlDefault{} ) - OV_CPU_INSTANCE_RISCV64( - "convolution_dnnl_nspc_nspc", ExecutorType::Dnnl, OperationType::Convolution, - // supports - [](const ConvConfig& config, const MemoryFormatFilter& memoryFormatFilter) -> bool { - VERIFY(!isQuantized(config), UNSUPPORTED_SRC_PRECISIONS); - VERIFY(config.attrs.postOps.empty(), UNSUPPORTED_POST_OPS); - return MatchesMemoryFormatFilter(config.descs, - LayoutConfig{LayoutType::nspc, LayoutType::ncsp, LayoutType::nspc, LayoutType::nspc}, - memoryFormatFilter, - dnnlConvolutionMappingNotation); - }, - // createOptimalConfig - CreateOptimalConfigDefault{{LayoutType::nspc, LayoutType::ncsp, LayoutType::nspc, LayoutType::nspc}}, - AcceptsAnyShape, - CreateDnnlDefault{} - ) OV_CPU_INSTANCE_RISCV64( "convolution_dnnl_ref_ncsp", ExecutorType::Dnnl, OperationType::Convolution, diff --git a/src/plugins/intel_cpu/src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp b/src/plugins/intel_cpu/src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp index a990b2c7f23b..e42f7108a3fe 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp @@ -12,8 +12,10 @@ #include #include #include +#include #include #include +#include #include #include #include diff --git a/src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp b/src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp index f17553e506b7..74cb272447e7 100644 --- a/src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp +++ b/src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp @@ -80,6 +80,12 @@ impl_desc_type parse_impl_name(std::string impl_desc_name) { if ((res & jit) && (res & any)) { res = static_cast(res & ~any); } + // Map gemm:ref to gemm_any so it can match existing priority lists. +#if defined(OPENVINO_ARCH_RISCV64) || defined(DNNL_RV64) || defined(RISCV64) || defined(__riscv) + if ((res & impl_desc_type::gemm) && (res & impl_desc_type::ref)) { + res = impl_desc_type::gemm_any; + } +#endif return res; } diff --git a/src/plugins/intel_cpu/thirdparty/onednn b/src/plugins/intel_cpu/thirdparty/onednn index a551c01f76e8..7c82da94cd9c 160000 --- a/src/plugins/intel_cpu/thirdparty/onednn +++ b/src/plugins/intel_cpu/thirdparty/onednn @@ -1 +1 @@ -Subproject commit a551c01f76e8d2c2d8a254805ca9246f8ed0bd1b +Subproject commit 7c82da94cd9c864ff4285ba09282ce3e80e5e4b0 From db6022a8f06c211dce924d5ce12b6bfcb678e035 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:51:34 +0000 Subject: [PATCH 08/17] [CPU][RV64] Remove gemm ref switch --- src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp | 6 ------ src/plugins/intel_cpu/thirdparty/onednn | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp b/src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp index 74cb272447e7..f17553e506b7 100644 --- a/src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp +++ b/src/plugins/intel_cpu/src/onednn/iml_type_mapper.cpp @@ -80,12 +80,6 @@ impl_desc_type parse_impl_name(std::string impl_desc_name) { if ((res & jit) && (res & any)) { res = static_cast(res & ~any); } - // Map gemm:ref to gemm_any so it can match existing priority lists. -#if defined(OPENVINO_ARCH_RISCV64) || defined(DNNL_RV64) || defined(RISCV64) || defined(__riscv) - if ((res & impl_desc_type::gemm) && (res & impl_desc_type::ref)) { - res = impl_desc_type::gemm_any; - } -#endif return res; } diff --git a/src/plugins/intel_cpu/thirdparty/onednn b/src/plugins/intel_cpu/thirdparty/onednn index 7c82da94cd9c..6791f0ea3e78 160000 --- a/src/plugins/intel_cpu/thirdparty/onednn +++ b/src/plugins/intel_cpu/thirdparty/onednn @@ -1 +1 @@ -Subproject commit 7c82da94cd9c864ff4285ba09282ce3e80e5e4b0 +Subproject commit 6791f0ea3e785912e79a31546133afaddfa018f7 From 10393319eaf3bac487874619d8c98e6cbec5e15f Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:55:12 +0000 Subject: [PATCH 09/17] [CPU][RV64] Clean up dnnl --- .../src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/plugins/intel_cpu/src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp b/src/plugins/intel_cpu/src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp index e42f7108a3fe..a990b2c7f23b 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/dnnl/dnnl_convolution_primitive.cpp @@ -12,10 +12,8 @@ #include #include #include -#include #include #include -#include #include #include #include From dc2437572233e58025c5fad14169f025c924fea3 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:56:41 +0000 Subject: [PATCH 10/17] [CPU][RV64] Clean up conv_impl --- .../src/nodes/executors/convolution_implementations.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 213b8cd40819..29880b3c1932 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -313,7 +313,6 @@ const std::vector>& getImplementations() { CreateDnnlDefault{} ) }; - return convolutionImplementations; } // clang-format on From beb7797b0672aa37cc2d54d4de7a25c2b25efe62 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:57:16 +0000 Subject: [PATCH 11/17] [CPU][RV64] Clean up conv_impl --- .../src/nodes/executors/convolution_implementations.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 29880b3c1932..213b8cd40819 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -313,6 +313,7 @@ const std::vector>& getImplementations() { CreateDnnlDefault{} ) }; + return convolutionImplementations; } // clang-format on From c66f745fa4b01d233de0e864cb5dcd0638120491 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:57:44 +0000 Subject: [PATCH 12/17] [CPU][RV64] Clean up conv_impl --- .../src/nodes/executors/convolution_implementations.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 213b8cd40819..9344ea119ead 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -313,7 +313,7 @@ const std::vector>& getImplementations() { CreateDnnlDefault{} ) }; - + return convolutionImplementations; } // clang-format on From 8c47a8997850858ad399fbf994b7e7bf3d1f71cc Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:58:10 +0000 Subject: [PATCH 13/17] [CPU][RV64] Clean up conv_impl --- .../src/nodes/executors/convolution_implementations.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 9344ea119ead..585fd1800978 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -313,7 +313,7 @@ const std::vector>& getImplementations() { CreateDnnlDefault{} ) }; - + return convolutionImplementations; } // clang-format on From d9c0a6ce26011afe7f399dd960aec0003b478f1d Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:58:57 +0000 Subject: [PATCH 14/17] [CPU][RV64] Clean up conv_impl --- .../src/nodes/executors/convolution_implementations.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 585fd1800978..1f79ecf3dd70 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -276,8 +276,6 @@ const std::vector>& getImplementations() { AcceptsAnyShape, CreateDnnlDefault{} ) - - OV_CPU_INSTANCE_RISCV64( "convolution_dnnl_ncsp_ncsp", ExecutorType::Dnnl, OperationType::Convolution, // supports From 5738884b5f32e176d99325716c59fb3abd26af73 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 28 Apr 2026 21:59:41 +0000 Subject: [PATCH 15/17] [CPU][RV64] Clean up conv_impl --- .../src/nodes/executors/convolution_implementations.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp index 1f79ecf3dd70..3dd212464163 100644 --- a/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp +++ b/src/plugins/intel_cpu/src/nodes/executors/convolution_implementations.cpp @@ -292,8 +292,6 @@ const std::vector>& getImplementations() { AcceptsAnyShape, CreateDnnlDefault{} ) - - OV_CPU_INSTANCE_RISCV64( "convolution_dnnl_ref_ncsp", ExecutorType::Dnnl, OperationType::Convolution, // supports From 19e2fc72eb41892f1da96244fcd6a6af659f109c Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Sat, 9 May 2026 10:53:06 +0000 Subject: [PATCH 16/17] Merge Master --- src/bindings/python/thirdparty/pybind11 | 2 +- src/plugins/intel_cpu/thirdparty/ComputeLibrary | 2 +- src/plugins/intel_cpu/thirdparty/onednn | 2 +- src/plugins/intel_gpu/thirdparty/onednn_gpu | 2 +- src/plugins/intel_npu/thirdparty/level-zero-ext | 2 +- thirdparty/gtest/gtest | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/bindings/python/thirdparty/pybind11 b/src/bindings/python/thirdparty/pybind11 index 45fab4087eaa..f5fbe867d2d2 160000 --- a/src/bindings/python/thirdparty/pybind11 +++ b/src/bindings/python/thirdparty/pybind11 @@ -1 +1 @@ -Subproject commit 45fab4087eaaff234227a10cf7845e8b07f28a98 +Subproject commit f5fbe867d2d26e4a0a9177a51f6e568868ad3dc8 diff --git a/src/plugins/intel_cpu/thirdparty/ComputeLibrary b/src/plugins/intel_cpu/thirdparty/ComputeLibrary index c245aa08b328..cffb5d67ad74 160000 --- a/src/plugins/intel_cpu/thirdparty/ComputeLibrary +++ b/src/plugins/intel_cpu/thirdparty/ComputeLibrary @@ -1 +1 @@ -Subproject commit c245aa08b328fe7ef1d356f40b89ebc587524dae +Subproject commit cffb5d67ad74e6ed924c708d4981ba15b644bc05 diff --git a/src/plugins/intel_cpu/thirdparty/onednn b/src/plugins/intel_cpu/thirdparty/onednn index 6791f0ea3e78..9faf455d7aaf 160000 --- a/src/plugins/intel_cpu/thirdparty/onednn +++ b/src/plugins/intel_cpu/thirdparty/onednn @@ -1 +1 @@ -Subproject commit 6791f0ea3e785912e79a31546133afaddfa018f7 +Subproject commit 9faf455d7aaf942909857da2d9c9895fb9c09722 diff --git a/src/plugins/intel_gpu/thirdparty/onednn_gpu b/src/plugins/intel_gpu/thirdparty/onednn_gpu index 20db47e2d3c4..7e6e4df24886 160000 --- a/src/plugins/intel_gpu/thirdparty/onednn_gpu +++ b/src/plugins/intel_gpu/thirdparty/onednn_gpu @@ -1 +1 @@ -Subproject commit 20db47e2d3c4df1b66e93bed2e97d30da175512d +Subproject commit 7e6e4df2488601e3694a2c83dce05ab435c5e35c diff --git a/src/plugins/intel_npu/thirdparty/level-zero-ext b/src/plugins/intel_npu/thirdparty/level-zero-ext index f9ad3bf89c24..42768cc73e74 160000 --- a/src/plugins/intel_npu/thirdparty/level-zero-ext +++ b/src/plugins/intel_npu/thirdparty/level-zero-ext @@ -1 +1 @@ -Subproject commit f9ad3bf89c2418d714aef2e6b96a5aafb12a1971 +Subproject commit 42768cc73e74f6d371bd9dd51b1860b07774e7ec diff --git a/thirdparty/gtest/gtest b/thirdparty/gtest/gtest index 03e2ed1291b4..99760ac17764 160000 --- a/thirdparty/gtest/gtest +++ b/thirdparty/gtest/gtest @@ -1 +1 @@ -Subproject commit 03e2ed1291b40062be24df240f597d995aaaa962 +Subproject commit 99760ac1776430f3df65947992bf4e8ebc0d7660 From 66678bb8af913210ef4f4802c5bc7a66a4f72355 Mon Sep 17 00:00:00 2001 From: StrelkovKM Date: Tue, 26 May 2026 14:24:21 +0000 Subject: [PATCH 17/17] [CPU][RV64] clear /.gitignore --- .gitignore | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/.gitignore b/.gitignore index 9b3c598f8674..6b6ad679ce98 100644 --- a/.gitignore +++ b/.gitignore @@ -68,12 +68,4 @@ coverage /tools/commit_slider/*.json /tools/commit_slider/slider_cache/* /src/plugins/intel_cpu/thirdparty/ComputeLibrary/build/arm_compute_version.embed -.github/GITHUB_OUTPUT - - -/models -/reports -/jit_riscv_demo -/datasets -/packages -/python_libs +.github/GITHUB_OUTPUT \ No newline at end of file