Replies: 2 comments
|
You can use the Verilog plugin. This is the sample generated Verilog code. |
0 replies
|
Hi taichi-ishitani |
0 replies
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Uh oh!
There was an error while loading. Please reload this page.
For example, original axi_lite interface of the top is as below,
rggen_axi4lite_if.slave axi4lite_if,
I would like to know if any option to turn off interface instance and just use axi_lite input/output ports?
input awvalid,
output awready,
input awid,
input awaddr,
input awprot,
input wvalid,
output wready,
input wdata,
input wstrb,
output bvalid,
input bready,
output bid,
output bresp,
input arvalid,
All reactions