How to initialize non sequential bit field register block

[alejandro-castro-ortegon]

Hello,

I have a register with size specified as:

register_blocks:
  - name: my_regs 
    comment: "ABC"
    byte_size: 64
    registers:
    - name: non_seq_reg
      comment: "reg"
      size: [8, step: 4]
      offset_address: 0x00
      bit_fields:
      - { name: non_zero_data,    bit_assignment: { lsb:   0, width: 32 }, type: rw, initial_value: 0x0, comment: "My data" }

Is it possible to assign an initial value to each of the registers?, something like: initial_value: [0x1, 0x2, 0x3, 0x4, 0x1, 0x2, 0x3, 0x4]

Thanks!

[ah-mah]

Hello, Could something like this work for you? initial_value: 0x12341234 BR.

…

On Fri, 31 Jan 2025, 18:51 alejandro-castro-ortegon, < ***@***.***> wrote: Hello, I have a register with size specified as: register_blocks: - name: my_regs comment: "ABC" byte_size: 64 registers: - name: non_seq_reg comment: "reg" size: [8, step: 4] offset_address: 0x00 bit_fields: - { name: non_zero_data, bit_assignment: { lsb: 0, width: 32 }, type: rw, initial_value: 0x0, comment: "My data" } Is it possible to assign an initial value to each of the registers?, something like: initial_value: [0x1, 0x2, 0x3, 0x4, 0x1, 0x2, 0x3, 0x4] Thanks! — Reply to this email directly, view it on GitHub <#240>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AOSD6JMQXWBLEDDC4XGUSYD2NOSYFAVCNFSM6AAAAABWH7RGZWVHI2DSMVQWIX3LMV43ERDJONRXK43TNFXW4OZXHA4TQMBZGQ> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[alejandro-castro-ortegon]

@ah-mah thanks for your answer but this approach will not work if I need to assign an initial value to every bit. As an example, I can't do [0x1111111122222222333333334444444411111111222222223333333344444444]. This is why it would be nice to have a mechanism to to do [0x11111111, 0x22222222, 0x333333333, 0x44444444, 0x11111111, 0x22222222, 0x333333333, 0x44444444].

[taichi-ishitani]

Hi @alejandro-castro-ortegon ,

Is it possible to assign an initial value to each of the registers?,

Currently, such initial value is not supported.
I'd like to you open a feature request if you want it.
https://github.com/rggen/rggen/issues/new?template=feature_request.md

[alejandro-castro-ortegon]

Hello!

Yes, please! It would be nice to have, that way we'll be able to assign a value to every bit of each register. I'll fil the request in a moment.

Thanks!

[taichi-ishitani]

Thanks for opening the issue.

BTW, such initial value for sequential bit field is supported.
You can write your specificatoin like below if you don't need to generate C header files.

# my_regs.yaml
register_blocks:
  - name: my_regs 
    comment: "ABC"
    byte_size: 64
    registers:
    - name: non_seq_reg
      comment: "reg"
      offset_address: 0x00
      bit_fields:
      - <<:
        - { name: non_zero_data, bit_assignment: { lsb: 0, width: 32, sequence_size: 8 }, type: rw }
        - { initial_value: [0x1, 0x2, 0x3, 0x4, 0x1, 0x2, 0x3, 0x4] }
        - { comment: "My data" }

By default, registers of which width is over 64 bits are not allowed.
You need to set the enable_wide_register configuration parameter to true.

# config.yaml
address_width: 16
bus_width: 32
enable_wide_register: true // set

Execute rggen command with --enable sv_rtl switch. This switch is to tell RgGen to generate SV RTL files only.

$ rggen -c config.yaml my_regs.yaml

This is the generated SV RTL.

`ifndef rggen_connect_bit_field_if
  `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
  assign  FIF.valid                 = RIF.valid; \
  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
`endif
`ifndef rggen_tie_off_unused_signals
  `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
  if (1) begin : __g_tie_off \
    genvar  __i; \
    for (__i = 0;__i < WIDTH;++__i) begin : g \
      if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \
        assign  RIF.read_data[__i]  = 1'b0; \
        assign  RIF.value[__i]      = 1'b0; \
      end \
    end \
  end
`endif
module my_regs
  import rggen_rtl_pkg::*;
#(
  parameter int ADDRESS_WIDTH = 6,
  parameter bit PRE_DECODE = 0,
  parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0,
  parameter bit ERROR_STATUS = 0,
  parameter bit [31:0] DEFAULT_READ_DATA = '0,
  parameter bit INSERT_SLICER = 0
)(
  input logic i_clk,
  input logic i_rst_n,
  rggen_apb_if.slave apb_if,
  output logic [7:0][31:0] o_non_seq_reg_non_zero_data
);
  rggen_register_if #(6, 32, 256) register_if[1]();
  rggen_apb_adapter #(
    .ADDRESS_WIDTH        (ADDRESS_WIDTH),
    .LOCAL_ADDRESS_WIDTH  (6),
    .BUS_WIDTH            (32),
    .REGISTERS            (1),
    .PRE_DECODE           (PRE_DECODE),
    .BASE_ADDRESS         (BASE_ADDRESS),
    .BYTE_SIZE            (64),
    .ERROR_STATUS         (ERROR_STATUS),
    .DEFAULT_READ_DATA    (DEFAULT_READ_DATA),
    .INSERT_SLICER        (INSERT_SLICER)
  ) u_adapter (
    .i_clk        (i_clk),
    .i_rst_n      (i_rst_n),
    .apb_if       (apb_if),
    .register_if  (register_if)
  );
  generate if (1) begin : g_non_seq_reg
    rggen_bit_field_if #(256) bit_field_if();
    `rggen_tie_off_unused_signals(256, 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff, bit_field_if)
    rggen_default_register #(
      .READABLE       (1),
      .WRITABLE       (1),
      .ADDRESS_WIDTH  (6),
      .OFFSET_ADDRESS (6'h00),
      .BUS_WIDTH      (32),
      .DATA_WIDTH     (256),
      .VALUE_WIDTH    (256)
    ) u_register (
      .i_clk        (i_clk),
      .i_rst_n      (i_rst_n),
      .register_if  (register_if[0]),
      .bit_field_if (bit_field_if)
    );
    if (1) begin : g_non_zero_data
      genvar i;
      for (i = 0;i < 8;++i) begin : g
        localparam bit [31:0] INITIAL_VALUE[8] = '{32'h00000001, 32'h00000002, 32'h00000003, 32'h00000004, 32'h00000001, 32'h00000002, 32'h00000003, 32'h00000004};
        rggen_bit_field_if #(32) bit_field_sub_if();
        `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0+32*i, 32)
        rggen_bit_field #(
          .WIDTH          (32),
          .INITIAL_VALUE  (INITIAL_VALUE[i]),
          .SW_WRITE_ONCE  (0),
          .TRIGGER        (0)
        ) u_bit_field (
          .i_clk              (i_clk),
          .i_rst_n            (i_rst_n),
          .bit_field_if       (bit_field_sub_if),
          .o_write_trigger    (),
          .o_read_trigger     (),
          .i_sw_write_enable  ('1),
          .i_hw_write_enable  ('0),
          .i_hw_write_data    ('0),
          .i_hw_set           ('0),
          .i_hw_clear         ('0),
          .i_value            ('0),
          .i_mask             ('1),
          .o_value            (o_non_seq_reg_non_zero_data[i]),
          .o_value_unmasked   ()
        );
      end
    end
  end endgenerate
endmodule

[taichi-ishitani]

Hi @alejandro-castro-ortegon

I've released RgGen v0.35.0. This release includes the feature which you requested.
You can specify initial values to each bit fields in an array register like below.

register_blocks:
  - name: my_regs
    comment: "ABC"
    byte_size: 64
    registers:
    - name: non_seq_reg
      comment: "reg"
      offset_address: 0x00
      size: [8]
      bit_fields:
      - <<:
        - { name: non_zero_data, bit_assignment: { lsb: 0, width: 32 }, type: rw }
        - { initial_value: [0x1, 0x2, 0x3, 0x4, 0x1, 0x2, 0x3, 0x4] }
        - { comment: "My data" }

Following SV RTL is generated from the above register map.

`ifndef rggen_connect_bit_field_if
  `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
  assign  FIF.valid                 = RIF.valid; \
  assign  FIF.read_mask             = RIF.read_mask[LSB+:WIDTH]; \
  assign  FIF.write_mask            = RIF.write_mask[LSB+:WIDTH]; \
  assign  FIF.write_data            = RIF.write_data[LSB+:WIDTH]; \
  assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
  assign  RIF.value[LSB+:WIDTH]     = FIF.value;
`endif
`ifndef rggen_tie_off_unused_signals
  `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
  if (1) begin : __g_tie_off \
    genvar  __i; \
    for (__i = 0;__i < WIDTH;++__i) begin : g \
      if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \
        assign  RIF.read_data[__i]  = 1'b0; \
        assign  RIF.value[__i]      = 1'b0; \
      end \
    end \
  end
`endif
module my_regs
  import rggen_rtl_pkg::*;
#(
  parameter int ADDRESS_WIDTH = 6,
  parameter bit PRE_DECODE = 0,
  parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0,
  parameter bit ERROR_STATUS = 0,
  parameter bit [31:0] DEFAULT_READ_DATA = '0,
  parameter bit INSERT_SLICER = 0
)(
  input logic i_clk,
  input logic i_rst_n,
  rggen_apb_if.slave apb_if,
  output logic [7:0][31:0] o_non_seq_reg_non_zero_data
);
  rggen_register_if #(6, 32, 32) register_if[8]();
  rggen_apb_adapter #(
    .ADDRESS_WIDTH        (ADDRESS_WIDTH),
    .LOCAL_ADDRESS_WIDTH  (6),
    .BUS_WIDTH            (32),
    .REGISTERS            (8),
    .PRE_DECODE           (PRE_DECODE),
    .BASE_ADDRESS         (BASE_ADDRESS),
    .BYTE_SIZE            (64),
    .ERROR_STATUS         (ERROR_STATUS),
    .DEFAULT_READ_DATA    (DEFAULT_READ_DATA),
    .INSERT_SLICER        (INSERT_SLICER)
  ) u_adapter (
    .i_clk        (i_clk),
    .i_rst_n      (i_rst_n),
    .apb_if       (apb_if),
    .register_if  (register_if)
  );
  generate if (1) begin : g_non_seq_reg
    genvar i;
    for (i = 0;i < 8;++i) begin : g
      rggen_bit_field_if #(32) bit_field_if();
      `rggen_tie_off_unused_signals(32, 32'hffffffff, bit_field_if)
      rggen_default_register #(
        .READABLE       (1),
        .WRITABLE       (1),
        .ADDRESS_WIDTH  (6),
        .OFFSET_ADDRESS (6'(4*i)),
        .BUS_WIDTH      (32),
        .DATA_WIDTH     (32),
        .VALUE_WIDTH    (32)
      ) u_register (
        .i_clk        (i_clk),
        .i_rst_n      (i_rst_n),
        .register_if  (register_if[i]),
        .bit_field_if (bit_field_if)
      );
      if (1) begin : g_non_zero_data
        localparam bit [7:0][31:0] INITIAL_VALUE = {32'h00000004, 32'h00000003, 32'h00000002, 32'h00000001, 32'h00000004, 32'h00000003, 32'h00000002, 32'h00000001};
        rggen_bit_field_if #(32) bit_field_sub_if();
        `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 32)
        rggen_bit_field #(
          .WIDTH          (32),
          .INITIAL_VALUE  (INITIAL_VALUE[i]),
          .SW_WRITE_ONCE  (0),
          .TRIGGER        (0)
        ) u_bit_field (
          .i_clk              (i_clk),
          .i_rst_n            (i_rst_n),
          .bit_field_if       (bit_field_sub_if),
          .o_write_trigger    (),
          .o_read_trigger     (),
          .i_sw_write_enable  ('1),
          .i_hw_write_enable  ('0),
          .i_hw_write_data    ('0),
          .i_hw_set           ('0),
          .i_hw_clear         ('0),
          .i_value            ('0),
          .i_mask             ('1),
          .o_value            (o_non_seq_reg_non_zero_data[i]),
          .o_value_unmasked   ()
        );
      end
    end
  end endgenerate
endmodule

[alejandro-castro-ortegon]

Thanks @taichi-ishitani !

[taichi-ishitani]

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