From 487c3e9fe7f21ec169bd6c149f309ca34af14113 Mon Sep 17 00:00:00 2001
From: zxq5 <80643031+zxq5-dev@users.noreply.github.com>
Date: Mon, 16 Jun 2025 20:20:14 +0100
Subject: [PATCH 1/2] changed to_ascii_uppercase() to to_ascii_lowercase()

changed from upper case to lowercase to fix a bug where syntax is not highlighted correctly. will also need to change special vals to lowercase in another file
---
 src/syntax/mod.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/syntax/mod.rs b/src/syntax/mod.rs
index 88ac5cc..c987471 100644
--- a/src/syntax/mod.rs
+++ b/src/syntax/mod.rs
@@ -174,21 +174,21 @@ impl Syntax {
         if self.case_sensitive {
             self.keywords.contains(&word)
         } else {
-            self.keywords.contains(word.to_ascii_uppercase().as_str())
+            self.keywords.contains(word.to_ascii_lowercase().as_str())
         }
     }
     pub fn is_type(&self, word: &str) -> bool {
         if self.case_sensitive {
             self.types.contains(&word)
         } else {
-            self.types.contains(word.to_ascii_uppercase().as_str())
+            self.types.contains(word.to_ascii_lowercase().as_str())
         }
     }
     pub fn is_special(&self, word: &str) -> bool {
         if self.case_sensitive {
             self.special.contains(&word)
         } else {
-            self.special.contains(word.to_ascii_uppercase().as_str())
+            self.special.contains(word.to_ascii_lowercase().as_str())
         }
     }
 }

From 5eb313e38504410ce0a6b27231cda28842f542fe Mon Sep 17 00:00:00 2001
From: zxq5 <80643031+zxq5-dev@users.noreply.github.com>
Date: Mon, 16 Jun 2025 20:21:12 +0100
Subject: [PATCH 2/2] Update asm.rs

lowercased register names
---
 src/syntax/asm.rs | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/syntax/asm.rs b/src/syntax/asm.rs
index f772886..9bd240c 100644
--- a/src/syntax/asm.rs
+++ b/src/syntax/asm.rs
@@ -1160,21 +1160,21 @@ impl Syntax {
             ]),
             types: BTreeSet::from(["ptr", "byte", "word", "dword", "qword"]),
             special: BTreeSet::from([
-                "RAX", "RBX", "RCX", "RDX", "RSI", "RDI", "RBP", "RSP", "R8", "R9", "R10", "R11",
-                "R12", "R13", "R14", "R15", // 64-bit registers
-                "EAX", "EBX", "ECX", "EDX", "ESI", "EDI", "EBP", "ESP", "R8D", "R9D", "R10D",
-                "R11D", "R12D", "R13D", "R14D", "R15D", // 32-bit registers
-                "AX", "BX", "CX", "DX", "SI", "DI", "BP", "SP", "R8W", "R9W", "R10W", "R11W",
-                "R12W", "R13W", "R14W", "R15W", // 16-bit registers
-                "AH", "BH", "CH", "DH", "AL", "BL", "CL", "DL", "SIL", "DIL", "BPL", "SPL", "R8B",
-                "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B",
+                "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", "r8", "r9", "r10", "r11",
+                "r12", "r13", "r14", "r15", // 64-bit registers
+                "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", "r8d", "r9d", "r10d",
+                "r11d", "r12d", "r13d", "r14d", "r15d", // 32-bit registers
+                "ax", "bx", "cx", "dx", "si", "di", "bp", "sp", "r8w", "r9w", "r10w", "r11w",
+                "r12w", "r13w", "r14w", "r15w", // 16-bit registers
+                "ah", "bh", "ch", "dh", "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", "r8b",
+                "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b",
                 // 8-bit registers
-                "XMM0", "XMM1", "XMM2", "XMM3", "XMM4", "XMM5", "XMM6", "XMM7", "XMM8", "XMM9",
-                "XMM10", "XMM11", "XMM12", "XMM13", "XMM14", "XMM15", // XMM
-                "YMM0", "YMM1", "YMM2", "YMM3", "YMM4", "YMM5", "YMM6", "YMM7", "YMM8", "YMM9",
-                "YMM10", "YMM11", "YMM12", "YMM13", "YMM14", "YMM15", // YMM
-                "ZMM0", "ZMM1", "ZMM2", "ZMM3", "ZMM4", "ZMM5", "ZMM6", "ZMM7", "ZMM8", "ZMM9",
-                "ZMM10", "ZMM11", "ZMM12", "ZMM13", "ZMM14", "ZMM15",
+                "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9",
+                "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", // XMM
+                "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
+                "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", // YMM
+                "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
+                "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15",
                 // ZMM
             ]),
         }