From b299ced705a3d3bbf8792cec7aebd6ead6f79f38 Mon Sep 17 00:00:00 2001
From: petitstrawberry <petitstrawberry.dev@gmail.com>
Date: Sat, 28 Feb 2026 07:41:14 +0000
Subject: [PATCH] change: update function signatures to return Result for error
 handling

---
 README.md            | 10 +++++-----
 src/lib.rs           |  2 +-
 src/riscv64/tests.rs | 24 ++++++++++++------------
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/README.md b/README.md
index 294c2ca..ba31f91 100644
--- a/README.md
+++ b/README.md
@@ -156,16 +156,16 @@ use jit_assembler::riscv64_asm;
 use jit_assembler::common::BuildError;
 
 // Simple function generator with macro
-fn generate_add_function(a: i16, b: i16) -> Vec<u8> {
+fn generate_add_function(a: i16, b: i16) -> Result<Vec<u8>, BuildError> {
     let instructions = riscv64_asm! {
         addi(reg::A0, reg::ZERO, a);       // Load first operand into a0
         addi(reg::A1, reg::ZERO, b);       // Load second operand into a1
         add(reg::A0, reg::A0, reg::A1);    // Add them, result in a0
         ret();                             // Return
-    };
+    }?;
     
     // Convert to bytes for execution
-    instructions.to_bytes()
+    Ok(instructions.to_bytes())
 }
 
 // Builder pattern for complex logic
@@ -190,11 +190,11 @@ use jit_assembler::common::{InstructionBuilder, BuildError};
 use jit_assembler::aarch64_asm;
 
 // Macro style (concise and assembly-like)
-fn generate_aarch64_add_function_macro() -> Vec<u8> {
+fn generate_aarch64_add_function_macro() -> Result<Vec<u8>, BuildError> {
     let instructions = aarch64_asm! {
         add(reg::X0, reg::X0, reg::X1);  // Add first two arguments (X0 + X1 -> X0)
         ret();                           // Return
-    };
+    }?;
     instructions
 }
 
diff --git a/src/lib.rs b/src/lib.rs
index 9cbaf46..1df5fc8 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -164,6 +164,6 @@ macro_rules! jit_asm_generic {
         $(
             builder.$method($($args),*);
         )*
-        builder.instructions().unwrap().to_vec()
+        builder.instructions().map(|c| c.to_vec())
     }};
 }
diff --git a/src/riscv64/tests.rs b/src/riscv64/tests.rs
index 18ca4c7..e5bbd3b 100644
--- a/src/riscv64/tests.rs
+++ b/src/riscv64/tests.rs
@@ -256,7 +256,8 @@ fn test_csr_with_macro() {
         csrrwi(reg::A1, csr::SEPC, 0x10);     // Write supervisor exception PC
         csrrsi(reg::A2, csr::SCAUSE, 0x08);   // Set supervisor cause bits
         csrrci(reg::A3, csr::SIP, 0x04);      // Clear supervisor interrupt pending bits
-    };
+    }
+    .unwrap();
 
     assert_eq!(instructions.len(), 11);
 
@@ -671,7 +672,8 @@ fn test_aliases_with_macro() {
         add(reg::A1, reg::A0, reg::SP);     // Add a0 and sp, store in a1
         sub(reg::T0, reg::A1, reg::A0);     // Subtract a0 from a1, store in t0
         ret();                              // Return from function
-    };
+    }
+    .unwrap();
 
     assert_eq!(instructions.len(), 4);
 
@@ -711,13 +713,13 @@ fn test_comprehensive_alias_demo() {
 
         // Function body
         addi(reg::A0, reg::ZERO, 42);       // Load 42 into a0 (return value)
-
         // Function epilogue
         ld(reg::S0, reg::SP, 0);            // Restore frame pointer
         ld(reg::RA, reg::SP, 8);            // Restore return address
         addi(reg::SP, reg::SP, 16);         // Deallocate stack space
         ret();                              // Return
-    };
+    }
+    .unwrap();
 
     assert_eq!(instructions.len(), 9);
 
@@ -737,7 +739,8 @@ fn test_macro_chaining() {
         addi(reg::X1, reg::X0, 10);
         add(reg::X2, reg::X1, reg::X0);
         csrrw(reg::X3, csr::MSTATUS, reg::X2);
-    };
+    }
+    .unwrap();
 
     assert_eq!(instructions.len(), 3);
 
@@ -763,7 +766,8 @@ fn test_macro_comprehensive() {
         beq(reg::X1, reg::X2, 8);
         jal(reg::X1, 16);
         csrr(reg::X4, csr::MSTATUS);
-    };
+    }
+    .unwrap();
 
     assert_eq!(instructions.len(), 6);
 
@@ -780,11 +784,6 @@ fn test_macro_comprehensive() {
         .to_vec();
 
     assert_eq!(instructions, builder_instructions);
-
-    // Each instruction should be non-zero
-    for instr in &instructions {
-        assert!(instr.value() != 0);
-    }
 }
 
 // Binary correctness tests comparing JIT assembler with GNU assembler output
@@ -1621,7 +1620,8 @@ fn test_binary_correctness_multiline_macro_comparison() {
         add(reg::X3, reg::X1, reg::X2);
         sub(reg::X4, reg::X3, reg::X1);
         xor(reg::X5, reg::X3, reg::X4);
-    };
+    }
+    .unwrap();
 
     let mut builder = Riscv64InstructionBuilder::new();
     builder.lui(reg::X1, 0x12345);