stream-2: layout pass — place + route innerjib7ea-rev-a

[marcos-mendez]

Goal

First layout pass for `kicad/innerjib7ea-rev-a/innerjib7ea.kicad_pcb`: component placement + routing of all nets, respecting the 8-layer stackup, controlled-impedance rules, and DDR3/PCIe length-match constraints.

Prerequisites

• Schematic complete (ECP5 + power tree + DDR3 SO-DIMM + inter-card + JTAG + USB-UART).
• Stackup configured.

Acceptance

• All nets routed, no airwires.
• DRC clean.
• DDR3 byte-lane length match within ±5 mil per group.
• DDR3 address group length match within ±10 mil.
• PCIe Gen2 diff pairs length match within ±2 mil per pair.
• 3D viewer shows expected mechanical envelope (M.2 form factor or full-length card — pin to ADR).

Authored by Agent 2 (FPGA Hardware).