From 66d4be2af1fc40008dd67e2bb944fff3a00b0ac3 Mon Sep 17 00:00:00 2001 From: Ralf Anton Beier Date: Mon, 22 Jun 2026 10:49:16 +0200 Subject: [PATCH] =?UTF-8?q?docs(changelog):=20correct=20v0.11.51=20shrink?= =?UTF-8?q?=20confirmation=20scope=20=E2=80=94=20qemu-8KB,=20not=20on-sili?= =?UTF-8?q?con=20(#383)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gale's runtime confirmation (issue #383) was qemu + an 8 KB-constrained link (cortex-m3 lm3s6965evb: dissolves to bss 4240, links into 8 KB ~4.8 KB used, boots + 5000 poll rounds with correct values), NOT a physical STM32F100 reflash (gale's bench is a 128 KB G474RE). The release notes said "confirmed on-silicon" — an overclaim gale explicitly asked to correct. This states exactly what was verified: qemu-8KB-confirmed; physical F100 reflash pending hardware. The feature is confirmed working; only the confirmation SCOPE wording is fixed. Trace: skip Co-Authored-By: Claude Opus 4.8 --- CHANGELOG.md | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7d86b0e9..7ab85f16 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -34,7 +34,11 @@ NOBITS `.bss` reservation accordingly, unblocking the 8 KiB STM32F100 gust boot. - Verification: flag-off byte-identical on `msgq_put_359` (the native-pointer path); the native-pointer differential passes; flag-on runtime exercised on `native_pointer_shadow_stack` (the store through the re-based SP lands - in-region). gale confirmed on-silicon (issue #383 closed COMPLETED). + in-region). **qemu + 8 KB-constrained-link confirmed** by gale (cortex-m3 + `lm3s6965evb`): the gust kernel dissolves to `.bss` 4240, links into 8 KB + (~4.8 KB used, was un-linkable), boots and runs 5000 poll rounds with correct + values (`gust_mix(1024)=1500`, `pwm=1522`). Physical STM32F100 reflash is + pending hardware — NOT literal-silicon-confirmed (gale #383). - Tests `shadow_stack_shrink_383.rs`; tracked `VCR-MEM-001`. - **Cross-backend op-parity oracle** (#387, `VCR-SEL-005`): the ARM-vs-RISC-V