No DP output on jetson nano

[pablitok]

Hi, I'm trying to use this repo to create a ubuntu version for my jetson nano 4g, the image creates well, I can boot it, but I'm using the jetson with a DP monitor and it's not giving me video signal. If I connect it via hdmi, it works fine.
Connected to DP seems to have signal (when there is no signal the screen monitor shows a text and go to sleep, also I see that the monitor is blank but turned on)

With other image (the official one or this one) Display Port has video signal

[pythops]

There is this thread from nvidia forums and it seems that it is related to the DP version of the monitor
https://forums.developer.nvidia.com/t/displayport-not-working/71989/11

[pablitok]

Hi, thanks for your reply, My monitor (Dell P2419hc) supports DP 1.2. Now I'm building an image with xrandr to check if with that I can set the output to DP El mié, 5 mar 2025 a la(s) 10:18 a.m., Badr ***@***.***) escribió:

…

There is this thread from nvidia forums and it seems that it is related to the DP version of the monitor https://forums.developer.nvidia.com/t/displayport-not-working/71989/11 — Reply to this email directly, view it on GitHub <#152 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABPXOJ3AX3U6P5MKMIIRZOT2S32RDAVCNFSM6AAAAABYMCHGSWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDOMBQHEYDMOBUGM> . You are receiving this because you authored the thread.Message ID: ***@***.***> [image: pythops]*pythops* left a comment (pythops/jetson-image#152) <#152 (comment)> There is this thread from nvidia forums and it seems that it is related to the DP version of the monitor https://forums.developer.nvidia.com/t/displayport-not-working/71989/11 — Reply to this email directly, view it on GitHub <#152 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABPXOJ3AX3U6P5MKMIIRZOT2S32RDAVCNFSM6AAAAABYMCHGSWVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDOMBQHEYDMOBUGM> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[nenekodev]

I have the same problem on Nano B01. Here is the event log output by the dmesg:

[  134.076022] tegradc tegradc.1: dp: plug event received
[  134.076270] hpd: state 3 (Disabled), hpd 1, pending_hpd_evt 1
[  134.076311] hpd: switching from state 3 (Disabled) to state 0 (Reset)
[  134.177094] hpd: state 0 (Reset), hpd 1, pending_hpd_evt 0
[  134.177192] tegradc tegradc.1: blank - powerdown
[  134.177389] extcon-disp-state extcon:disp-state: cable 44 state 0 already set.
[  134.177422] Extcon DP: HPD disabled
[  134.177451] hpd: hpd_switch 0
[  134.177489] hpd: switching from state 0 (Reset) to state 1 (Check Plug)
[  134.177565] hpd: state 1 (Check Plug), hpd 1, pending_hpd_evt 0
[  134.177614] hpd: switching from state 1 (Check Plug) to state 2 (Check EDID)
[  134.184965] hpd: state 2 (Check EDID), hpd 1, pending_hpd_evt 0
[  134.190866] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.195649] tegradc tegradc.0: blank - powerdown
[  134.195679] tegradc tegradc.0: unblank
[  134.195738] tegradc tegradc.0: unblank
[  134.195764] tegradc tegradc.1: blank - powerdown
[  134.209946] tegradc tegradc.1: nominal-pclk:148500000 parent:148500000 div:1.0 pclk:148500000 147015000~161865000
[  134.211525] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.215240] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[  134.220187] dp lt: state 0 (Reset), pending_lt_evt 1
[  134.220191] dp lt: switching from state 0 (Reset) to state 0 (Reset)
[  134.220195] dp lt: state 0 (Reset), pending_lt_evt 0
[  134.221383] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[  134.221518] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[  134.221523] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  134.221754] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[  134.221762] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[  134.221769] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[  134.221777] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[  134.221782] dp lt: tx_pu: 0x20
[  134.222671] dp lt: CR not done
[  134.223112] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  134.223114] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  134.223116] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  134.223118] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  134.223120] dp lt: CR retry
[  134.223123] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[  134.223127] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  134.223136] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  134.223144] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  134.223151] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  134.223159] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  134.223163] dp lt: tx_pu: 0x30
[  134.224087] dp lt: CR done
[  134.224090] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  134.224094] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  134.226712] dp lt: CE done
[  134.226717] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  134.227034] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.227316] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.227548] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x400000 did not specify bpp
[  134.227774] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.227999] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.228225] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.228450] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  134.228678] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.228903] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.229128] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.229354] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.229578] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.229803] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp
[  134.230028] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp
[  134.230033] tegradc tegradc.1: blank - powerdown
[  134.260385] dp lt: state 5 (link training pass), pending_lt_evt 1
[  134.260387] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[  134.260389] dp lt: state 0 (Reset), pending_lt_evt 0
[  134.260393] dp lt: link training force disable
[  134.260395] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[  134.281140] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.281151] tegradc tegradc.1: unblank
[  134.311611] tegradc tegradc.1: nominal-pclk:148500000 parent:148500000 div:1.0 pclk:148500000 147015000~161865000
[  134.313000] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.316591] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[  134.321016] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[  134.321019] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[  134.321021] dp lt: state 0 (Reset), pending_lt_evt 0
[  134.322211] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[  134.322353] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[  134.322357] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  134.322592] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[  134.322599] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[  134.322607] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[  134.322614] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[  134.322620] dp lt: tx_pu: 0x20
[  134.323525] dp lt: CR not done
[  134.323973] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  134.323975] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  134.323977] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  134.323978] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  134.323980] dp lt: CR retry
[  134.323982] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[  134.323985] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  134.323995] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  134.324003] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  134.324011] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  134.324018] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  134.324022] dp lt: tx_pu: 0x30
[  134.324928] dp lt: CR done
[  134.324930] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  134.324934] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  134.327299] dp lt: CE done
[  134.327302] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  134.327604] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.327831] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.328058] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x400000 did not specify bpp
[  134.328287] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.335390] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.335628] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.335857] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  134.336085] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.336312] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.336503] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.336731] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.336959] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.337187] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp
[  134.337415] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp
[  134.337420] tegradc tegradc.1: blank - powerdown
[  134.361003] dp lt: state 5 (link training pass), pending_lt_evt 1
[  134.361014] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[  134.361026] dp lt: state 0 (Reset), pending_lt_evt 0
[  134.361040] dp lt: link training force disable
[  134.361047] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[  134.381697] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.381708] tegradc tegradc.1: unblank
[  134.412127] tegradc tegradc.1: nominal-pclk:148500000 parent:148500000 div:1.0 pclk:148500000 147015000~161865000
[  134.413515] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.417103] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[  134.421519] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[  134.421522] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[  134.421524] dp lt: state 0 (Reset), pending_lt_evt 0
[  134.422715] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[  134.422858] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[  134.422862] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  134.423097] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[  134.423105] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[  134.423112] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[  134.423120] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[  134.423125] dp lt: tx_pu: 0x20
[  134.424029] dp lt: CR not done
[  134.424494] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  134.424496] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  134.424497] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  134.424499] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  134.424501] dp lt: CR retry
[  134.424503] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[  134.424507] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  134.424519] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  134.424526] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  134.424533] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  134.424540] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  134.424544] dp lt: tx_pu: 0x30
[  134.425446] dp lt: CR done
[  134.425448] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  134.425452] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  134.427813] dp lt: CE done
[  134.427815] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  134.427925] extcon-disp-state extcon:disp-state: cable 44 state 1
[  134.427928] Extcon DP: HPD enabled
[  134.427947] hpd: Display connected, hpd_switch 1
[  134.427950] hpd: switching from state 2 (Check EDID) to state 4 (Enabled)
[  134.428348] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[  134.430911] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.431183] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x400000 did not specify bpp
[  134.431433] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.431672] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.431907] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.432141] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x0 did not specify bpp
[  134.432374] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.432609] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.432846] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.433081] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.433315] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x80 did not specify bpp
[  134.433550] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10400000 did not specify bpp
[  134.433783] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10420000 did not specify bpp
[  134.436275] tegradc tegradc.0: blank - powerdown
[  134.436285] tegradc tegradc.0: unblank
[  134.436309] tegradc tegradc.0: unblank
[  134.436319] tegradc tegradc.1: blank - powerdown
[  134.461342] dp lt: state 5 (link training pass), pending_lt_evt 1
[  134.461346] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[  134.461349] dp lt: state 0 (Reset), pending_lt_evt 0
[  134.461354] dp lt: link training force disable
[  134.461356] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)

I think the problem may arise here causing the link training to be reset multiple times, since this log appears repeatedly:

tegradc.1: DP: no prod_c_hbr prod settings node in device tree

Does this mean we need to recompile the device tree? Here is a discussion that seems to be related to this issue：

https://forums.developer.nvidia.com/t/display-port/53284/2

https://forums.developer.nvidia.com/t/edp-link-training-fails/110364/16

Hope the information I provided will be helpful.

[nenekodev]

I just solved this problem, here are the steps for reference.

1. Decompile the device tree file on Jetson Nano:

$ dtc -I fs /proc/device-tree > extracted.dts

2. Open the file with a text editor, locate node / > host1x > sor > prod-settings, and append the following content after prod_c_dp:

```
prod_c_hbr {
	prod = <
		0x00000590 0x00f00000 0x00400000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x04 
		>;
};
prod_c_hbr2 {
	prod = <
		0x00000590 0x00f00000 0x00600000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x06 
		>;
};
prod_c_rbr {
	prod = <
		0x00000590 0x00f00000 0x00300000   //SOR_NV_PDISP_SOR_PLL1_0	23:20=LOADADJ	0x03
		>;
};
```

then save it as a different file name. Here is extracted-hbr.dts

3. Confirm the current kernel dtb file name, and backup it
$ ls /boot/dtb/

On my device, it shows kernel_tegra210-p3448-0000-p3449-0000-b00.dtb

$ sudo mv /boot/dtb/kernel_tegra210-p3448-0000-p3449-0000-b00.dtb /boot/dtb/kernel_tegra210-p3448-0000-p3449-0000-b00.dtb.bak

4. Compile the new dtb file:

$ dtc -I dts -O dtb extracted-hbr.dts -o kernel_tegra210-p3448-0000-p3449-0000-b00-hbr.dtb

5. Replace original dtb file with your new dtb file:

$ sudo cp ./kernel_tegra210-p3448-0000-p3449-0000-b00-hbr.dtb /boot/dtb/kernel_tegra210-p3448-0000-p3449-0000-b00.dtb

6. reboot

[pablitok]

@nenekodev I have a couple of questions for you:

1. How did you manage to install ubuntu 22.04 and keep your graphical interface running? I'm only getting a blank screen.
2. this approach works for the console too? or is just for XWindows?

[nenekodev]

@nenekodev I have a couple of questions for you:

1. How did you manage to install ubuntu 22.04 and keep your graphical interface running? I'm only getting a blank screen.

2. this approach works for the console too? or is just for XWindows?

@pablitok Yes, it's definitely a little weird...

For question 2 first, I just tried using init 3 or Ctrl+Alt+F1 to return to the console and found that there was indeed no output from the DP port.

Here's the dmesg log:

[ 1389.268182] tegradc tegradc.0: blank - powerdown
[ 1389.268233] tegradc tegradc.1: blank - powerdown
[ 1389.330472] dp lt: state 5 (link training pass), pending_lt_evt 1
[ 1389.330475] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[ 1389.330477] dp lt: state 0 (Reset), pending_lt_evt 0
[ 1389.330481] dp lt: link training force disable
[ 1389.330483] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[ 1389.372398] tegradc tegradc.0: blank - powerdown
[ 1389.372420] tegradc tegradc.0: unblank
[ 1389.372432] tegradc tegradc.0: update windows ret = -14
[ 1389.372434] tegradc tegradc.0: sync windows ret = -14
[ 1395.174832] tegradc tegradc.1: blank - powerdown
[ 1395.175085] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 1395.175103] tegradc tegradc.1: unblank
[ 1395.205539] tegradc tegradc.1: nominal-pclk:148500000 parent:148500000 div:1.0 pclk:148500000 147015000~161865000
[ 1395.206940] tegradc tegradc.1: tegra_dp_get_bpp: vmode=0x10600000 did not specify bpp
[ 1395.210540] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[ 1395.215002] dp lt: state 4 (link training fail/disable), pending_lt_evt 1
[ 1395.215004] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[ 1395.215007] dp lt: state 0 (Reset), pending_lt_evt 0
[ 1395.216202] tegradc tegradc.1: DP: no prod_c_hbr prod settings node in device tree
[ 1395.216346] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[ 1395.216350] dp lt: state 2 (clock recovery), pending_lt_evt 0
[ 1395.216588] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[ 1395.216595] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[ 1395.216603] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[ 1395.216611] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[ 1395.216616] dp lt: tx_pu: 0x20
[ 1395.217520] dp lt: CR done
[ 1395.217523] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[ 1395.217527] dp lt: state 3 (channel equalization), pending_lt_evt 0
[ 1395.219893] dp lt: CE done
[ 1395.219895] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[ 1395.220067] tegradc tegradc.1: unblank
[ 1395.220347] tegradc tegradc.0: blank - powerdown

Notice that it mentioned tegradc.1: DP: no prod_c_hbr prod settings node in device tree again. But after pressing Ctrl+Alt+f7 or restarting and switching back to the graphical interface, everything is normal.

Btw, I recalled that if you only plug in the DP cable and start it, the device will not display the Nvidia logo on the boot interface, but will directly display the mouse pointer and desktop environment after XWindows starts. So this may mean that the solution is only applicable to XWindows.

---

For question 1, This link gives a reference, pointing out that the default xorg server version in the Ubuntu 22.04 may have ABI incompatibility issues, which will make the XWindow unable to start, so you need to specify the xorg version first and prohibit updating the package:

sudo apt install xserver-xorg-core=2:1.20.8-2ubuntu2
sudo apt-mark hold xserver-xorg-core

Then install the x-window software and your favorite desktop environment. Here I have installed LXDE in a minimal way, and subsequently modified some of my personal flavor settings.

sudo apt install xorg lightdm lightdm-gtk-greeter lxde-core lxterminal pcmanfm --no-install-recommends 

Finally, don't forget to change the default startup to the graphical interface. If you don't mind typing startx every time you enter the system, you can leave it unchanged.

sudo systemctl set-default graphical.target

[nenekodev]

@pablitok

After some research, I think the problem is probably the lack of nvidia's proprietary DRM driver in the kernel, because the DP output comes from the buffer and drm before the GUI is started.

I found that only version file in the /sys/class/drm/ folder. Typing lsmod | grep tegra_drm also had no results, which means that the kernel may not have loaded the DRM module.

So I tried to compile a kernel with host1x and tegra_drm support using this project, but unfortunately I encountered some problems and failed to compile. It seems that the kernel version, L4T version (32.7.6 in my case) and host1x driver version are not correctly corresponding.

I will continue to follow up on this issue, but you may try to back up the existing kernel and try the official or third-party compiled version to see if you can get DP to work properly in the console interface.

[pablitok]

Hi @nenekodev , yesterday I was looking around to see if I can see something interesting and the only thing I saw is that lspci is not showing nothing related to monitors and with startx I was getting a error message saying something about no screen found.
Maybe I should start again with a 22.04 fresh image. I was trying to compile the kernel following this but with no luck, always had some issue with some module, even if I didn't add anything besides what is stated in that guide.

[nenekodev]

@pablitok Maybe you can try the kernel compiled by myself

https://github.com/nenekodev/jetson-linux-build/releases/tag/4.9.337-tegra

And the image automatically built using GitHub action (note that this image has not yet installed the graphical interface, uses the default kernel, and the device tree has not been modified. After flashing the image, you can follow the steps I provided before to modify the device tree to achieve DP support for the graphical interface)

https://drive.google.com/file/d/1c8GcOcI2X_c58oL55cMeN5YdyFZyQ5Mp/view?usp=sharing

[pablitok]

Great, after work I'll try both

[pablitok]

@nenekodev I'm trying the kernel image.
Xwindows is working in hdmi out of the box, but when I connected the DP and changed to it, it didn't show anything, and when I tried to go back to hdmi I get only a blank screen. I'm using your kernel and the edited dbt from your comment
With dmesg I see a lot of lines with "dp" in them, for example:

[  255.782876] tegradc tegradc.1: dp: aux write defer (0x10020000) -- 6
[  255.785671] dp lt: CR not done
[  255.786968] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  255.786970] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  255.786972] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  255.786973] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  255.786975] dp lt: CR retry
[  255.786978] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[  255.786984] dp lt: state 2 (clock recovery), pending_lt_evt 0
[  255.786998] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  255.787008] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  255.787017] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  255.787027] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  255.787031] dp lt: tx_pu: 0x30
[  255.787924] tegradc tegradc.1: dp: aux write defer (0x10020000) -- 6
[  255.790644] dp lt: CR done
[  255.790647] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  255.790651] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  255.792016] tegradc tegradc.1: dp: aux read defer (0x10020000) -- 6
[  255.794104] dp lt: CE not done
[  255.795391] dp lt: new config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[  255.795392] dp lt: new config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[  255.795394] dp lt: new config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[  255.795396] dp lt: new config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[  255.795406] dp lt: config: lane 0: vs level: 2, pe level: 0, pc2 level: 0
[  255.795415] dp lt: config: lane 1: vs level: 2, pe level: 0, pc2 level: 0
[  255.795425] dp lt: config: lane 2: vs level: 2, pe level: 0, pc2 level: 0
[  255.795434] dp lt: config: lane 3: vs level: 2, pe level: 0, pc2 level: 0
[  255.795438] dp lt: tx_pu: 0x40
[  255.796319] tegradc tegradc.1: dp: aux write defer (0x10020000) -- 6
[  255.797978] dp lt: CE retry
[  255.797980] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization)
[  255.797984] dp lt: state 3 (channel equalization), pending_lt_evt 0
[  255.801404] dp lt: CE done
[  255.801407] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  255.802241] extcon-disp-state extcon:disp-state: cable 44 state 1
[  255.802245] Extcon DP: HPD enabled
[  255.802393] hpd: Display connected, hpd_switch 1
[  255.802397] hpd: switching from state 2 (Check EDID) to state 4 (Enabled)

[nenekodev]

Your dmesg log is different from mine, so could you please give me the full dmesg output since booting after plugging in DP?

Also, I'm not sure if the hardware carrier you are using is the same as mine (B01, internal model P3449-45-13450-0000-100). I'm trying to compile a kernel with tegra host1x and tegra drm support on the official ubuntu 18.04 jetpack 4.6 to see if that solves the problem.

[pablitok]

Hi! last night I tried your image and worked, seems that the DP output only works in X.
How can I check the hardware version?

[nenekodev]

The easiest way is to check the interface configuration on the left side of the carrier board. If there are two CSI camera interfaces, it is B01, otherwise it is A02. More detailed instructions here: https://www.arducam.com/nvidia-jetson-nano-b01-update-dual-camera/

Since JetPack 4.4.1, the official system mirrors of the two are common, discussed here: https://forums.developer.nvidia.com/t/do-jetson-nano-b01-and-a02-use-the-same-sd-card-mirror/165278

But I’m not sure whether the system image we built ourselves is also compatible with the differences in details between the two versions of hardware, so I want to ask you to confirm whether the hardware version you are using is the same as mine, which is the later version B01.

[nenekodev]

I just tried the latest official image jetpack 4.6.1. After flashing it to the SD card, its DP also only works in the graphical interface. Once it switches to the character interface, the screen will go black. Therefore, I suspect that this is caused by nvidia's failure to do a good job of the graphics driver under the character interface.

This was later confirmed on the linux kernel website:
https://www.kernel.org/doc/html/v4.16/gpu/tegra.html#edp-dp

eDP was first introduced in Tegra124 where it was used to drive the display panel for notebook form factors. 

Tegra210 added support for full DisplayPort support, though this is currently not implemented in the drm/tegra driver.

Note that tegra 210 is the soc of jetson nano.

I looked up nvidia's official developer forum and found two posts mentioning this issue. The community administrator replied that

https://forums.developer.nvidia.com/t/cant-load-tegra-drm-module-on-custom-build-kernel/73771/2

CONFIG_DRM_TEGRA is not supported on tegra kernel yet. 
However, we have a userspace library libdrm-nvdc.so that can help you do drm-kms.

https://forums.developer.nvidia.com/t/tegra-drm-driver-building/276603/3

The DRM software stacks are prebuilt and not open source.

which confirmed my guess: for the jetson nano product and the corresponding L4T 32.x version, there is no kernel-level drm driver, but only user-mode driver - so you can use the DP port to output GPU content normally in the Xwindow, but you can only use HDMI output in the character interface.

Moreover, because Jetson Nano and JetPack 4.x have been officially listed as obsolete products, they probably don't plan to continue to follow up on this development.

---

Later, I found the kernel compilation document of L4T 35.x on the nvidia official website:

This may answer why I failed to compile the kernel with nvidia-drm. Maybe only L4T35.x and above can compile successfully.