diff --git a/librz/arch/cpus/c166-c166-generic.sdb.txt b/librz/arch/cpus/c166-c166-generic.sdb.txt index 3b09a75435d..d1f8b673325 100644 --- a/librz/arch/cpus/c166-c166-generic.sdb.txt +++ b/librz/arch/cpus/c166-c166-generic.sdb.txt @@ -37,9 +37,9 @@ IDX1.comment=MAC Address Pointer 1 ADEIC=io ADEIC.address=0xff9a ADEIC.comment=A/D Converter Overrun Error Interrupt Control Register -SYSCON=io -SYSCON.address=0xff0c -SYSCON.comment=CPU System Configuration Register +BUSCON0=io +BUSCON0.address=0xff0c +BUSCON0.comment=Bus Configuration Register 0 (Stack Pointer Segment Register [SPSEG]) VECSEG=io VECSEG.address=0xff12 VECSEG.comment=Bus Configuration Register 0 @@ -313,9 +313,6 @@ CCM7.comment=CAPCOM Mode Control Register 7 CP=io CP.address=0xfe10 CP.comment=CPU Context Pointer Register -R1=io -R1.address=0xfe12 -R1.comment=General Purpose Word Register R1 CRIC=io CRIC.address=0xff6a CRIC.comment=GPT2 CAPREL Interrupt Ctrl. Register diff --git a/librz/arch/filter.c b/librz/arch/filter.c index 2c436c57e10..5220ac8b646 100644 --- a/librz/arch/filter.c +++ b/librz/arch/filter.c @@ -6,7 +6,9 @@ #include #include #include +#include #include "analysis_private.h" +#include "rz_analysis.h" #define isx86separator(x) ( \ (x) == ' ' || (x) == '\t' || (x) == '\n' || (x) == '\r' || (x) == ' ' || \ @@ -209,6 +211,12 @@ static bool filter(RzParse *p, ut64 addr, RzFlag *f, RzAnalysisHint *hint, char ut64 off; bool x86 = false; bool arm = false; + bool c16x = false; + if (p && p->analb.analysis) { + if (strstr(p->analb.analysis->cur->arch, "c166")) { + c16x = true; + } + } if (p && p->cur && p->cur->name) { if (strstr(p->cur->name, "x86")) { x86 = true; @@ -445,7 +453,7 @@ static bool filter(RzParse *p, ut64 addr, RzFlag *f, RzAnalysisHint *hint, char } } } - if (hint) { + if (hint && !c16x) { char *num_start = ptr; char *num_end = ptr2; const int nw = hint->nword; diff --git a/librz/arch/isa/c166/c166_common.c b/librz/arch/isa/c166/c166_common.c new file mode 100644 index 00000000000..67a646010a4 --- /dev/null +++ b/librz/arch/isa/c166/c166_common.c @@ -0,0 +1,69 @@ +// SPDX-FileCopyrightText: 2025-2026 Sergey Sharshunov +// SPDX-License-Identifier: LGPL-3.0-only + +#include "c166/c166_common.h" + +const char *const c166_rw[] = { + "r0", "r1", "r2", "r3", + "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", + "r12", "r13", "r14", "r15", +}; + +const char *const c166_rb[] = { + "rl0", "rh0", + "rl1", "rh1", + "rl2", "rh2", + "rl3", "rh3", + "rl4", "rh4", + "rl5", "rh5", + "rl6", "rh6", + "rl7", "rh7", +}; + +/** + * Maps hexcodes to condition codes for JMPR instructions + * Used to determine the condition code for conditional jump instructions + */ +// C166 condition code names +// static +const char *const conds_names[] = { + [C166_CC_UC] = "cc_UC", ///< Unconditional + [C166_CC_V] = "cc_V", ///< Overflow + [C166_CC_NV] = "cc_NV", ///< No Overflow + [C166_CC_N] = "cc_N", ///< Negative + [C166_CC_NN] = "cc_NN", ///< Not Negative + [C166_CC_C] = "cc_C/ULT", ///< Carry + [C166_CC_NC] = "cc_NC/UGE", ///< No Carry + [C166_CC_EQ] = "cc_Z/EQ", ///< Equal + [C166_CC_NE] = "cc_NZ/NE", ///< Not Equal + [C166_CC_ULE] = "cc_ULE", ///< Unsigned Less Than or Equal + [C166_CC_UGT] = "cc_UGT", ///< Unsigned Greater Than + [C166_CC_SLE] = "cc_SLE", ///< Signed Less Than or Equal + [C166_CC_SGE] = "cc_SGE", ///< Signed Greater Than or Equal + [C166_CC_SGT] = "cc_SGT", ///< Signed Greater Than + [C166_CC_NET] = "cc_NET", ///< Not Equal and Not End-of-Table + + [C166_CC_SLT] = "cc_SLT", ///< Signed Less Than + + [C166_CC_NUSR0] = "cc_NUSR0", ///< USR-bit 0 is cleared (*) + [C166_CC_NUSR1] = "cc_NUSR1", ///< USR-bit 1 is cleared (*) + [C166_CC_USR0] = "cc_USR0", ///< USR-bit 0 is set 1 + [C166_CC_USR1] = "cc_USR1" ///< USR-bit 1 is set 1 +}; +// clang-format on + +const char *conds(ut8 cc) { + return conds_names[cc << 1]; +} + +const char *conds_extended(ut8 cc) { + return conds_names[cc]; +} + +const char *const c166_extx_names[] = { + "exts", + "extp", + "extsr", + "extpr" +}; diff --git a/librz/arch/isa/c166/c166_common.h b/librz/arch/isa/c166/c166_common.h new file mode 100644 index 00000000000..e994c73d600 --- /dev/null +++ b/librz/arch/isa/c166/c166_common.h @@ -0,0 +1,147 @@ +// SPDX-FileCopyrightText: 2025-2026 Sergey Sharshunov +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef C166_COMMON_H +#define C166_COMMON_H + +#include +#include +#include +#include + +#define H_NIB(x) (((x) & 0xF0) >> 4) ///< High nibble +#define L_NIB(x) ((x) & 0x0F) ///< Low nibble + +// Core Special Function Registers (CSFR) +#define BASE_GPR_ADDR 0xFE10 ///< Base address for calculate GPR physical address (also REG_CP) +#define BASE_SFR_ADDR 0xFE00 ///< Base address for calculate SFR physical address (also REG_DPP0) +#define BASE_ESFR_ADDR 0xF000 ///< Base address for calculate ESFR physical address +#define BASE_RAM_B_ADDR 0xFD00 ///< Base address for calculate RAM physical address (bit) +#define BASE_SFR_B_ADDR 0xFF00 ///< Base address for calculate SFR physical address (bit) +#define BASE_ESFR_B_ADDR 0xF100 ///< Base address for calculate ESFR physical address (bit) + +#define QX0 0xF000 ///< MAC Offset Register X0 (ESFRs) +#define QX1 0xF002 ///< MAC Offset Register X1 (ESFRs) +#define QR0 0xF004 ///< MAC Offset Register R0 (ESFRs) +#define QR1 0xF006 ///< MAC Offset Register R1 (ESFRs) +#define CPUID 0xF00C ///< CPU Identification Register (ESFRs) + +#define REG_PSW 0xFF10 ///< Processor Status Word + +#define REG_DPP0 (BASE_SFR_ADDR + 0x00) ///< CPU Data Page Pointer 0 Register (10 bits) +#define REG_DPP1 (BASE_SFR_ADDR + 0x02) ///< CPU Data Page Pointer 1 Register (10 bits) +#define REG_DPP2 (BASE_SFR_ADDR + 0x04) ///< CPU Data Page Pointer 2 Register (10 bits) +#define REG_DPP3 (BASE_SFR_ADDR + 0x06) ///< CPU Data Page Pointer 3 Register (10 bits) +#define REG_CSP (BASE_SFR_ADDR + 0x08) ///< Code Segment Pointer +#define REG_MDH (BASE_SFR_ADDR + 0x0c) ///< Multiply Divide High Word +#define REG_MDL (BASE_SFR_ADDR + 0x0e) ///< Multiply Divide Low Word +#define REG_CP (BASE_SFR_ADDR + 0x10) ///< CPU Context Pointer Register +#define REG_SP (BASE_SFR_ADDR + 0x12) ///< Stack Pointer Register +#define REG_STKOV (BASE_SFR_ADDR + 0x14) ///< Stack Overflow Pointer +#define REG_STKUN (BASE_SFR_ADDR + 0x16) ///< Stack Underflow Pointer +#define REG_CPUCON1 (BASE_SFR_ADDR + 0x18) ///< Core Control Register +#define REG_CPUCON2 (BASE_SFR_ADDR + 0x1A) ///< Core Control Register +#define REG_MAL (BASE_SFR_ADDR + 0x5C) ///< MAC Accumulator – Low Word +#define REG_MAH (BASE_SFR_ADDR + 0x5E) ///< MAC Accumulator – High Word + +#define IDX0 0xFF08 ///< Address Pointer IDX0 +#define IDX1 0xFF0A ///< Address Pointer IDX1 +#define SPSEG 0xFF0C ///< Stack Pointer Segment Register +#define MDC 0xFF0E ///< (Bit addressable) Multiply Divide Control Register +#define PSW 0xFF10 ///< (Bit addressable) Program Status Word +#define VECSEG 0xFF12 ///< (Bit addressable) Vector Table Segment Register +#define ZEROS 0xFF1C ///< (Bit addressable) Constant Value 0s Register (read only) +#define ONES 0xFF1E ///< (Bit addressable) Constant Value 1s Register (read only) +#define TFR 0xFFAC ///< (Bit addressable) Trap Flag Register +#define MRW 0xFFDA ///< (Bit addressable) MAC Repeat Word +#define MCW 0xFFDC ///< (Bit addressable) MAC Control Word +#define MSW 0xFFDE ///< (Bit addressable) MAC Status Word + +#define REG_ASC0_TIC 0xFF6C ///< Serial Channel 0 Transmit Interrupt Control Register +#define REG_ASC0_RIC 0xFF6E ///< Serial Channel 0 Receive Interrupt Control Register + +/*! + * \brief C166 Branch Condition Codes + * + * Defines condition codes used for conditional branching instructions + * Datasheet page 39 + * (*) Only usable with the JMPA and CALLA instructions + */ +// clang-format off +typedef enum { + C166_CC_UC = 0x00, ///< CCNc = 0x00; [0D] Unconditional + C166_CC_NET = 0x02, ///< CCNc = 0x01; [1D] Not equal AND not end of table + // C166_CC_Z = 0x04, ///< CCNc = 0x02; [2D] Zero + C166_CC_EQ = 0x04, ///< CCNc = 0x02; [2D] Equal + // C166_CC_NZ = 0x06, ///< CCNc = 0x03; [3D] Not zero + C166_CC_NE = 0x06, ///< CCNc = 0x03; [3D] Not equal + C166_CC_V = 0x08, ///< CCNc = 0x04; [4D] Overflow + C166_CC_NV = 0x0A, ///< CCNc = 0x05; [5D] No overflow + C166_CC_N = 0x0C, ///< CCNc = 0x06; [6D] Negative + C166_CC_NN = 0x0E, ///< CCNc = 0x07; [7D] Not negative + C166_CC_C = 0x10, ///< CCNc = 0x08; [8D] Carry + // C166_CC_ULT = 0x10, ///< CCNc = 0x08; [8D] Unsigned less than + C166_CC_NC = 0x12, ///< CCNc = 0x09; [9D] No carry + // C166_CC_UGE = 0x12, ///< CCNc = 0x09; [9D] Unsigned greater than or equal + C166_CC_SGT = 0x14, ///< CCNc = 0x0A; [AD] Signed greater than + C166_CC_SLE = 0x16, ///< CCNc = 0x0B; [BD] Signed less than or equal + C166_CC_SLT = 0x18, ///< CCNc = 0x0C; [CD] Signed less than + C166_CC_SGE = 0x1A, ///< CCNc = 0x0D; [DD] Signed greater than or equal + C166_CC_UGT = 0x1C, ///< CCNc = 0x0E; [ED] Unsigned greater than + C166_CC_ULE = 0x1E, ///< CCNc = 0x0F; [FD] Unsigned less than or equal + + C166_CC_NUSR0 = 0x01, ///< USR-bit 0 is cleared (*) + C166_CC_NUSR1 = 0x03, ///< USR-bit 1 is cleared (*) + C166_CC_USR0 = 0x05, ///< USR-bit 0 is set 1 + C166_CC_USR1 = 0x07 ///< USR-bit 1 is set 1 +} C166CondCode; + +typedef enum { + C166_EXT_MODE_NONE, + C166_EXT_MODE_ATOMIC, + C166_EXT_MODE_REG, + C166_EXT_MODE_PAGE, + C166_EXT_MODE_SEG, +} C166ExtMode; + +// clang-format off +typedef struct { + bool esfr; ///< Extended register sequence active + C166ExtMode mode; ///< Extended page/seq mode + ut8 i; ///< Number of unstructions remaining until state exits + ut16 value; ///< Value of ext +} C166ExtState; + +typedef struct { + ut32 last_addr; ///< State of last addr dissassembled + C166ExtState ext; + RzPVector /**/ *token_patterns; + bool inited; +} C166State; +// clang-format on + +extern const char *const c166_rw[]; +extern const char *const c166_rb[]; +extern const char *const conds_names[]; +extern const char *const c166_extx_names[]; + +const char *conds(ut8 cc); +const char *conds_extended(ut8 cc); + +static inline bool IS_GPR(ut8 addr) { + return addr >= 0xF0 && addr <= 0xFF; +} + +static inline bool IS_RAM(ut8 addr) { + return addr <= 0x7F; +} + +static inline bool IS_rSFR(ut8 addr) { + return addr <= 0xEF; +} + +static inline bool IS_bSFR(ut8 addr) { + return addr >= 0x80 && addr <= 0xEF; +} + +#endif /* C166_COMMON_H */ \ No newline at end of file diff --git a/librz/arch/isa/c166/c166_disas.c b/librz/arch/isa/c166/c166_disas.c index 1bbcd46ad3b..62312200359 100644 --- a/librz/arch/isa/c166/c166_disas.c +++ b/librz/arch/isa/c166/c166_disas.c @@ -15,7 +15,7 @@ */ #include -#include +// #include #include #include @@ -344,21 +344,21 @@ static const char *c166_instr_name(ut8 instr) { } } -const char *c166_extx_names[] = { - "exts", - "extp", - "extsr", - "extpr" -}; - RZ_API void c166_activate_ext(RZ_NONNULL C166State *state, ut32 addr, C166ExtState ext) { + rz_return_if_fail(ext.i > 0); + rz_return_if_fail(ext.i < 5); // rz_return_if_fail(state->ext.i == 0); // realy need? - rz_return_if_fail(ext.i <= 3); + if (ext.i > 4) { + printf("ext.i: %d, addr: 0x%x\n", ext.i, addr); + } + // rz_return_if_fail(ext.i <= 3); state->ext = ext; state->last_addr = addr; } RZ_API void c166_maybe_deactivate_ext(RZ_NONNULL C166State *state, ut32 addr) { + // printf("c166_maybe_deactivate_ext addr: 0x%x, state->last_addr: 0x%x, state->ext.i: %i\n", + // addr, state->last_addr, state->ext.i); if (addr == state->last_addr) { return; } @@ -383,14 +383,39 @@ RZ_API void c166_maybe_deactivate_ext(RZ_NONNULL C166State *state, ut32 addr) { static const char *c166_fmt_mem(const C166ExtState *ext, char *buf, ut16 mem) { const st32 i = (mem >> 14) & 0b11; switch (ext->mode) { + case C166_EXT_MODE_REG: case C166_EXT_MODE_NONE: { const ut16 addr = BASE_SFR_ADDR + (i * 2); snprintf(buf, 16, "0x%x:0x%04x", addr, mem & 0x3FFF); break; } case C166_EXT_MODE_SEG: { - const ut32 seg = ((ut32)(ext->value & 0xFF)) << 16; - snprintf(buf, 12, "0x%06x", seg | (mem & 0x3FFF)); + const ut32 seg = ((ut32)(ext->value & 0xFF));// << 16; + // snprintf(buf, 19, "0x%04x:0x%04x", + // 0xfe00 | ((seg - 1) * 2), + // (mem & 0x3FFF)); + switch (seg) { + case 1: + snprintf(buf, 16, "0xfe00:0x%04x", (mem & 0x3FFF)); + break; + case 2: + snprintf(buf, 16, "0xfe02:0x%04x", (mem & 0x3FFF)); + break; + case 3: + snprintf(buf, 16, "0xfe04:0x%04x", (mem & 0x3FFF)); + break; + case 4: + snprintf(buf, 16, "0xfe06:0x%04x", (mem & 0x3FFF)); + break; + default: + printf("seg: %d 0x%04x [0x%08x]\n", + seg, mem, ext->value); + snprintf(buf, 19, "0x%04x:0x%04x", + 0xfe00 | ((seg - 1) * 2), + (mem & 0x3FFF)); + rz_warn_if_reached(); + } + // snprintf(buf, 16+1, "%x 0x%06x", seg, (mem & 0x3FFF)); break; } case C166_EXT_MODE_PAGE: { @@ -398,6 +423,7 @@ static const char *c166_fmt_mem(const C166ExtState *ext, char *buf, ut16 mem) { snprintf(buf, 11, "0x%08x", page | (mem & 0x3FFF)); break; } + default:; } return buf; } @@ -476,8 +502,12 @@ static ut8 c166_instr_mov_mem_oRw(C166_Inst *instr) { } if (swap) { + // printf("pc: [0x%02x] - [0x%02x] 0x%08lx\n", + // instr->addr, instr->id, instr->d); OPERANDS(FMT2, c166_rw[n], c166_fmt_mem(&instr->ext, SBUF_16, mem)); } else { + // printf("pc: [0x%02x] - [0x%02x] 0x%08lx\n", + // instr->addr, instr->id, instr->d); OPERANDS(FMT0, c166_fmt_mem(&instr->ext, SBUF_16, mem), c166_rw[n]); } return C166_BYTESIZE_4; @@ -632,7 +662,7 @@ static ut8 c166_instr_rb_x(C166_Inst *instr) { static ut8 c166_instr_rw_rb(C166_Inst *instr) { const ut8 reg = get_operand(instr, 1); - ///< NOTE: It is D0 mn , NOT nm, but displayed as Rwn, Rbm + ///< NOTE: It is D0 mn, NOT nm, but displayed as Rwn, Rbm OPERANDS(FMT9, c166_rw[L_NIB(reg)], c166_rb[H_NIB(reg)]); return C166_BYTESIZE_2; } @@ -672,6 +702,8 @@ static ut8 c166_instr_rb(C166_Inst *instr) { static ut8 c166_instr_reg_mem(C166_Inst *instr, bool byte) { const ut8 reg = get_operand(instr, 1); const ut16 mem = rz_read_at_le16(&instr->d, 2); + // printf("pc: [0x%02x] - [0x%02x] 0x%08lx\n", + // instr->addr, instr->id, instr->d); OPERANDS(FMT9, c166_fmt_reg(&instr->ext, SBUF_16, reg, byte), c166_fmt_mem(&instr->ext, SBUF_16, mem)); @@ -682,6 +714,8 @@ static ut8 c166_instr_mem_reg(C166_Inst *instr, bool byte) { ///< f6 8e fcf0 F6 RR MM MM const ut8 reg = get_operand(instr, 1); const ut16 mem = rz_read_at_le16(&instr->d, 2); + // printf("pc: [0x%02x] - [0x%02x] 0x%08lx\n", + // instr->addr, instr->id, instr->d); OPERANDS(FMT9, c166_fmt_mem(&instr->ext, SBUF_16, mem), c166_fmt_reg(&instr->ext, SBUF_16, reg, byte)); @@ -781,6 +815,8 @@ static ut8 c166_instr_rw_data16(C166_Inst *instr) { static ut8 c166_instr_rw_mem(C166_Inst *instr) { const ut8 reg = get_operand(instr, 1); const ut16 data = rz_read_at_le16(&instr->d, 2); + // printf("pc: [0x%02x] - [0x%02x] 0x%08lx\n", + // instr->addr, instr->id, instr->d); OPERANDS("r%i, %s", L_NIB(reg), c166_fmt_mem(&instr->ext, SBUF_16, data)); return C166_BYTESIZE_4; @@ -794,8 +830,8 @@ static ut8 c166_instr_bitaddr_bitaddr(C166_Inst *instr) { const ut8 q = H_NIB(qz); const ut8 z = L_NIB(qz); OPERANDS("%s.%i, %s.%i", - c166_fmt_bitoff(&instr->ext, SBUF_16, qq), q, - c166_fmt_bitoff(&instr->ext, SBUF_16, zz), z); + c166_fmt_bitoff(&instr->ext, SBUF_16, zz), z, + c166_fmt_bitoff(&instr->ext, SBUF_16, qq), q); return C166_BYTESIZE_4; } @@ -821,74 +857,152 @@ static ut8 c166_instr_call_rel(C166_Inst *instr) { * Modes ATOMIC #irang2 D1 :00##-0 2 * Modes EXTR #irang2 D1 :10##-0 2 */ -static ut8 c166_instr_irang2(C166State *state, C166_Inst *instr) { +// static ut8 c166_instr_irang2(C166State *state, C166_Inst *instr) { +// const ut8 op = get_operand(instr, 1); +// const ut8 sub_op = (op >> 6) & 0b11; +// const ut8 irang2 = ((op >> 4) & 0b0011) + 1; +// +// if (sub_op == 0b00) { +// INSTR("%s", "atomic"); +// } else if (sub_op == 0b10) { +// const C166ExtState ex = (C166ExtState){ +// .esfr = true, +// .mode = C166_EXT_MODE_NONE, +// .value = (op & 3), +// .i = 0 +// }; +// c166_activate_ext(state, instr->addr, ex); +// INSTR("%s", "extr"); +// } else +// INSTR("%s", "invalid"); +// OPERANDS("#%x", irang2); +// return C166_BYTESIZE_2; +// } + +///< This modifies the ext state +// static ut8 c166_instr_rw_irang2(C166State *state, C166_Inst *instr) { +// const ut8 op = get_operand(instr, 1); +// +// INSTR("%s", c166_extx_names[(op >> 6) & 0b11]); +// const ut8 m = L_NIB(op); +// const ut8 irang2 = ((op >> 4) & 0b0011) + 1; +// const C166ExtState ex = (C166ExtState){ +// .esfr = true, +// // .mode = C166_EXT_MODE_NONE, +// .mode = C166_EXT_MODE_SEG, +// .value = m, +// .i = irang2 +// }; +// c166_activate_ext(state, instr->addr, ex); +// OPERANDS(FMT10, c166_rw[m], irang2); +// return C166_BYTESIZE_2; +// } + +static ut8 c166_instr_seg_or_pag_irang2(C166State *state, C166_Inst *instr) { const ut8 op = get_operand(instr, 1); const ut8 sub_op = (op >> 6) & 0b11; const ut8 irang2 = ((op >> 4) & 0b0011) + 1; - if (sub_op == 0b00) { - INSTR("%s", "atomic"); - } else if (sub_op == 0b10) { + // d c 0 9 + // 1101 1100 00 00 1001 + // D C :00 ##-m + // D 7 :00 ##-0 ss 00 + // ATOMIC #irang2 D1 :00##-0 2 + // EXTR #irang2 D1 :10##-0 2 + + // EXTS #seg , #irang2 D7 :00##-0 ss 00 4 + // EXTP #pag , #irang2 D7 :01##-0 pp 0:00pp 4 + // EXTSR #seg , #irang2 D7 :10##-0 ss 00 4 + // EXTPR #pag , #irang2 D7 :11##-0 pp 0:00pp 4 + + // EXTS Rwm , #irang2 DC :00##-m 2 + // EXTP Rwm , #irang2 DC :01##-m 2 + // EXTSR Rwm , #irang2 DC :10##-m 2 + // EXTPR Rwm , #irang2 DC :11##-m 2 + + /** + * Modes ATOMIC #irang2 D1 :00##-0 2 + * Modes EXTR #irang2 D1 :10##-0 2 + */ + if (instr->id == C166_ATOMIC_or_EXTR_irang2) { // D1 + if (sub_op == 0b00) { + const C166ExtState ex = (C166ExtState){ + .esfr = false, + .mode = C166_EXT_MODE_ATOMIC, + .value = 0, + .i = irang2 + }; + c166_activate_ext(state, instr->addr, ex); + INSTR("%s", "atomic"); + } else if (sub_op == 0b10) { + const C166ExtState ex = (C166ExtState){ + .esfr = true, + .mode = C166_EXT_MODE_NONE, + .value = 0, + .i = irang2 + }; + c166_activate_ext(state, instr->addr, ex); + INSTR("%s", "extr"); + } else { + INSTR("%s", "invalid"); + return C166_BYTESIZE_2; + } + OPERANDS("#%x", irang2); + return C166_BYTESIZE_2; + } + /** + * Modes EXTS Rwm , #irang2 DC :00##-m 2 + * Modes EXTP Rwm , #irang2 DC :01##-m 2 + * Modes EXTSR Rwm , #irang2 DC :10##-m 2 + * Modes EXTPR Rwm , #irang2 DC :11##-m 2 + */ + if (instr->id == C166_EXTP_or_EXTS_Rwm_irang2) { // DC + INSTR("%s", c166_extx_names[(op >> 6) & 0b11]); + const ut8 m = L_NIB(op); const C166ExtState ex = (C166ExtState){ .esfr = true, - .mode = C166_EXT_MODE_NONE, - .value = (op & 3), - .i = 0 + .mode = C166_EXT_MODE_REG, + // .mode = C166_EXT_MODE_SEG, + .value = m, + .i = irang2 }; c166_activate_ext(state, instr->addr, ex); - INSTR("%s", "extr"); - } else - INSTR("%s", "invalid"); - OPERANDS("#%x", irang2); - return C166_BYTESIZE_2; -} - -///< This modifies the ext state -static ut8 c166_instr_rw_irang2(C166State *state, C166_Inst *instr) { - const ut8 op = get_operand(instr, 1); - - INSTR("%s", c166_extx_names[(op >> 6) & 0b11]); - const ut8 m = L_NIB(op); - const ut8 irang2 = ((op >> 4) & 0b0011) + 1; - const C166ExtState ex = (C166ExtState){ - .esfr = true, - .mode = C166_EXT_MODE_NONE, - .value = 0, - .i = irang2 - }; - c166_activate_ext(state, instr->addr, ex); - OPERANDS(FMT10, c166_rw[m], irang2); - return C166_BYTESIZE_2; -} + OPERANDS(FMT10, c166_rw[m], irang2); + return C166_BYTESIZE_2; + } + /** + * Modes EXTS #seg , #irang2 D7 :00##-0 ss 00 4 + * Modes EXTP #pag , #irang2 D7 :01##-0 pp 0:00pp 4 + * Modes EXTSR #seg , #irang2 D7 :10##-0 ss 00 4 + * Modes EXTPR #pag , #irang2 D7 :11##-0 pp 0:00pp 4 + */ + if (instr->id == C166_EXTP_or_EXTS_pag10_or_seg8_irang2) { // 0xD7 + // const ut8 sub_op = (op >> 6) & 0b11; + INSTR("%s", c166_extx_names[sub_op]); -static ut8 c166_instr_seg_or_pag_irang2(C166State *state, C166_Inst *instr, ut16 data) { - const ut8 op = get_operand(instr, 1); - const ut8 sub_op = (op >> 6) & 0b11; + bool seg = (sub_op == 0b00) || (sub_op == 0b10); - INSTR("%s", c166_extx_names[sub_op]); + // const ut8 irang2 = ((op >> 4) & 0b0011) + 1; + const bool esfr = (op >> 7) & 1; - bool seg = (sub_op == 0b00) || (sub_op == 0b10); + ut16 data = rz_read_at_le16(&instr->d, 2); + C166ExtState new_state = { + .esfr = esfr, + .mode = seg ? C166_EXT_MODE_SEG : C166_EXT_MODE_PAGE, + .i = irang2, + .value = data & (seg ? 0xFF : 0x3FF) + }; + // ut16 value = data & (seg ? 0xFF : 0x3FF); + // new_state.value = data & (seg ? 0xFF : 0x3FF); + OPERANDS("#0x%04x, #%i", new_state.value, irang2); - const ut8 irang2 = ((op >> 4) & 0b0011) + 1; - const bool esfr = (op >> 7) & 1; - - C166ExtState new_state = { - .esfr = esfr, - .mode = seg ? C166_EXT_MODE_SEG : C166_EXT_MODE_PAGE, - .i = irang2, - .value = 0 - }; - - if (seg) { - new_state.value = data & 0xFF; - OPERANDS("#0x%04x, #%i", data & 0xFF, irang2); - } else { - new_state.value = data & 0x3FF; - OPERANDS("#0x%04x, #%i", data & 0x3FF, irang2); + c166_activate_ext(state, instr->addr, new_state); + return C166_BYTESIZE_4; } - - c166_activate_ext(state, instr->addr, new_state); - return 4; + printf("id: 0x%02x, addr: 0x%08x\n", instr->id, instr->addr); + rz_warn_if_reached(); + return C166_BYTESIZE_2; + // return C166_BYTESIZE_INVALID; } static ut8 c166_trap_instr(C166_Inst *instr) { @@ -896,7 +1010,7 @@ static ut8 c166_trap_instr(C166_Inst *instr) { const ut16 addr = 4 * (trap7 & 0x7F); INSTR("%s", "trap"); OPERANDS("#0x%04x", addr); - return 2; + return C166_BYTESIZE_2; } /** @@ -1177,35 +1291,35 @@ static const char *c166_instr_extended_name(C166_Inst *instr) { return "invalid"; } -static const char *CoREG(ut8 bits) { +static ut16 CoREG(ut8 bits) { switch (bits) { case 0b00000: { ///< MAC-Unit Status Word - return "0xffde"; + return 0xffde; } case 0b00001: { ///< MAC-Unit Accumulator High Word - return "0xfe5e"; + return 0xfe5e; } case 0b00010: { - ///< Limited MAC-Unit Accumulator High Word - return "MAS"; + ///< MAS - Limited MAC-Unit Accumulator High Word + return -1; ///< Not documented value } case 0b00100: { ///< MAC-Unit Accumulator Low Word - return "0xfe5c"; + return 0xfe5c; } case 0b00101: { ///< MAC-Unit Control Word - return "0xffdc"; + return 0xffdc; } case 0b00110: { ///< MAC-Unit Repeat Word - return "0xffda"; + return 0xffda; } default: RZ_LOG_INFO("Unknown bits: 0x%02x.\n", bits); - return NULL; + return -1; } } @@ -1218,27 +1332,27 @@ static const char *idx_formatter(char *buf, ut8 nm) { switch (idx_op) { case 0b010: { ///< IDX +2 - format = "[0x%04x +2]"; + format = "[0x%04x+]"; break; } case 0b011: { ///< IDX -2 - format = "[0x%04x -2]"; + format = "[0x%04x-]"; break; } case 0b100: { ///< IDX + QX0 - format = "[0x%04x + QX0]"; + format = "[0x%04x+QX0]"; break; } case 0b101: { ///< IDX - QX0 - format = "[0x%04x - QX0]"; + format = "[0x%04x-QX0]"; break; } case 0b110: { ///< IDX + QX1 - format = "[0x%04x + QX1]"; + format = "[0x%04x+QX1]"; break; } case 0b111: { ///< IDX - QX1 - format = "[0x%04x - QX1]"; + format = "[0x%04x-QX1]"; break; } case 0b000: ///< RESERVED @@ -1256,27 +1370,27 @@ static const char *qqq_formatter(char *buf, ut8 op, ut8 n) { const char *format = NULL; switch (q) { case 0b010: { ///< Rw +2 - format = "[r%i +2]"; + format = "[r%i+]"; break; } case 0b011: { ///< Rw -2 - format = "[r%i -2]"; + format = "[r%i-]"; break; } case 0b100: { ///< Rw + QR0 - format = "[r%i + QR0]"; + format = "[r%i+QR0]"; break; } case 0b101: { ///< Rw - QR0 - format = "[r%i - QR0]"; + format = "[r%i-QR0]"; break; } case 0b110: { ///< Rw + QR1 - format = "[r%i + QR1]"; + format = "[r%i+QR1]"; break; } case 0b111: { ///< Rw - QR1 - format = "[r%i - QR1]"; + format = "[r%i-QR1]"; break; } case 0b000: ///< RESERVED @@ -1316,7 +1430,7 @@ static ut8 c166_instr_extended(C166_Inst *instr) { ///< qqq : 3-bit addressing mode specifier for CoXXX instructions ///< ut8 rrr = opt2 >> 5; - const char *rrr = repeat_control(opt2); + const char *rpctl = repeat_control(opt2); const ut8 opcode = instr->id; const char *instruction_name = c166_instr_extended_name(instr); @@ -1324,7 +1438,7 @@ static ut8 c166_instr_extended(C166_Inst *instr) { goto err; } - INSTR("%s%s", rrr ? rrr : "", instruction_name); ///< `- USRx` repeat control label + INSTR("%s%s", rpctl ? rpctl : "", instruction_name); ///< `- USRx` repeat control label if (opcode == 0xD3) { ///< CoMOV [IDXi*], [Rwm*] @@ -1339,7 +1453,7 @@ static ut8 c166_instr_extended(C166_Inst *instr) { ///< CoSTORE [Rwn*], CoReg ///< B3 nn wwww:w000 rrr0:0qqq const ut8 wwwww = (extID >> 3); - OPERANDS("[r%i], %s", n, CoREG(wwwww)); + OPERANDS("%s, 0x%04x", qqq_formatter(SBUF_16, opt2, n), CoREG(wwwww)); goto end; } @@ -1347,17 +1461,17 @@ static ut8 c166_instr_extended(C166_Inst *instr) { ///< CoSTORE Rwn, CoReg ///< C3 nn wwww:w000 rrr0:0000 const ut8 wwwww = (extID >> 3); - OPERANDS("r%i, %s", n, CoREG(wwwww)); // CoSTORE RWn, CoReg + OPERANDS("r%i, 0x%04x", n, CoREG(wwwww)); // CoSTORE RWn, CoReg goto end; } if ((opcode == 0x83) && (extID == 0xAA)) { - OPERANDS("[r%i]", m); // CoASHR [RWm*] + OPERANDS("%s", qqq_formatter(SBUF_16, opt2, m)); // CoASHR [RWm*] goto end; } else if ((opcode == 0x83) && (extID == 0xBA)) { ///< CoASHR [Rwm*], rnd ///< 83 mm BA rrr0:0qqq - OPERANDS("[r%i], rnd", m); // CoASHR [RWm*], rnd + OPERANDS("%s, rnd", qqq_formatter(SBUF_16, opt2, m)); // CoASHR [RWm*], rnd goto end; } else if ((opcode == 0xA3) && (extID == 0xAA)) { OPERANDS("r%i", n); // CoASHR RWn @@ -1394,62 +1508,69 @@ static ut8 c166_instr_extended(C166_Inst *instr) { } else if ((opcode == 0xA3) && (extID == 0xB2)) { goto end; } else if ((opcode == 0x83) && (extID == 0x8A)) { - OPERANDS("[r%i]", m); // ????? CoSHL [RWm*] + OPERANDS("%s", qqq_formatter(SBUF_16, opt2, m)); // ????? CoSHL [RWm*] goto end; } else if ((opcode == 0xA3) && (extID == 0x8A)) { OPERANDS("r%i", n); goto end; } else if ((opcode == 0x83) && (extID == 0x9A)) { - OPERANDS("[r%i]", m); // ????? CoSHR [RWm*] + OPERANDS("%s", qqq_formatter(SBUF_16, opt2, m)); // ????? CoSHR [RWm*] goto end; } else if ((opcode == 0xA3) && (extID == 0x9A)) { OPERANDS("r%i", n); // CoSHR RWn goto end; } else if ((opcode == 0x93) && (L_NIB(extID) == 0x00)) { // CoXXX_oIDXi_oRWm(); - OPERANDS("%s, [r%i]", - idx_formatter(SBUF_16, nm), m); // CoXXX [IDXi*], [RWm*] + OPERANDS("%s, %s", + idx_formatter(SBUF_16, nm), + qqq_formatter(SBUF_16, opt2, m)); // CoXXX [IDXi*], [RWm*] goto end; } else if ((opcode == 0x93) && (L_NIB(extID) == 0x02)) { // CoXXX_RWn_oRWm(); - OPERANDS("%s, [r%i]", - idx_formatter(SBUF_16, nm), m); // CoXXX [IDXi*], [RWm*] + OPERANDS("%s, %s", + idx_formatter(SBUF_16, nm), + qqq_formatter(SBUF_16, opt2, m)); // CoXXX [IDXi*], [RWm*] goto end; } else if ((opcode == 0x93) && (L_NIB(extID) == 0x0A)) { // CoXXX_RWn_oRWm(); - OPERANDS("%s, [r%i]", - idx_formatter(SBUF_16, nm), m); // CoXXX [IDXi*], [RWm*] + OPERANDS("%s, %s", + idx_formatter(SBUF_16, nm), + qqq_formatter(SBUF_16, opt2, m)); // CoXXX [IDXi*], [RWm*] goto end; } else if ((opcode == 0x93) && (L_NIB(extID) == 0x08)) { // CoXXX_RWn_oRWm(); - OPERANDS("%s, [r%i]", - idx_formatter(SBUF_16, nm), m); // CoXXX [IDXi*], [RWm*] + OPERANDS("%s, %s", + idx_formatter(SBUF_16, nm), + qqq_formatter(SBUF_16, opt2, m)); // CoXXX [IDXi*], [RWm*] goto end; } else if ((opcode == 0x93) && (L_NIB(extID) == 0x09)) { // CoXXX_RWn_oRWm(); - OPERANDS("%s, [r%i], rnd", - idx_formatter(SBUF_16, nm), m); // CoXXX [IDXi*], [RWm*], rnd + OPERANDS("%s, %s, rnd", + idx_formatter(SBUF_16, nm), + qqq_formatter(SBUF_16, opt2, m)); // CoXXX [IDXi*], [RWm*], rnd goto end; } else if ((opcode == 0x93) && (L_NIB(extID) == 0x01)) { // CoXXX_RWn_oRWm(); - OPERANDS("%s, [r%i], rnd", - idx_formatter(SBUF_16, nm), m); // CoXXX [IDXi*], [RWm*], rnd + OPERANDS("%s, %s, rnd", + idx_formatter(SBUF_16, nm), + qqq_formatter(SBUF_16, opt2, m)); // CoXXX [IDXi*], [RWm*], rnd goto end; } else if ((opcode == 0x83) && (L_NIB(extID) == 0x00)) { // CoXXX_RWn_oRWm(); - OPERANDS("r%i, [r%i]", n, m); // CoXXX RWn, [RWm*] + OPERANDS("r%i, %s", n, qqq_formatter(SBUF_16, opt2, m)); // CoXXX RWn, [RWm*] goto end; } else if ((opcode == 0x83) && (L_NIB(extID) == 0x02)) { // CoXXX_RWn_oRWm(); - OPERANDS("r%i, [r%i]", n, m); // CoXXX RWn, [RWm*] + OPERANDS("r%i, %s]", n, qqq_formatter(SBUF_16, opt2, m)); // CoXXX RWn, [RWm*] goto end; } else if ((opcode == 0x83) && (L_NIB(extID) == 0x0A)) { // CoXXX_RWn_oRWm(); - OPERANDS("r%i, [r%i]", n, m); // CoXXX RWn, [RWm*] + OPERANDS("r%i, %s", n, qqq_formatter(SBUF_16, opt2, m)); // CoXXX RWn, [RWm*] goto end; } else if ((opcode == 0x83) && (L_NIB(extID) == 0x01)) { // CoMULu_RWn_oRWm_rnd(); - OPERANDS("r%i, [r%i], rnd", n, m); // CoXXX RWn, [RWm*], rnd + OPERANDS("r%i, %s, rnd", n, + qqq_formatter(SBUF_16, opt2, m)); // CoXXX RWn, [RWm*], rnd goto end; } else if (opcode == 0x83) { // CoMULu_RWn_oRWm(); @@ -1457,12 +1578,14 @@ static ut8 c166_instr_extended(C166_Inst *instr) { (extID == 0x48) || (extID == 0x88) || (extID == 0xC8)) { - OPERANDS("r%i, [r%i]", n, m); // CoXXX RWn, [RWm*] + OPERANDS("r%i, %s", n, + qqq_formatter(SBUF_16, opt2, m)); // CoXXX RWn, [RWm*] goto end; } } else if ((opcode == 0xA3) && (L_NIB(extID) == 0x01)) { // CoXXX_RWn_RWm_rnd(); - OPERANDS("r%i, r%i, rnd", n, m); // CoXXX RWn, [RWm*], rnd + OPERANDS("r%i, %s, rnd", n, + qqq_formatter(SBUF_16, opt2, m)); // CoXXX RWn, [RWm*], rnd goto end; } else if ((opcode == 0xA3) && (L_NIB(extID) == 0x00)) { // CoXXX_RWn_RWm(); @@ -1516,8 +1639,7 @@ RZ_IPI st32 c166_decode_command(RZ_NONNULL C166State *state, RZ_NONNULL C166_Ins const ut8 opcode = rz_read_le8(&instr->d); instr->id = opcode; instr->ext = state->ext; // Copy state - c166_maybe_deactivate_ext(state, instr->addr); - + // c166_maybe_deactivate_ext(state, instr->addr); switch (opcode) { case C166_ADD_Rwn_Rwm: case C166_ADDC_Rwn_Rwm: @@ -1686,11 +1808,17 @@ RZ_IPI st32 c166_decode_command(RZ_NONNULL C166State *state, RZ_NONNULL C166_Ins instr->byte_size = c166_instr_mov_nm(instr); break; case C166_ATOMIC_or_EXTR_irang2: - instr->byte_size = c166_instr_irang2(state, instr); - goto ok; + // instr->byte_size = c166_instr_irang2(state, instr); + // goto ok; case C166_EXTP_or_EXTS_Rwm_irang2: - instr->byte_size = c166_instr_rw_irang2(state, instr); + case C166_EXTP_or_EXTS_pag10_or_seg8_irang2: { + instr->byte_size = c166_instr_seg_or_pag_irang2( + state, instr); goto ok; + } + // // instr->byte_size = c166_instr_rw_irang2(state, instr); + // instr->byte_size = c166_instr_seg_or_pag_irang2(state, instr); + // goto ok; case C166_TRAP_trap7: instr->byte_size = c166_trap_instr(instr); goto ok; @@ -1817,10 +1945,6 @@ RZ_IPI st32 c166_decode_command(RZ_NONNULL C166State *state, RZ_NONNULL C166_Ins case C166_BFLDL_bitoff_x: instr->byte_size = c166_instr_bfld(instr); break; - case C166_EXTP_or_EXTS_pag10_or_seg8_irang2: { - instr->byte_size = c166_instr_seg_or_pag_irang2(state, instr, rz_read_at_le16(bytes, 2)); - goto ok; - } case C166_SBRK: case C166_NOP: case C166_RET: @@ -1828,13 +1952,13 @@ RZ_IPI st32 c166_decode_command(RZ_NONNULL C166State *state, RZ_NONNULL C166_Ins case C166_RETI: instr->byte_size = C166_BYTESIZE_2; break; - case C166_SRST: // B7 48 B7 B7 - case C166_IDLE: // 87 78 87 87 - case C166_PWRDN: // 97 68 97 97 - case C166_SRVWDT: // A7 58 A7 A7 - case C166_DISWDT: // A5 5A A5 A5 - case C166_EINIT: // B5 4A B5 B5 - case C166_ENWDT: // 85 7A 85 85 + case C166_SRST: ///< B7 48 B7 B7 + case C166_IDLE: ///< 87 78 87 87 + case C166_PWRDN: ///< 97 68 97 97 + case C166_SRVWDT: ///< A7 58 A7 A7 + case C166_DISWDT: ///< A5 5A A5 A5 + case C166_EINIT: ///< B5 4A B5 B5 + case C166_ENWDT: ///< 85 7A 85 85 instr->byte_size = C166_BYTESIZE_4; break; case C166_CoMOV: @@ -1863,8 +1987,9 @@ RZ_IPI st32 c166_decode_command(RZ_NONNULL C166State *state, RZ_NONNULL C166_Ins goto ok; } PRINT_INSTR; - if (instr->byte_size > len) + if (instr->byte_size > len) { INSTR("invalid"); + } ok: rz_buf_free(b); diff --git a/librz/arch/isa/c166/c166_disas.h b/librz/arch/isa/c166/c166_disas.h index ed43f2663ab..e3cda2f4fd5 100644 --- a/librz/arch/isa/c166/c166_disas.h +++ b/librz/arch/isa/c166/c166_disas.h @@ -6,12 +6,13 @@ #ifndef C166_DISAS_H #define C166_DISAS_H -#include #include +#include "c166/c166_common.h" #define C166_INSTR_MAXLEN (16 + 16) // ? #define C166_OPERANDS_MAXLEN 32 +#define C166_BYTESIZE_INVALID (-1) #define C166_BYTESIZE_2 2 #define C166_BYTESIZE_4 4 @@ -50,54 +51,6 @@ #define FMT9 "%s, %s" #define FMT10 "%s, #%i" -// Core Special Function Registers (CSFR) -#define BASE_GPR_ADDR 0xFE10 ///< Base address for calculate GPR phisical address (also REG_CP) -#define BASE_SFR_ADDR 0xFE00 ///< Base address for calculate SFR phisical address (also REG_DPP0) -#define BASE_ESFR_ADDR 0xF000 ///< Base address for calculate ESFR phisical address -#define BASE_RAM_B_ADDR 0xFD00 ///< Base address for calculate RAM phisical address (bit) -#define BASE_SFR_B_ADDR 0xFF00 ///< Base address for calculate SFR phisical address (bit) -#define BASE_ESFR_B_ADDR 0xF100 ///< Base address for calculate ESFR phisical address (bit) - -#define QX0 0xF000 ///< MAC Offset Register X0 (ESFRs) -#define QX1 0xF002 ///< MAC Offset Register X1 (ESFRs) -#define QR0 0xF004 ///< MAC Offset Register R0 (ESFRs) -#define QR1 0xF006 ///< MAC Offset Register R1 (ESFRs) -#define CPUID 0xF00C ///< CPU Identification Register (ESFRs) - -#define REG_PSW 0xFF10 ///< Processor Status Word - -#define REG_DPP0 (BASE_SFR_ADDR + 0x00) ///< CPU Data Page Pointer 0 Register (10 bits) -#define REG_DPP1 (BASE_SFR_ADDR + 0x02) ///< CPU Data Page Pointer 1 Register (10 bits) -#define REG_DPP2 (BASE_SFR_ADDR + 0x04) ///< CPU Data Page Pointer 2 Register (10 bits) -#define REG_DPP3 (BASE_SFR_ADDR + 0x06) ///< CPU Data Page Pointer 3 Register (10 bits) -#define REG_CSP (BASE_SFR_ADDR + 0x08) ///< Code Segment Pointer -#define REG_MDH (BASE_SFR_ADDR + 0x0c) ///< Multiply Divide High Word -#define REG_MDL (BASE_SFR_ADDR + 0x0e) ///< Multiply Divide Low Word -#define REG_CP (BASE_SFR_ADDR + 0x10) ///< CPU Context Pointer Register -#define REG_SP (BASE_SFR_ADDR + 0x12) ///< Stack Pointer Register -#define REG_STKOV (BASE_SFR_ADDR + 0x14) ///< Stack Overflow Pointer -#define REG_STKUN (BASE_SFR_ADDR + 0x16) ///< Stack Underflow Pointer -#define REG_CPUCON1 (BASE_SFR_ADDR + 0x18) ///< Core Control Register -#define REG_CPUCON2 (BASE_SFR_ADDR + 0x1A) ///< Core Control Register -#define REG_MAL (BASE_SFR_ADDR + 0x5C) ///< MAC Accumulator – Low Word -#define REG_MAH (BASE_SFR_ADDR + 0x5E) ///< MAC Accumulator – High Word - -#define IDX0 0xFF08 ///< Address Pointer IDX0 -#define IDX1 0xFF0A ///< Address Pointer IDX1 -#define SPSEG 0xFF0C ///< Stack Pointer Segment Register -#define MDC 0xFF0E ///< (Bit addressable) Multiply Divide Control Register -#define PSW 0xFF10 ///< (Bit addressable) Program Status Word -#define VECSEG 0xFF12 ///< (Bit addressable) Vector Table Segment Register -#define ZEROS 0xFF1C ///< (Bit addressable) Constant Value 0s Register (read only) -#define ONES 0xFF1E ///< (Bit addressable) Constant Value 1s Register (read only) -#define TFR 0xFFAC ///< (Bit addressable) Trap Flag Register -#define MRW 0xFFDA ///< (Bit addressable) MAC Repeat Word -#define MCW 0xFFDC ///< (Bit addressable) MAC Control Word -#define MSW 0xFFDE ///< (Bit addressable) MAC Status Word - -#define REG_ASC0_TIC 0xFF6C ///< Serial Channel 0 Transmit Interrupt Control Register -#define REG_ASC0_RIC 0xFF6E ///< Serial Channel 0 Receive Interrupt Control Register - #define SHORT_TO_LONG_ADDR(base, ind) ((base) + (2 * (ind))) ///< [0..15] -> 0xFXXX #define REG_R(n) SHORT_TO_LONG_ADDR(BASE_GPR_ADDR, n) @@ -142,21 +95,21 @@ TCONCS6 EQU 0EE40H TCONCS7 EQU 0EE48H WDTCON DEFR 0FFAEH */ -static inline bool IS_GPR(ut8 addr) { - return addr >= 0xF0 && addr <= 0xFF; -} - -static inline bool IS_RAM(ut8 addr) { - return addr <= 0x7F; -} - -static inline bool IS_rSFR(ut8 addr) { - return addr <= 0xEF; -} - -static inline bool IS_bSFR(ut8 addr) { - return addr >= 0x80 && addr <= 0xEF; -} +// static inline bool IS_GPR(ut8 addr) { +// return addr >= 0xF0 && addr <= 0xFF; +// } +// +// static inline bool IS_RAM(ut8 addr) { +// return addr <= 0x7F; +// } +// +// static inline bool IS_rSFR(ut8 addr) { +// return addr <= 0xEF; +// } +// +// static inline bool IS_bSFR(ut8 addr) { +// return addr >= 0x80 && addr <= 0xEF; +// } #define R_IP (op->addr) #define NEXT_ADDR (R_IP + op->size) @@ -647,119 +600,6 @@ typedef enum { C166_BSET_bitoff15 = 0xFF, ///< [0xFF] Set direct bit (x.15) (2 bytes) } c166_opcodes; -/*! - * \brief C166 Branch Condition Codes - * - * Defines condition codes used for conditional branching instructions - * Datasheet page 39 - * (*) Only usable with the JMPA and CALLA instructions - */ -// clang-format off -typedef enum { - C166_CC_UC = 0x00, ///< CCNc = 0x00; [0D] Unconditional - C166_CC_NET = 0x02, ///< CCNc = 0x01; [1D] Not equal AND not end of table - // C166_CC_Z = 0x04, ///< CCNc = 0x02; [2D] Zero - C166_CC_EQ = 0x04, ///< CCNc = 0x02; [2D] Equal - // C166_CC_NZ = 0x06, ///< CCNc = 0x03; [3D] Not zero - C166_CC_NE = 0x06, ///< CCNc = 0x03; [3D] Not equal - C166_CC_V = 0x08, ///< CCNc = 0x04; [4D] Overflow - C166_CC_NV = 0x0A, ///< CCNc = 0x05; [5D] No overflow - C166_CC_N = 0x0C, ///< CCNc = 0x06; [6D] Negative - C166_CC_NN = 0x0E, ///< CCNc = 0x07; [7D] Not negative - C166_CC_C = 0x10, ///< CCNc = 0x08; [8D] Carry - // C166_CC_ULT = 0x10, ///< CCNc = 0x08; [8D] Unsigned less than - C166_CC_NC = 0x12, ///< CCNc = 0x09; [9D] No carry - // C166_CC_UGE = 0x12, ///< CCNc = 0x09; [9D] Unsigned greater than or equal - C166_CC_SGT = 0x14, ///< CCNc = 0x0A; [AD] Signed greater than - C166_CC_SLE = 0x16, ///< CCNc = 0x0B; [BD] Signed less than or equal - C166_CC_SLT = 0x18, ///< CCNc = 0x0C; [CD] Signed less than - C166_CC_SGE = 0x1A, ///< CCNc = 0x0D; [DD] Signed greater than or equal - C166_CC_UGT = 0x1C, ///< CCNc = 0x0E; [ED] Unsigned greater than - C166_CC_ULE = 0x1E, ///< CCNc = 0x0F; [FD] Unsigned less than or equal - - C166_CC_NUSR0 = 0x01, ///< USR-bit 0 is cleared (*) - C166_CC_NUSR1 = 0x03, ///< USR-bit 1 is cleared (*) - C166_CC_USR0 = 0x05, ///< USR-bit 0 is set 1 - C166_CC_USR1 = 0x07 ///< USR-bit 1 is set 1 -} C166CondCode; - -const char *c166_rw[] = { - "r0", "r1", "r2", "r3", - "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", - "r12", "r13", "r14", "r15", -}; - -const char *c166_rb[] = { - "rl0", "rh0", - "rl1", "rh1", - "rl2", "rh2", - "rl3", "rh3", - "rl4", "rh4", - "rl5", "rh5", - "rl6", "rh6", - "rl7", "rh7", -}; - -/** - * Maps hexcodes to condition codes for JMPR instructions - * Used to determine the condition code for conditional jump instructions - */ -// C166 condition code names -static const char *conds_names[] = { - [C166_CC_UC] = "cc_UC", ///< Unconditional - [C166_CC_V] = "cc_V", ///< Overflow - [C166_CC_NV] = "cc_NV", ///< No Overflow - [C166_CC_N] = "cc_N", ///< Negative - [C166_CC_NN] = "cc_NN", ///< Not Negative - [C166_CC_C] = "cc_C/ULT", ///< Carry - [C166_CC_NC] = "cc_NC/UGE", ///< No Carry - [C166_CC_EQ] = "cc_Z/EQ", ///< Equal - [C166_CC_NE] = "cc_NZ/NE", ///< Not Equal - [C166_CC_ULE] = "cc_ULE", ///< Unsigned Less Than or Equal - [C166_CC_UGT] = "cc_UGT", ///< Unsigned Greater Than - [C166_CC_SLE] = "cc_SLE", ///< Signed Less Than or Equal - [C166_CC_SGE] = "cc_SGE", ///< Signed Greater Than or Equal - [C166_CC_SGT] = "cc_SGT", ///< Signed Greater Than - [C166_CC_NET] = "cc_NET", ///< Not Equal and Not End-of-Table - - [C166_CC_SLT] = "cc_SLT", ///< Signed Less Than - - [C166_CC_NUSR0] = "cc_NUSR0", ///< USR-bit 0 is cleared (*) - [C166_CC_NUSR1] = "cc_NUSR1", ///< USR-bit 1 is cleared (*) - [C166_CC_USR0] = "cc_USR0", ///< USR-bit 0 is set 1 - [C166_CC_USR1] = "cc_USR1" ///< USR-bit 1 is set 1 -}; -// clang-format on - -static const char *conds(ut8 cc) { - return conds_names[cc << 1]; -} -static const char *conds_extended(ut8 cc) { - return conds_names[cc]; -} - -typedef enum { - C166_EXT_MODE_NONE, - C166_EXT_MODE_PAGE, - C166_EXT_MODE_SEG, -} C166ExtMode; - -// clang-format off -typedef struct { - bool esfr; ///< Extended register sequence active - C166ExtMode mode; ///< Extended page/seq mode - ut8 i; ///< Number of unstructions remaining until state exits - ut16 value; ///< Value of ext -} C166ExtState; - -typedef struct { - ut32 last_addr; ///< State of last addr dissassembled - C166ExtState ext; - RzPVector /**/ *token_patterns; -} C166State; -// clang-format on - typedef struct { ut64 d; ut32 imm; @@ -787,5 +627,7 @@ static inline ut16 get_operand(const C166_Inst *i, const ut8 index) { } RZ_IPI st32 c166_decode_command(RZ_NONNULL C166State *state, RZ_NONNULL C166_Inst *instr, RZ_NONNULL const ut8 *bytes, st32 len); +RZ_API void c166_maybe_deactivate_ext(RZ_NONNULL C166State *state, ut32 addr); static bool check_unused_opcode(ut8 opcode); +static ut16 CoREG(ut8 bits); #endif /* C166_DISAS_H */ diff --git a/librz/arch/isa/c166/c166_il.c b/librz/arch/isa/c166/c166_il.c new file mode 100644 index 00000000000..0f800ed3205 --- /dev/null +++ b/librz/arch/isa/c166/c166_il.c @@ -0,0 +1,1470 @@ +// SPDX-FileCopyrightText: 2026 Sergey Sharshunov +// SPDX-License-Identifier: LGPL-3.0-only + +#include "c166/c166_il.h" +#include "c166_common.h" + +/** + * All registers available as global IL variables + */ +static const char *c166_global_registers[] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10", "r11", "r12", "r13", "r14", "r15", + // "rl5", + "IP", + "DPP0", "DPP1", "DPP2", "DPP3", + // "SP", + // "STKUN", + "CSP", "SGTDIS", //"CP", + "e", "z", "v", "c", "n", // "pc", + // "STKOV", "", + "BUSCON0", "SYSCON", + NULL +}; + +#include + +typedef RzILOpEffect *(*c166_il_op)(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op); + +RzILOpEffect *mov_flags_seq(RzILOpBitVector *data) { + RzILOpEffect *e = SETG("e", ITE(EQ(DUP(data), S16(0x8000)), IL_TRUE, IL_FALSE)); + RzILOpEffect *z = SETG("z", ITE(IS_ZERO(DUP(data)), IL_TRUE, IL_FALSE)); + RzILOpEffect *n = SETG("n", MSB(DUP(data))); + return SEQ3(e, z, n); +} + +RzILOpEffect *bfld_flags_seq(RzILOpBitVector *result) { + RzILOpEffect *e = SETG("e", IL_FALSE); + RzILOpEffect *z = SETG("z", ITE(IS_ZERO(DUP(result)), IL_TRUE, IL_FALSE)); + RzILOpEffect *v = SETG("v", IL_FALSE); + RzILOpEffect *c = SETG("c", IL_FALSE); + RzILOpEffect *n = SETG("n", MSB(DUP(result))); + return SEQ5(e, z, v, c, n); +} +static RzILOpEffect *c166_il_unk(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_unk\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_add_rwn_rwm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_add_rwn_rwm\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_bclr_bitoff4(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bclr_bitoff4\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_bset_bitoff4(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bset_bitoff4\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_xorb_rbn_rbm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_xorb_rbn_rbm\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_xor_reg_mem(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_xor_reg_mem\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_shl_rwn_data4(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_shl_rwn_data4\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_div_rwn(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_div_rwn\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_cmpb_rbn_rbm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cmpb_rbn_rbm\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_cmp_reg_mem(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cmp_reg_mem\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_cmpb_reg_mem(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cmpb_reg_mem\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_cmp_reg_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cmp_reg_data16\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_cmpb_reg_data8(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cmpb_reg_data8\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_cmp_rwn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cmp_rwn_x\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_cmpb_rbn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cmpb_rbn_x\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_mov_rwn_orwm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_rwn_orwm\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +/** + * (count) ← 0 + * DO WHILE ((count) <8) + * IF op2[(count)] = 1 + * (op1[(count)]) ← op3[(count)] + * ENDIF + * (count) ← (count) + 1 + * END WHILE + * + */ +static RzILOpEffect *c166_il_bfldl_bitoff_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 bitoff = buf[1]; + const ut8 mask8 = buf[2]; // #mask8 ## + const ut8 data8 = buf[3]; // #data8 @@ + if (IS_GPR(bitoff)) { + RzILOpPure *dst = VARG(c166_rw[L_NIB(bitoff)]); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bfldl_bitoff_x %s, #0x%02x, #0x%02x\n", + op->id, pc, IP, + c166_rw[L_NIB(bitoff)], buf[2], buf[3]); + (void)dst; + } + if (IS_RAM(bitoff)) { + const ut16 addr = BASE_RAM_B_ADDR + (2 * bitoff); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bfldl_bitoff_x ram 0x%04x, #0x%02x, #0x%02x\n", + op->id, pc, IP, + addr, buf[2], buf[3]); + RzILOpBitVector *load = LOAD(U16(addr)); + RzILOpEffect *bfld = STORE(U16(addr), load); + return SEQ2(bfld_flags_seq(load), bfld); + } + if (IS_bSFR(bitoff)) { + C166State *state = (C166State *)analysis->plugin_data; + if (!state) { + RZ_LOG_FATAL("C166State was NULL."); + } + const ut16 base_addr = state->ext.esfr ? BASE_ESFR_B_ADDR : BASE_SFR_B_ADDR; + const ut16 addr = base_addr + (2 * (bitoff & 0x7F)); + RzPlatformTarget *arch_target = rz_analysis_get_arch_target(analysis); + const char *resolved = rz_platform_profile_resolve_mmio(arch_target->profile, addr); + if (!resolved) { + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bfldl_bitoff_x bSFR unk 0x%04x, #0x%02x, #0x%02x\n", + op->id, pc, IP, + addr, buf[2], buf[3]); + return rz_il_op_new_nop(); + } + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bfldl_bitoff_x bSFR %s, #0x%02x, #0x%02x\n", + op->id, pc, IP, + resolved, buf[2], buf[3]); + + RzILOpBitVector *val = UNSIGNED(16, DUP(LOGAND(U8(data8), U8(mask8)))); + RzILOpPure *src = VARG(resolved); + RzILOpBitVector *result = LOGOR(src, val); + RzILOpEffect *bfld = SETG(resolved, result); + return SEQ2(bfld_flags_seq(result), bfld); + } + + return bfld_flags_seq(U16(buf[3])); +} +static RzILOpEffect *c166_il_bfldh_bitoff_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 bitoff = buf[1]; + const ut8 mask8 = buf[3]; // #mask8 ## + const ut8 data8 = buf[2]; // #data8 @@ + // ut16 addr = 0; + if (IS_GPR(bitoff)) { + RzILOpPure *dst = VARG(c166_rw[L_NIB(bitoff)]); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bfldh_bitoff_x %s, #0x%02x, #0x%02x\n", + op->id, pc, IP, + c166_rw[L_NIB(bitoff)], buf[3], buf[2]); + (void)dst; + + } + if (IS_RAM(bitoff)) { + const ut16 addr = BASE_RAM_B_ADDR + (2 * bitoff); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bfldh_bitoff_x ram 0x%04x, #0x%02x, #0x%02x\n", + op->id, pc, IP, + addr, buf[3], buf[2]); + } + if (IS_bSFR(bitoff)) { + C166State *state = (C166State *)analysis->plugin_data; + if (!state) { + RZ_LOG_FATAL("C166State was NULL."); + } + const ut16 base_addr = state->ext.esfr ? BASE_ESFR_B_ADDR : BASE_SFR_B_ADDR; + const ut16 addr = base_addr + (2 * (bitoff & 0x7F)); + RzPlatformTarget *arch_target = rz_analysis_get_arch_target(analysis); + const char *resolved = rz_platform_profile_resolve_mmio(arch_target->profile, addr); + if (!resolved) { + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bfldh_bitoff_x bSFR unk 0x%04x, #0x%02x, #0x%02x\n", + op->id, pc, IP, + addr, buf[3], buf[2]); + return rz_il_op_new_nop(); + } + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bfldh_bitoff_x bSFR %s, #0x%02x, #0x%02x\n", + op->id, pc, IP, + resolved, buf[3], buf[2]); + + + RzILOpBitVector *mask = U16(~(mask8 << 8)); + RzILOpBitVector *tval = LOGAND(VARG(resolved), DUP(mask)); + RzILOpBitVector *tval2 = LOGAND(U16(data8 << 8), DUP(mask)); + RzILOpBitVector *result = LOGOR(tval, tval2); + RzILOpEffect *bfld = SETG(resolved, result); + return SEQ2(bfld_flags_seq(result), bfld); + } + return bfld_flags_seq(U16(buf[3])); +} +static RzILOpEffect *c166_il_movb_rbn_oRwm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_rbn_oRwm\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_jnb_bitaddr_rel(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_jnb_bitaddr_rel\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_and_reg_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_and_reg_data16\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_jb_bitaddr_rel(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_jb_bitaddr_rel\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +static RzILOpEffect *c166_il_or_reg_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_or_reg_data16\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_or_rwn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_or_rwn_x\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_orb_rbn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_orb_rbn_x\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_bmovn_bitaddr_bitaddr(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bmovn_bitaddr_bitaddr\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_cmp_rwn_rwm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cmp_rwn_rwm\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_addc_rwn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_addc_rwn_x\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_sub_rwn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_sub_rwn_x\n", op->id, pc, IP); + // if (pc == 0x98) exit(0); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_subb_rbn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_subb_rbn_x\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_sub_reg_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_sub_reg_data16\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_movb_orwm_rbn(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + C166State *state = (C166State *)analysis->plugin_data; + if (!state) { + RZ_LOG_FATAL("C166State was NULL."); + } + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + if (state->ext.esfr && state->ext.mode == C166_EXT_MODE_REG) { + const char *ext_reg_name = c166_global_registers[state->ext.value]; + + const ut8 reg = buf[1]; + const char *src = c166_rw[L_NIB(reg)]; + const char *dst = c166_rb[H_NIB(reg)]; + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_orwm_rbn [%s], %s (esfr: %s)\n", + op->id, pc, IP, src, dst, + state->ext.esfr ? "true" : "false"); + // RzILOpPure *addr = VARG(src); + RzILOpBitVector *seg = UNSIGNED(32, VARG(ext_reg_name)); + seg = SHIFTL0(seg, U16(16)); + RzILOpBitVector *addr = LOGOR(seg, UNSIGNED(32, VARG(src))); + // RzILOpBitVector *addr = UNSIGNED(32, VARG(src)); + RzILOpBitVector *load = LOADW(16, addr); + // RzILOpBitVector *load = BSWAP16(LOADW(16, addr)); + // RzILOpEffect *mov = SETG(dst, addr); + RzILOpEffect *mov = SETG(dst, UNSIGNED(16, load)); + RzILOpBitVector *add = ADD(VARG(src), U16(2)); + RzILOpEffect *inc = SETG(src, add); + return SEQ3(mov_flags_seq(load), mov, inc); + } + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_orwm_rbn\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_movbz_rwn_rbm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movbz_rwn_rbm\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_mov_orwm_data16_rwn(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_orwm_data16_rwn\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_bclr_bitoff11(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bclr_bitoff11\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_bset_bitoff11(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bset_bitoff11\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_mov_orwm_rwn(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_orwm_rwn\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_cpl_rwn(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_cpl_rwn\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_shr_rwn_data4(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_shr_rwn_data4\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_mov_norwm_rwn(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_norwm_rwn\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_and_rwn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_and_rwn_x\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_divl_rwn(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_divl_rwn\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_shl_rwn_rwm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_shl_rwn_rwm\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_bclr_bitoff0(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bclr_bitoff0\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_bset_bitoff0(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bset_bitoff0\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_addc_reg_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_addc_reg_data16\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_add_rwn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_add_rwn_x\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_addb_rbn_x(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_addb_rbn_x\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_add_reg_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_add_reg_data16\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_addb_reg_data8(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_addb_reg_data8\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_rets(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_rets\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_extp_or_exts_rwm_irang2(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + // INSTR("%s", c166_extx_names[(op >> 6) & 0b11]); + const ut8 op1 = buf[1]; + C166State *state = (C166State *)analysis->plugin_data; + if (!state) { + RZ_LOG_FATAL("C166State was NULL."); + } + // const ut8 m = L_NIB(op1); + // const ut8 irang2 = ((op1 >> 4) & 0b0011) + 1; + const ut8 m = state->ext.value; + const ut8 irang2 = state->ext.i; + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_%s %s, #%i (esfr: %s)\n", + op->id, pc, IP, + c166_extx_names[(op1 >> 6) & 0b11], + c166_rw[m], + irang2, + state->ext.esfr ? "true" : "false"); + // if (pc == 0x86) exit(0); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_jmpr_cc_sge_rel(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_jmpr_cc_sge_rel\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_bset_bitoff6(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bset_bitoff6\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// RzILOpEffect *or_flags_seq(const char *src, const char *dst) { +// +// return ; +// } + +static RzILOpEffect *c166_il_or_rwn_rwm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 reg = buf[1]; + const ut8 op1 = H_NIB(reg); + const ut8 op2 = L_NIB(reg); + const char *src = c166_global_registers[op2]; + const char *dst = c166_global_registers[op1]; + // printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_rwn_rwm r%i, r%i\n", + // op->id, pc, IP, H_NIB(reg), L_NIB(reg)); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_or_rwn_rwm r%i, r%i\n", + op->id, pc, IP, op1, op2); + RzILOpPure *d = VARG(dst); + RzILOpBitVector *res = LOGOR(d, VARG(src)); + RzILOpEffect *or = SETG(dst, res); + + RzILOpEffect *e = SETG("e", ITE(EQ(DUP(d), S16(0x8000)), IL_TRUE, IL_FALSE)); + // RzILOpEffect *e = SETG("e", ITE(IS_ZERO(S16(op2)), IL_TRUE, IL_FALSE)); + RzILOpEffect *z = SETG("z", ITE(IS_ZERO(U16(op2)), IL_TRUE, IL_FALSE)); + RzILOpEffect *v = SETG("v", IL_FALSE); + RzILOpEffect *c = SETG("c", IL_FALSE); + RzILOpEffect *n = SETG("n", MSB(DUP(res))); + + RzILOpEffect *or_flags_seq = SEQ5(e, z, v, c, n); + return SEQ2(or_flags_seq, or); +} + +static RzILOpEffect *c166_il_push_reg(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_push_reg\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_jmpr_cc_ugt_rel(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_jmpr_cc_ugt_rel\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_movb_rbn_rbm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_rbn_rbm\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_movb_reg_mem(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_reg_mem\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_bset_bitoff1(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bset_bitoff1\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_sub_rwn_rwm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_sub_rwn_rwm\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_einit(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_einit\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +static RzILOpEffect *c166_il_movb_rbn_orwm_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_rbn_orwm_data16\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +static RzILOpEffect *c166_il_mov_mem_reg(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_mem_reg\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_movb_mem_reg(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_mem_reg\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +static RzILOpEffect *c166_il_movb_orwm_data16_rbn(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_orwm_data16_rbn\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +static RzILOpEffect *c166_il_mov_rwn_rwm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 reg = buf[1]; + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_rwn_rwm r%i, r%i\n", + op->id, pc, IP, H_NIB(reg), L_NIB(reg)); + RzILOpEffect *mov = SETG(c166_global_registers[H_NIB(reg)], VARG(c166_global_registers[L_NIB(reg)])); + if (pc == 0x6a) exit(0); + return SEQ2(mov_flags_seq(VARG(c166_global_registers[L_NIB(reg)])), mov); +} + +static RzILOpEffect *c166_il_mov_rwn_orwmp(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + // const ut8 m = L_NIB(op1); + // const ut8 irang2 = ((op1 >> 4) & 0b0011) + 1; + + C166State *state = (C166State *)analysis->plugin_data; + if (!state) { + RZ_LOG_FATAL("C166State was NULL."); + } + // ut8 irang2 = 0; // ((op1 >> 4) & 0b0011) + 1; + if (state->ext.esfr && state->ext.mode == C166_EXT_MODE_REG) { + const char *ext_reg_name = c166_global_registers[state->ext.value]; + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 reg = buf[1]; + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_rwn_orwmp r%i, [r%i+] (esfr: %s)\n", + op->id, pc, IP, H_NIB(reg), L_NIB(reg), + state->ext.esfr ? "true" : "false"); + const char *src = c166_global_registers[L_NIB(reg)]; + const char *dst = c166_global_registers[H_NIB(reg)]; + // RzILOpPure *addr = VARG(src); + RzILOpBitVector *seg = UNSIGNED(32, VARG(ext_reg_name)); + seg = SHIFTL0(seg, U16(16)); + RzILOpBitVector *addr = LOGOR(seg, UNSIGNED(32, VARG(src))); + // RzILOpBitVector *addr = UNSIGNED(32, VARG(src)); + RzILOpBitVector *load = LOADW(16, addr); + // RzILOpBitVector *load = BSWAP16(LOADW(16, addr)); + // RzILOpEffect *mov = SETG(dst, addr); + RzILOpEffect *mov = SETG(dst, UNSIGNED(16, load)); + RzILOpBitVector *add = ADD(VARG(src), U16(2)); + RzILOpEffect *inc = SETG(src, add); + return SEQ3(mov_flags_seq(load), mov, inc); + } + + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 reg = buf[1]; + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_rwn_orwmp r%i, [r%i+] (esfr: %s)\n", + op->id, pc, IP, H_NIB(reg), L_NIB(reg), + state->ext.esfr ? "true" : "false"); + const char *src = c166_global_registers[L_NIB(reg)]; + const char *dst = c166_global_registers[H_NIB(reg)]; + // RzILOpPure *addr = VARG(src); + RzILOpBitVector *addr = UNSIGNED(32, VARG(src)); + RzILOpBitVector *load = LOAD(addr); + // RzILOpEffect *mov = SETG(dst, addr); + RzILOpEffect *mov = SETG(dst, UNSIGNED(16, load)); + RzILOpBitVector *add = ADD(VARG(src), U16(2)); + RzILOpEffect *inc = SETG(src, add); + return SEQ3(mov_flags_seq(VARG(c166_global_registers[L_NIB(reg)])), mov, inc); +} + +static RzILOpEffect *c166_il_mov_rwn_data4(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 reg = L_NIB(buf[1]); + const ut8 data = H_NIB(buf[1]); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_rwn_data4 r%i, #0x%02x\n", + op->id, pc, IP, reg, data); + RzILOpEffect *mov = SETG(c166_global_registers[reg], U16(data)); + return SEQ2(mov_flags_seq(VARG(c166_global_registers[L_NIB(reg)])), mov); +} + +static RzILOpEffect *c166_il_mov_reg_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut16 data = rz_read_at_le16(buf, 2); + const ut8 reg = buf[1]; + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_reg_data16 0x%02x 0x%04x\n", + op->id, pc, IP, reg, data); + +#ifdef C166_DUPLICATE_REG_OPERATIONS +// const ut8 SGTDIS = (ut8)rz_reg_getv(analysis->reg, "SGTDIS"); +// if (SGTDIS == 0) { +// rz_reg_setv(analysis->reg, "CSP", seg); +// } +// // rz_reg_setv(analysis->reg, "IP", (((ut32)seg) << 16) | caddr); + // rz_reg_setv(analysis->reg, c166_global_registers[L_NIB(reg)], (ut32)data); +#endif + + if (IS_GPR(reg)) { +#ifdef C166_DUPLICATE_REG_OPERATIONS + rz_reg_setv(analysis->reg, c166_global_registers[L_NIB(reg)], (ut32)data); + // printf("r 0x%lx, (0x%x) ret: 0x%lx [0x%lx]\n", + // rz_reg_getv(analysis->reg, c166_global_registers[L_NIB(reg)]), + // data, + // rz_reg_setv(analysis->reg, c166_global_registers[L_NIB(reg)], (ut32)data), + // rz_reg_getv(analysis->reg, c166_global_registers[L_NIB(reg)])); + // { + // ut64 xxxx = rz_reg_getv(analysis->reg, c166_global_registers[L_NIB(reg)]); + // // printf("%s 0x%lx\n", c166_global_registers[L_NIB(reg)], xxxx); + // } +#endif + return SEQ2( + mov_flags_seq(U16(data)), + SETG(c166_global_registers[L_NIB(reg)], U16(data)) + ); + } + + const ut16 base_addr = 0xfe00; //BASE_SFR_ADDR; + const ut16 addr = base_addr + (2 * reg); + + RzPlatformTarget *arch_target = rz_analysis_get_arch_target(analysis); + const char *resolved = rz_platform_profile_resolve_mmio(arch_target->profile, addr); + if (resolved) { + switch (addr) { + case 0xfe14: ///< "STKOV" +#ifdef C166_DUPLICATE_REG_OPERATIONS + rz_reg_setv(analysis->reg, "r2", (ut32)data); + // printf("STKOV 0x%lx, (0x%x) ret: 0x%lx [0x%lx]\n", + // rz_reg_getv(analysis->reg, "STKOV"), + // data, + // rz_reg_setv(analysis->reg, "STKOV", (ut64)data), + // rz_reg_getv(analysis->reg, "STKOV")); + // { + // ut64 xxxx = rz_reg_getv(analysis->reg, "STKOV"); + // printf("STKOV 0x%lx\n", xxxx); + // } +#endif + return SEQ2( + mov_flags_seq(U16(data)), + SETG("r2", U16(data)) + ); + // return SETG("r2", U16(data)); + // return NOP(); + // return SETG("r2", U16(data)); + case 0xfe10: ///< "CP" +#ifdef C166_DUPLICATE_REG_OPERATIONS + rz_reg_setv(analysis->reg, "r0", (ut32)data); + // printf("CP 0x%lx, (0x%x) ret: 0x%lx [0x%lx]\n", + // rz_reg_getv(analysis->reg, "CP"), + // data, + // rz_reg_setv(analysis->reg, "CP", (ut32)data), + // rz_reg_getv(analysis->reg, "CP")); + // { + // ut64 xxxx = rz_reg_getv(analysis->reg, "CP"); + // printf("CP 0x%lx\n", xxxx); + // } +#endif + return SEQ2( + mov_flags_seq(U16(data)), + SETG("r0", U16(data)) + ); + // return SETG("r0", U16(data)); + case 0xfe00: ///< "DPP0" +#ifdef C166_DUPLICATE_REG_OPERATIONS + rz_reg_setv(analysis->reg, "DPP0", (ut32)data); + // printf("DPP0 0x%lx, (0x%x) ret: 0x%lx [0x%lx]\n", + // rz_reg_getv(analysis->reg, "DPP0"), + // data, + // rz_reg_setv(analysis->reg, "DPP0", (ut32)data), + // rz_reg_getv(analysis->reg, "DPP0")); + // { + // ut64 xxxx = rz_reg_getv(analysis->reg, "DPP0"); + // printf("DPP0 0x%lx\n", xxxx); + // } +#endif + return SEQ2( + mov_flags_seq(U16(data)), + SETG("DPP0", UN(10, data)) + ); + case 0xfe02: ///< "DPP1" +#ifdef C166_DUPLICATE_REG_OPERATIONS + rz_reg_setv(analysis->reg, "DPP1", (ut32)data); + // printf("DPP1 0x%lx, (0x%x) ret: 0x%lx [0x%lx]\n", + // rz_reg_getv(analysis->reg, "DPP1"), + // data, + // rz_reg_setv(analysis->reg, "DPP1", (ut32)data), + // rz_reg_getv(analysis->reg, "DPP1")); + // { + // ut64 xxxx = rz_reg_getv(analysis->reg, "DPP0"); + // printf("DPP0 0x%lx\n", xxxx); + // } +#endif + return SEQ2( + mov_flags_seq(U16(data)), + SETG("DPP1", UN(10, data)) + ); + // return SETG("DPP1", U16(data)); + case 0xfe04: ///< "DPP2" +#ifdef C166_DUPLICATE_REG_OPERATIONS + rz_reg_setv(analysis->reg, "DPP2", (ut32)data); + // printf("DPP2 0x%lx, (0x%x) ret: 0x%lx [0x%lx]\n", + // rz_reg_getv(analysis->reg, "DPP2"), + // data, + // rz_reg_setv(analysis->reg, "DPP2", (ut32)data), + // rz_reg_getv(analysis->reg, "DPP2")); + // { + // ut64 xxxx = rz_reg_getv(analysis->reg, "DPP2"); + // printf("DPP2 0x%lx\n", xxxx); + // } +#endif + return SEQ2( + mov_flags_seq(U16(data)), + SETG("DPP2", UN(10, data)) + ); + // return SETG("DPP2", U16(data)); + case 0xfe06: ///< "DPP3" +#ifdef C166_DUPLICATE_REG_OPERATIONS + rz_reg_setv(analysis->reg, "DPP3", (ut32)data); + // printf("DPP3 0x%lx, (0x%x) ret: 0x%lx [0x%lx]\n", + // rz_reg_getv(analysis->reg, "DPP3"), + // data, + // rz_reg_setv(analysis->reg, "DPP3", (ut32)data), + // rz_reg_getv(analysis->reg, "DPP3")); + // { + // ut64 xxxx = rz_reg_getv(analysis->reg, "DPP3"); + // printf("DPP3 0x%lx\n", xxxx); + // } +#endif + return SEQ2( + mov_flags_seq(U16(data)), + SETG("DPP3", UN(10, data)) + ); + default: + printf("x `%s`\n", resolved); + return SEQ2(mov_flags_seq(U16(data)), SETG(resolved, U16(data))); + } + } else { + printf("--------------[0x%06lx] [%d] `%s`, 0x%04x\n", + pc, + L_NIB(reg), + c166_global_registers[L_NIB(reg)], + data); + return mov_flags_seq(U16(data)); // rz_il_op_new_nop(); + } + return EMPTY(); + // return mov_flags_seq(data); //rz_il_op_new_nop(); +} + + +// static RzILOpEffect *c166_il_mov_reg_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// ut16 data = rz_read_at_le16(buf, 2); +// // printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_reg_data16\n", op->id, pc, IP); +// const ut8 reg = buf[1]; +// // ut16 addr = 0; +// char buf_addr[10] = {0}; +// const ut16 base_addr = 0xfe00; //BASE_SFR_ADDR; +// const ut16 addr = base_addr + (2 * reg); +// if (IS_GPR(reg)) { +// rz_snprintf(buf_addr, 10, "r%d", L_NIB(reg)); +// } else { +// rz_snprintf(buf_addr, 10, "0x%04x", addr); +// } +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_reg_data16 %s, 0x%04x\n", +// op->id, pc, IP, +// buf_addr, +// data); +// +// +// +// // RzPVector *items = sdb_get_items(analysis->sdb_classes, true); +// // void **it; +// // rz_pvector_foreach (items, it) { +// // SdbKv *kv = *it; +// // // save_kv_cb(&fd, kv); +// // printf("kv->base.key: `%s`, kv->base.value: `%s`\n", kv->base.key, kv->base.value); +// // +// // } +// // rz_pvector_free(items); +// // char *x = sdb_get(analysis->sdb, "MDH"); +// // printf("x `%s`\n", x); +// +// if (IS_GPR(reg)) { +// // char *reg_name = RZ_NEWS0(char, 4); +// // char reg_name[4] = {0}; +// // rz_snprintf(reg_name, 4, "r%x", L_NIB(reg)); +// return SETG(c166_global_registers[L_NIB(reg)], U16(data)); +// // return SETG(buf_addr, U16(data)); +// // return rz_il_op_new_nop(); +// } else { //if () +// RzPlatformTarget *arch_target = rz_analysis_get_arch_target(analysis); +// // ut32 sz = ht_up_size(arch_target->profile->registers_mmio); +// const char *resolved = rz_platform_profile_resolve_mmio(arch_target->profile, addr); +// // printf("arch_target->arch: `%s`, arch_target->cpu: `%s` `%s` 0x%04x `%s` %d\n", +// // arch_target->arch, +// // arch_target->cpu, +// // arch_target->profile->registers_mmio ? "mmio" : "no mmio", +// // addr, resolved, sz +// // ); +// if (resolved) { +// switch (addr) { +// case 0xfe14: ///< "STKOV" +// return SETG("r2", U16(data)); +// case 0xfe10: ///< "CP" +// return SETG("r0", U16(data)); +// case 0xfe00: ///< "CP" +// return SETG("DPP0", UN(10, data)); +// case 0xfe02: ///< "CP" +// return SETG("DPP1", UN(10, data)); +// case 0xfe04: ///< "CP" +// return SETG("DPP2", UN(10, data)); +// case 0xfe06: ///< "CP" +// return SETG("DPP3", UN(10, data)); +// default:; +// } +// printf("x `%s`\n", resolved); +// return SETG(resolved, U16(data)); +// } else { +// printf("--------------[0x%06lx] [%d] `%s`, 0x%04x\n", +// pc, +// L_NIB(reg), +// c166_global_registers[L_NIB(reg)], +// data); +// return rz_il_op_new_nop(); +// } +// // return SETG(buf_addr, U32(data)); +// // return SETG("DPP0", UN(10, 1)); +// // return SETG("r10", U8(1)); +// // return rz_il_op_new_nop(); +// } +// // if (IS_GPR(reg)) { +// // if (pc <= 0x00003e) +// // return SETG(buf_addr, U32(data)); +// // else +// // return rz_il_op_new_nop(); +// // } else { +// // +// // } +// // return rz_il_op_new_nop(); +// return rz_il_op_new_nop(); +// } +// static RzILOpEffect *c166_il_movb_reg_data8(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_reg_data8\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } +// static RzILOpEffect *c166_il_mov_orwn_orwmp(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_orwn_orwmp\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } +// static RzILOpEffect *c166_il_jmpa_cc_caddr(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_jmpa_cc_caddr\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } +static RzILOpEffect *c166_il_movb_rbn_data4(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movb_rbn_data4\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +// static RzILOpEffect *c166_il_movbs_rwn_rbm(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_movbs_rwn_rbm\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } +// static RzILOpEffect *c166_il_atomic_or_extr_irang2(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_atomic_or_extr_irang2\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } +static RzILOpEffect *c166_il_mov_rwn_orwm_data16(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_mov_rwn_orwm_data16\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} +static RzILOpEffect *c166_il_extp_or_exts_pag10_or_seg8_irang2(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_extp_or_exts_pag10_or_seg8_irang2\n", op->id, pc, IP); + // if (pc == 0x86) exit(0); + return rz_il_op_new_nop(); +} +// static RzILOpEffect *c166_il_pop_reg(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_pop_reg\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } +// static RzILOpEffect *c166_il_atomic_or_extr_irang2(ut64 pc, RzAnalysis *analysis, const ut8 *buf) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL - [0x%06lx] IP: [0x%06lx] c166_il_atomic_or_extr_irang2\n", pc, IP); +// return rz_il_op_new_nop(); +// } + +/** + * + * IF (CPUCON1.SGTDIS = 0) THEN + * (CSP) ← op1 + * END IF + * (IP) ← op2 + * + */ +static RzILOpEffect *c166_il_diswdt(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_diswdt\n", op->id, pc, IP); + return rz_il_op_new_nop(); +} + +static RzILOpEffect *c166_il_jbc_bitaddr_rel(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + ut64 new_IP = op->addr + op->size + (2 * ((st8)buf[2])); + ut8 bitoff = buf[1]; + ut8 bit_index = H_NIB(buf[3]); + const char *reg = NULL; + if (bitoff >= 0xF0) { + reg = c166_rw[L_NIB(bitoff)]; + // val->reg = rz_reg_get(analysis->reg, c166_rw[L_NIB(bitoff)], RZ_REG_TYPE_GPR); + // val->base = rz_reg_get_value(analysis->reg, val->reg); + // return val; + } + // if (bitoff >= 0x80) { + // ut16 addr = BASE_SFR_B_ADDR + (2 * (bitoff & 0x7F)); + // // val->base = (instr->ext.esfr ? BASE_ESFR_B_ADDR : BASE_SFR_B_ADDR) + (2 * (bitoff & 0x7F)); + // } else { + // ut16 addr = BASE_RAM_B_ADDR + 2 * bitoff; + // // val->base = BASE_RAM_B_ADDR + 2 * bitoff; + // } + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_jbc_bitaddr_rel new_IP: [0x%06lx] reg: %s\n", + op->id, pc, IP, new_IP, reg); + + RzILOpBitVector *mask = U16(1 << bit_index); + + RzILOpBitVector *_iar = LOGAND(VARG(reg), mask); + _iar = SHIFTR0(_iar, U16(bit_index)); + + RzILOpBool *cond = NON_ZERO(_iar); + RzILOpEffect *clear_bit = BRANCH(DUP(cond), SETG(reg, SUB(VARG(reg), DUP(mask))), NOP()); + // RzILOpEffect *clear_bit = ITE( + // cond, + // NOP(), // SETG(reg, SUB(VARG(reg), DUP(mask))), + // NOP() + // ); + // RzILOpEffect *clear_bit = SETG(reg, SUB(VARG(reg), mask)); + + // RzILOpBool *cond = IS_ZERO(LOGAND(VARG(reg), mask)); + + RzILOpEffect *e = SETG("e", IL_FALSE); + RzILOpEffect *z = SETG("z", INV(DUP(cond))); + RzILOpEffect *v = SETG("v", IL_FALSE); + RzILOpEffect *c = SETG("c", IL_FALSE); + RzILOpEffect *n = SETG("n", DUP(cond)); + // exit(0); + // if (pc == 0x66) exit(0); + // return SEQ6(e, z, v, c, n, NOP()); + // return SEQ6(e, z, v, c, n, BRANCH(INV(cond), JMP(U32(new_IP)), NOP())); + return SEQ7(e, z, v, c, n, BRANCH(DUP(cond), JMP(U32(new_IP)), NOP()), clear_bit); + // return ; + // return rz_il_op_new_nop(); +} + +static RzILOpEffect *c166_il_jmpr_rel(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + ut8 condition = (buf[0] & 0xf0) >> 4; + ut64 new_IP = op->addr + op->size + (2 * ((st8)buf[1])); + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_jmpr_rel %s (%x) new_IP: [0x%06lx] \n", + op->id, pc, IP, conds(condition), condition << 1, new_IP); + // return rz_il_op_new_nop(); + RzILOpBool *cond = NULL; + // RzILOpBool *cond = INV(VARG("z")); + switch (condition << 1) { + case C166_CC_UC: + cond = IL_TRUE; + break; + case C166_CC_NET: + break; + case C166_CC_EQ: + // cond = VARG("z"); + // cond = INV(VARG("z")); + // cond = ITE(VARG("z"), IL_FALSE, IL_TRUE); + cond = ITE(VARG("z"), IL_TRUE, IL_FALSE); + // cond = ITE(EQ(VARG("z"), IL_FALSE), IL_TRUE, IL_FALSE); + break; + case C166_CC_NE: + cond = INV(VARG("z")); + break; + case C166_CC_V: + break; + case C166_CC_NV: + break; + case C166_CC_N: + break; + case C166_CC_NN: + cond = INV(VARG("n")); + break; + case C166_CC_C: + break; + case C166_CC_NC: + break; + case C166_CC_SGT: + break; + case C166_CC_SLE: + break; + case C166_CC_SLT: + break; + case C166_CC_SGE: + break; + case C166_CC_UGT: + break; + case C166_CC_ULE: + break; + default:; + rz_warn_if_reached(); + } + // (void)cond; + // RzILOpBool *cond = INV(VARG("z")); + // return BRANCH(cond, JMP(U32(new_IP)), JMP(U32(op->addr + op->size))); + return BRANCH(cond, JMP(U32(new_IP)), rz_il_op_new_nop()); + // return rz_il_op_new_nop(); +} + +// static RzILOpEffect *c166_il_bclr_bitoff2(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bclr_bitoff2\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +// static RzILOpEffect *c166_il_bset_bitoff2(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { +// ut64 IP = rz_reg_getv(analysis->reg, "IP"); +// printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_bset_bitoff2\n", op->id, pc, IP); +// return rz_il_op_new_nop(); +// } + +/** + * + * (SP) ← (SP) - 2 + * ((SP)) ← (CSP) + * (SP) ← (SP) - 2 + * ((SP)) ← (IP) + * IF (CPUCON1.SGTDIS = 0) THEN + * (CSP) ← op1 + * END IF + * (IP) ← op2 + * + */ +static RzILOpEffect *c166_il_calls_seg_caddr(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 seg = buf[1]; + const ut16 caddr = rz_read_at_le16(buf, 2); + const ut32 to_addr = (((ut32)seg) << 16) | caddr; + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_calls_seg_caddr\n", op->id, pc, IP); + RzILOpEffect *set_CSP = SETG("CSP", ITE(INV(VARG("SGTDIS")), U8(seg), U8(0))); + RzILOpBitVector *_loc = UN(C166_ADDR_SIZE, to_addr); + (void)_loc; + (void)set_CSP; + return rz_il_op_new_nop(); + // return SEQ2(set_CSP, JMP(_loc)); +} + +/** + * + * IF (CPUCON1.SGTDIS = 0) THEN + * (CSP) ← op1 + * END IF + * (IP) ← op2 + * + */ +static RzILOpEffect *c166_il_jmps_seg_caddr(ut64 pc, RzAnalysis *analysis, const ut8 *buf, RzAnalysisOp *op) { + ut64 IP = rz_reg_getv(analysis->reg, "IP"); + const ut8 seg = buf[1]; + const ut16 caddr = rz_read_at_le16(buf, 2); + const ut32 to_addr = (((ut32)seg) << 16) | caddr; + printf("IL[0x%02x] - [0x%06lx] IP: [0x%06lx] c166_il_jmps_seg_caddr\n", op->id, pc, IP); + +#ifdef C166_DUPLICATE_REG_OPERATIONS + const ut8 SGTDIS = (ut8)rz_reg_getv(analysis->reg, "SGTDIS"); + if (SGTDIS == 0) { + rz_reg_setv(analysis->reg, "CSP", seg); + } + rz_reg_setv(analysis->reg, "IP", (((ut32)seg) << 16) | caddr); +#endif + + RzILOpEffect *set_CSP = SETG("CSP", ITE(INV(VARG("SGTDIS")), U8(seg), U8(0))); + RzILOpBitVector *_loc = UN(C166_ADDR_SIZE, to_addr); + return SEQ2(set_CSP, JMP(_loc)); +} + +static c166_il_op c166_ops[256] = { + c166_il_add_rwn_rwm, // 0x00 + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_add_reg_data16, // + c166_il_unk, //c166_il_addb_reg_data8, // + c166_il_add_rwn_x, // 0x08 + c166_il_addb_rbn_x, // 0x09 + c166_il_bfldl_bitoff_x, // 0x0A 10 + c166_il_unk, // + c166_il_unk, // + c166_il_jmpr_rel, // + c166_il_bclr_bitoff0, // + c166_il_bset_bitoff0, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // 20 + c166_il_unk, // + c166_il_unk, //c166_il_addc_reg_data16, // + c166_il_unk, // + c166_il_addc_rwn_x, // + c166_il_unk, // + c166_il_bfldh_bitoff_x, // + c166_il_unk, // + c166_il_unk, // + c166_il_jmpr_rel, // + c166_il_unk, //30 + c166_il_unk, //c166_il_bset_bitoff1, // + c166_il_unk, //c166_il_sub_rwn_rwm, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //c166_il_sub_reg_data16, // + c166_il_unk, // + c166_il_sub_rwn_x, //40 + c166_il_unk, //c166_il_subb_rbn_x, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // C166_ROR_Rwn_Rwm + c166_il_jmpr_rel, // + c166_il_unk, //c166_il_bclr_bitoff2, // + c166_il_unk, //c166_il_bset_bitoff2, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //50 + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //c166_il_bmovn_bitaddr_bitaddr, // + c166_il_unk, // + c166_il_unk, //60 + c166_il_jmpr_rel, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //c166_il_cmp_rwn_rwm, // + c166_il_cmpb_rbn_rbm, // + c166_il_unk, //c166_il_cmp_reg_mem, // + c166_il_unk, //c166_il_cmpb_reg_mem, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //c166_il_cmp_reg_data16, //70 + c166_il_cmpb_reg_data8, // + c166_il_unk, //c166_il_cmp_rwn_x, // + c166_il_cmpb_rbn_x, // + c166_il_unk, // + c166_il_unk, //c166_il_div_rwn, // + c166_il_shl_rwn_rwm, // + c166_il_jmpr_rel, // + c166_il_unk, //c166_il_bclr_bitoff4, // + c166_il_unk, //c166_il_bset_bitoff4, // + c166_il_unk, //80 + c166_il_xorb_rbn_rbm, // + c166_il_xor_reg_mem, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //90 + c166_il_unk, // + c166_il_shl_rwn_data4, // + c166_il_jmpr_rel, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //100 + c166_il_unk, // + c166_il_and_reg_data16, // + c166_il_unk, // + c166_il_and_rwn_x, // + c166_il_unk, // + c166_il_unk, // + c166_il_divl_rwn, // + c166_il_unk, // + c166_il_jmpr_rel, // + c166_il_unk, //110 + c166_il_bset_bitoff6, // + c166_il_or_rwn_rwm, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_or_reg_data16, // + c166_il_unk, // + c166_il_or_rwn_x, //120 + c166_il_orb_rbn_x, // + c166_il_unk, // + c166_il_unk, // + c166_il_shr_rwn_data4, // + c166_il_jmpr_rel, // + c166_il_unk, //c166_il_bclr_bitoff7, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //130 + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //c166_il_mov_norwm_rwn, // + c166_il_unk, // + c166_il_jb_bitaddr_rel, // + c166_il_unk, // + c166_il_unk, //140 + c166_il_jmpr_rel, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_cpl_rwn, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //150 + c166_il_unk, // + c166_il_mov_rwn_orwmp, // + c166_il_unk, // + c166_il_jnb_bitaddr_rel, // + c166_il_unk, // + c166_il_unk, // + c166_il_jmpr_rel, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //160 + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_diswdt, // 0xA5 + c166_il_unk, // + c166_il_unk, // + c166_il_mov_rwn_orwm, // + c166_il_movb_rbn_oRwm, // + c166_il_jbc_bitaddr_rel, //170 + c166_il_unk, // + c166_il_unk, // + c166_il_jmpr_rel, + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //180 + c166_il_einit, // + c166_il_unk, // + c166_il_unk, // + c166_il_mov_orwm_rwn, // + c166_il_movb_orwm_rbn, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_jmpr_rel, // + c166_il_unk, //c166_il_bclr_bitoff11, //190 + c166_il_unk, //c166_il_bset_bitoff11, // + c166_il_movbz_rwn_rbm, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //c166_il_mov_orwm_data16_rwn, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, //200 + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_unk, // + c166_il_jmpr_rel, //c166_il_jmpr_cc_slt_rel, // + c166_il_unk,c166_il_unk, // + c166_il_unk, //c166_il_movbs_rwn_rbm, // + c166_il_unk, //c166_il_atomic_or_extr_irang2, // + c166_il_unk, //210 + c166_il_unk, // + c166_il_mov_rwn_orwm_data16, // + c166_il_unk, // + c166_il_unk, // + c166_il_extp_or_exts_pag10_or_seg8_irang2, // + c166_il_unk, // + c166_il_unk, // + c166_il_calls_seg_caddr, // + c166_il_rets, // + c166_il_extp_or_exts_rwm_irang2, //220 + c166_il_jmpr_rel, //c166_il_jmpr_cc_sge_rel, // + c166_il_unk, // + c166_il_unk, // + c166_il_mov_rwn_data4, // 0xE0 + c166_il_movb_rbn_data4, // + c166_il_unk, // + c166_il_unk, // + c166_il_movb_orwm_data16_rbn, // + c166_il_unk, // + c166_il_mov_reg_data16, //230 + c166_il_unk, //c166_il_movb_reg_data8, // + c166_il_unk, //c166_il_mov_orwn_orwmp, // + c166_il_unk, // + c166_il_unk, //c166_il_jmpa_cc_caddr, // + c166_il_unk, // + c166_il_push_reg, // + c166_il_jmpr_rel, //c166_il_jmpr_cc_ugt_rel, // + c166_il_unk, // + c166_il_unk, // + c166_il_mov_rwn_rwm, //240 + c166_il_movb_rbn_rbm, // + c166_il_unk, // + c166_il_unk, //c166_il_movb_reg_mem, // + c166_il_movb_rbn_orwm_data16, // + c166_il_unk, // + c166_il_mov_mem_reg, // 0xF6 + c166_il_unk, //c166_il_movb_mem_reg, // + c166_il_unk, // + c166_il_unk, // + c166_il_jmps_seg_caddr, ///< C166_JMPS_seg_caddr = 0xFA 250 + c166_il_unk, // 0xFB + c166_il_unk, //c166_il_pop_reg, // 0xFC + c166_il_jmpr_rel, // 0xFD + c166_il_unk, // 0xFE + c166_il_unk // 0xFF +}; + +RZ_IPI bool rz_c166_il_opcode(RzAnalysis *analysis, RzAnalysisOp *op, ut64 pc, const ut8 *buf) { + rz_return_val_if_fail(analysis && op, false); + + const c166_il_op create_op = c166_ops[op->id]; + op->il_op = create_op(pc, analysis, buf, op); + return true; +} + +RZ_IPI RzAnalysisILConfig *rz_c166_il_config(RZ_NONNULL RzAnalysis *analysis) { + rz_return_val_if_fail(analysis, NULL); + + RzAnalysisILConfig *r = rz_analysis_il_config_new(32, analysis->big_endian, C166_ADDR_SIZE); + r->reg_bindings = c166_global_registers; + // C166State *state = (C166State *)analysis->plugin_data; + // if (!state) { + // RZ_LOG_FATAL("C166State was NULL."); + // } + // const RzCore *core = analysis->core; + // char *cpus_dir = rz_path_system(core->sys_path, RZ_SDB_ARCH_CPUS); + // if (!cpus_dir) { + // return false; + // } + // rz_type_db_reload(core->analysis->typedb, cpus_dir); + // free(cpus_dir); + // + // + // RzPlatformTarget *arch_target = rz_analysis_get_arch_target(analysis); + // rz_platform_load_profile_sdb(arch_target, RZ_SDB_ARCH_CPUS); + // + // ut32 sz = ht_up_size(arch_target->profile->registers_mmio); + // const char *resolved = rz_platform_profile_resolve_mmio(arch_target->profile, 0xfe00); + // printf("arch_target->arch: `%s`, arch_target->cpu: `%s` `%s` 0x%04x `%s` %d\n", + // arch_target->arch, + // arch_target->cpu, + // arch_target->profile->registers_mmio ? "mmio" : "no mmio", + // 0xfe00, resolved, sz + // ); + r->init_state = rz_analysis_il_init_state_new(); + if (!r->init_state) { + rz_analysis_il_config_free(r); + return NULL; + } +#define IL_UN(l, x) rz_il_value_new_bitv(rz_bv_new_from_ut64(l, x)) +#define IL_U8(x) IL_UN(8, x) +#define IL_U16(x) IL_UN(16, x) +#define IL_U32(x) IL_UN(32, x) + rz_analysis_il_init_state_set_var(r->init_state, "r0", IL_U16(0xFC00)); ///< CP + rz_analysis_il_init_state_set_var(r->init_state, "r1", IL_U16(0xFC00)); /// < SP + rz_analysis_il_init_state_set_var(r->init_state, "r2", IL_U16(0xFA00)); ///< STKOV + rz_analysis_il_init_state_set_var(r->init_state, "r3", IL_U16(0xFC00)); ///< STKUN + rz_analysis_il_init_state_set_var(r->init_state, "DPP1", IL_UN(10, 0x0001)); + rz_analysis_il_init_state_set_var(r->init_state, "DPP2", IL_UN(10, 0x0002)); + rz_analysis_il_init_state_set_var(r->init_state, "DPP3", IL_UN(10, 0x0003)); + rz_analysis_il_init_state_set_var(r->init_state, "BUSCON0", IL_U16(0x0680)); ///< BUSCON0 + return r; +} +#include \ No newline at end of file diff --git a/librz/arch/isa/c166/c166_il.h b/librz/arch/isa/c166/c166_il.h new file mode 100644 index 00000000000..b6bcd249c75 --- /dev/null +++ b/librz/arch/isa/c166/c166_il.h @@ -0,0 +1,31 @@ +// SPDX-FileCopyrightText: 2026 Sergey Sharshunov +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef RZIL_ANALYSIS_C166_H +#define RZIL_ANALYSIS_C166_H + +#include "analysis_private.h" +// #include +#include + +#define C166_SP_SIZE 16 +#define C166_CSP_SIZE 16 + +#define C166_SP "SP" +#define C166_CSP "CSP" + +#define C166_DUPLICATE_REG_OPERATIONS 1 + + + +// #define R1V VARG(R1) +// #define R2V VARG(R2) + +// #define C166_ADDR_SIZE 24 +#define C166_ADDR_SIZE 32 // should be 24 bits max, but we can ignore this + +// RZ_IPI bool rz_c166_il_opcode(RzAnalysis *analysis, RzAnalysisOp *op, ut64 pc, AVROp *aop, AVROp *next_op); +RZ_IPI bool rz_c166_il_opcode(RzAnalysis *analysis, RzAnalysisOp *op, ut64 pc, const ut8 *buf); +RZ_IPI RzAnalysisILConfig *rz_c166_il_config(RZ_NONNULL RzAnalysis *analysis); + +#endif // RZIL_ANALYSIS_C166_H diff --git a/librz/arch/meson.build b/librz/arch/meson.build index 3cd4b2eda66..365174d794a 100644 --- a/librz/arch/meson.build +++ b/librz/arch/meson.build @@ -158,6 +158,8 @@ arch_isa_sources = [ 'isa/avr/disassembler.c', 'isa/cil/cil_dis.c', 'isa/cr16/cr16_disas.c', + 'isa/c166/c166_common.c', + 'isa/c166/c166_il.c', 'isa/dcpu16/asm.c', 'isa/dcpu16/dis.c', 'isa/ebc/ebc_disas.c', diff --git a/librz/arch/omf_process.c b/librz/arch/omf_process.c index d5fde3bf8c7..2225e1c5c05 100644 --- a/librz/arch/omf_process.c +++ b/librz/arch/omf_process.c @@ -25,18 +25,21 @@ ut64 get_reg_val2(RzReg *areg, const char *name) { return value; } -#define SET_CPUCON1(val) set_reg_val2(areg, CPUCON1_NAME, val) -#define SET_SP(val) set_reg_val2(areg, "SP", val) -#define SET_CSP(val) set_reg_val2(areg, "CSP", val) -#define SET_SGTDIS(val) set_reg_val2(areg, CPUCON1_NAME, (CPUCON1_RESET_VALUE | (val << 3))) +#define SET_CPUCON1(analysis, val) set_reg_val2(rz_analysis_get_reg(analysis), CPUCON1_NAME, val) +#define SET_SP(analysis, val) set_reg_val2(rz_analysis_get_reg(analysis), "SP", val) +#define SET_CSP(analysis, val) set_reg_val2(rz_analysis_get_reg(analysis), "CSP", val) +#define SET_SGTDIS(analysis, val) set_reg_val2(rz_analysis_get_reg(analysis), CPUCON1_NAME, (CPUCON1_RESET_VALUE | (val << 3))) -#define GET_SGTDIS get_flg_val(areg, "SGTDIS") -#define GET_CPUCON1 get_reg_val2(areg, "CPUCON1") -#define GET_SP get_reg_val2(areg, "SP") +#define GET_SGTDIS(analysis) get_flg_val(rz_analysis_get_reg(analysis), "SGTDIS") +#define GET_CPUCON1(analysis) get_reg_val2(rz_analysis_get_reg(analysis), "CPUCON1") +#define GET_SP(analysis) get_reg_val2(rz_analysis_get_reg(analysis), "SP") static OMF_components *get_component_by_ti(const rz_bin_omf166_obj *omf_obj, ut16 ti) { bool found = false; OMF_type *type = ht_up_find(omf_obj->ht_types, ti, &found); + if (!found) { + return NULL; + } if (type->descr_type == COMPONENT_LIST_DESCRIPTOR) { return (OMF_components *)&type->descriptor.components; } @@ -89,8 +92,9 @@ static inline RzType *TYPE_TI(rz_bin_omf166_obj *omf_obj, ut16 ti) { } RzType *ret = rz_type_identifier_of_base_type_str(typedb, type->label); - if (!ret) + if (!ret) { return rz_type_identifier_of_base_type_str(typedb, "unknown_t"); + } return ret; } @@ -211,8 +215,8 @@ RZ_API bool rz_core_bin_apply_omf_debug(const RzCore *core, const RzBinFile *bin return false; } - RzReg *areg = rz_analysis_get_reg(core->analysis); - SET_SP(SP_RESET_VALUE); + SET_SP(core->analysis, SP_RESET_VALUE); + rz_bin_omf166_obj *omf_obj = (rz_bin_omf166_obj *)binfile->o->bin_obj; #ifdef RZ_BUILD_DEBUG @@ -228,7 +232,20 @@ RZ_API bool rz_core_bin_apply_omf_debug(const RzCore *core, const RzBinFile *bin return false; } - SET_SGTDIS(!(omf_obj->modinfo & 0x01)); + SET_SGTDIS(core->analysis, !(omf_obj->modinfo & 0x01)); + + void **it; + rz_pvector_foreach (omf_obj->sections_vec, it) { + const OMF_sections *section = (OMF_sections *)*it; + if (section->class_index == C166_CLASS_FCONST || + section->class_index == C166_CLASS_HCONST || + section->class_index == C166_CLASS_XCONST || + section->class_index == C166_CLASS_NCONST || + section->Type != 2) { + ut64 vaddr = (section->SegmentNumber8 << 16) + section->offset; + rz_meta_set(core->analysis, RZ_META_TYPE_DATA, vaddr, section->Seclen, "CONST"); + } + } if (!binfile->o->lines) { RzPVector *ls = omf_obj->linnums_vec; diff --git a/librz/arch/op.c b/librz/arch/op.c index becb187424b..51f246abc36 100644 --- a/librz/arch/op.c +++ b/librz/arch/op.c @@ -30,7 +30,9 @@ RZ_API void rz_analysis_op_init(RzAnalysisOp *op) { op->refptr = 0; op->val = UT64_MAX; op->disp = UT64_MAX; - op->mmio_address = UT64_MAX; + for (int i = 0; i < RZ_ARRAY_SIZE(op->mmios); i++) { + op->mmios[i] = UT64_MAX; + } op->stackptr = RZ_ANALYSIS_OP_INVALID_STACKPTR; } diff --git a/librz/arch/p/analysis/analysis_avr.c b/librz/arch/p/analysis/analysis_avr.c index 0622447d395..4aaa81e7f43 100644 --- a/librz/arch/p/analysis/analysis_avr.c +++ b/librz/arch/p/analysis/analysis_avr.c @@ -151,7 +151,8 @@ static int avr_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 * break; case AVR_OP_IN: op->type2 = 0; - op->val = op->mmio_address = aop.param[1]; // A + op->val = op->mmios[op->mmios_count] = aop.param[1]; // A + op->mmios_count++; op->type = RZ_ANALYSIS_OP_TYPE_IO; op->family = RZ_ANALYSIS_OP_FAMILY_IO; break; @@ -178,7 +179,8 @@ static int avr_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 * break; case AVR_OP_OUT: op->type2 = 1; - op->val = op->mmio_address = aop.param[0]; // A + op->val = op->mmios[op->mmios_count] = aop.param[0]; // A + op->mmios_count++; op->type = RZ_ANALYSIS_OP_TYPE_IO; op->family = RZ_ANALYSIS_OP_FAMILY_IO; break; diff --git a/librz/arch/p/analysis/analysis_c166.c b/librz/arch/p/analysis/analysis_c166.c index 3260f310c30..4af3d1dbfc9 100644 --- a/librz/arch/p/analysis/analysis_c166.c +++ b/librz/arch/p/analysis/analysis_c166.c @@ -7,6 +7,7 @@ #include #include #include +#include "c166/c166_il.h" #include "librz/arch/isa/c166/c166_disas.h" @@ -89,11 +90,6 @@ bool set_reg_val(RzAnalysis *analysis, const char *name, const ut64 value) { #define SET_A_IP(val) set_reg_val(analysis, "IP", val) #define SET_A_SP(val) set_reg_val(analysis, "SP", val) -static void c166_set_mimo_addr_from_reg(RzAnalysisOp *op, ut8 reg) { - if (reg < 0xF0) { - op->mmio_address = BASE_SFR_ADDR + (2 * reg); - } -} static ut16 target_addressing_mode_caddr(RzAnalysisOp *op, ut16 target) { /** @@ -158,7 +154,9 @@ static RzAnalysisValue *c166_new_mem_value(const RzAnalysis *analysis, const C16 } switch (instr->ext.mode) { + case C166_EXT_MODE_ATOMIC: case C166_EXT_MODE_NONE: + case C166_EXT_MODE_REG: val->reg = reg; break; case C166_EXT_MODE_SEG: @@ -168,6 +166,7 @@ static RzAnalysisValue *c166_new_mem_value(const RzAnalysis *analysis, const C16 val->reg = reg; val->base = ((ut32)instr->ext.value) << 14; break; + default:; } val->base += mem & 0x3FFF; return val; @@ -181,6 +180,15 @@ static RzAnalysisValue *c166_new_imm_value(ut16 data, bool absolute) { return val; } +// static RzAnalysisValue *c166_new_mem_value(ut16 data, bool absolute) { +// RzAnalysisValue *val = rz_analysis_value_new(); +// val->type = RZ_ANALYSIS_VAL_MEM; +// // val->imm = data; +// // val->absolute = absolute; +// val->delta = data; +// return val; +// } + static RzAnalysisValue *c166_new_bitaddr_value(const RzAnalysis *analysis, const C166_Inst *instr, ut8 bitoff) { RzAnalysisValue *val = rz_analysis_value_new(); val->type = RZ_ANALYSIS_VAL_MEM; @@ -308,11 +316,11 @@ static void c166_op_trap7(RzAnalysis *analysis, RzAnalysisOp *op, const ut8 *buf op->fail = op->addr + op->size; op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = 4; - const ut8 SGTDIS = (ut8)GET_A_SGTDIS; - if (SGTDIS == 0) { - op->stackptr += 2; - } - SET_A_IP((buf[1] * 4) << GET_A_SCINT); + // const ut8 SGTDIS = (ut8)GET_A_SGTDIS; + // if (SGTDIS == 0) { + // op->stackptr += 2; + // } + // SET_A_IP((buf[1] * 4) << GET_A_SCINT); } /** @@ -349,7 +357,7 @@ static void c166_op_jmpi_cc_orwn(RzAnalysis *analysis, RzAnalysisOp *op, const u const ut8 seg = GET_A_CSP; if (buf[1] == 1) { op->jump = (((ut32)seg) << 16) | ((cp + 2 * v) - op->size); - SET_A_IP(op->jump); + // SET_A_IP(op->jump); } } @@ -384,8 +392,11 @@ static void c166_op_jmps_seg_caddr(RzAnalysis *analysis, RzAnalysisOp *op, const } } c166_set_jump_target_seg_caddr(op, seg, caddr); + // op->dst = c166_new_reg_value(analysis, reg, false); + op->src[0] = c166_new_imm_value(seg, false); + op->src[1] = c166_new_imm_value(caddr, false); // SET_IP(caddr); ///< Need implement relative jump by offset - SET_A_IP((((ut32)seg) << 16) | (caddr - op->size)); ///< (caddr - op->size) for emulation fix + SET_A_IP((((ut32)seg) << 16) | caddr); ///< (caddr - op->size) for emulation fix } /** @@ -495,17 +506,17 @@ static void c166_op_call_seg_caddr(RzAnalysis *analysis, RzAnalysisOp *op, const op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = 4; - ut8 SP = (ut8)GET_A_SP; - SET_A_SP((ut64)SP - 2); - SP = (ut8)GET_A_SP; - - const ut8 SGTDIS = (ut8)GET_A_SGTDIS; - if (SGTDIS == 0) { - if (!SET_A_CSP((ut64)seg)) { - RZ_LOG_WARN("Error setting reg value\n"); - } - } - SET_A_IP((ut64)caddr); + // ut8 SP = (ut8)GET_A_SP; + // SET_A_SP((ut64)SP - 2); + // SP = (ut8)GET_A_SP; + // + // const ut8 SGTDIS = (ut8)GET_A_SGTDIS; + // if (SGTDIS == 0) { + // if (!SET_A_CSP((ut64)seg)) { + // RZ_LOG_WARN("Error setting reg value\n"); + // } + // } + // SET_A_IP((ut64)caddr); op->eob = true; } @@ -539,14 +550,13 @@ static void c166_op_pcall_reg_caddr(RzAnalysis *analysis, RzAnalysisOp *op, cons op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = 4; - ut8 SP = (ut8)GET_A_SP; - SET_A_SP((ut64)SP - 2); - SP = (ut8)GET_A_SP; - SET_A_IP((ut64)caddr); + // ut8 SP = (ut8)GET_A_SP; + // SET_A_SP((ut64)SP - 2); + // SP = (ut8)GET_A_SP; + // SET_A_IP((ut64)caddr); op->type = RZ_ANALYSIS_OP_TYPE_UCALL; c166_set_jump_target_from_caddr(op, caddr); - c166_set_mimo_addr_from_reg(op, buf[1]); op->eob = true; } @@ -781,46 +791,74 @@ static void c166_op_rets(RzAnalysis *analysis, RzAnalysisOp *op, const ut8 *buf) op->stackptr = 4; } -static void c166_op_mov_reg_data(RzAnalysis *analysis, RzAnalysisOp *op, const ut8 *buf) { +static void c166_op_mov_reg_data(RzAnalysis *analysis, RzAnalysisOp *op, const C166_Inst *instr, const ut8 *buf) { const ut8 reg = buf[1]; - const bool byte = buf[0] == C166_MOVB_reg_data8; - const ut16 mask = byte ? 0xFF : 0xFFFF; - const ut16 data = rz_read_at_le16(&buf, 2) & mask; + // const bool byte = buf[0] == C166_MOVB_reg_data8; + // const ut16 mask = byte ? 0xFF : 0xFFFF; + // const ut16 data = rz_read_at_le16(&buf, 2) & mask; + const ut16 data = rz_read_at_le16(&buf, 2); op->type = RZ_ANALYSIS_OP_TYPE_MOV; op->dst = c166_new_reg_value(analysis, reg, false); op->src[0] = c166_new_imm_value(data, true); if (op->dst != NULL) { - op->mmio_address = op->dst->base; + op->mmios[op->mmios_count] = op->dst->base; + op->mmios_count++; } + const ut16 base_addr = instr->ext.esfr ? BASE_ESFR_ADDR : BASE_SFR_ADDR; + const ut16 addr = base_addr + (2 * reg); + op->mmios[op->mmios_count] = addr; + op->mmios_count++; } -static void c166_op_mov_reg_mem(const RzAnalysis *analysis, RzAnalysisOp *op, const C166_Inst *instr, const ut8 *buf) { - op->type = RZ_ANALYSIS_OP_TYPE_MOV; - const bool byte = buf[0] != C166_MOV_reg_mem; - const ut16 mask = byte ? 0xFF : 0xFFFF; - const ut32 addr = rz_read_at_le16(buf, 2) & mask; +static void c166_op_dst_reg_src_mem(const RzAnalysis *analysis, RzAnalysisOp *op, const C166_Inst *instr, const ut8 *buf, const bool byte) { + const ut16 mem = rz_read_at_le16(buf, 2); + const st32 i = (mem >> 14) & 0b11; + const ut16 addr = BASE_SFR_ADDR + (i * 2); op->dst = c166_new_reg_value(analysis, buf[1], byte); - op->src[0] = c166_new_mem_value(analysis, instr, addr); - if (op->dst != NULL) { - op->mmio_address = op->dst->base; - } + op->src[0] = c166_new_mem_value(analysis, instr, rz_read_at_le16(buf, 2)); + op->mmios[op->mmios_count] = addr; + op->mmios_count++; } -static void c166_op_mov_mem_reg(const RzAnalysis *analysis, RzAnalysisOp *op, const C166_Inst *instr, const ut8 *buf) { - op->type = RZ_ANALYSIS_OP_TYPE_MOV; - const bool byte = buf[0] != C166_MOV_mem_reg; +static void c166_op_src_mem_src_reg(const RzAnalysis *analysis, RzAnalysisOp *op, const C166_Inst *instr, const ut8 *buf, const bool byte) { + const ut16 mem = rz_read_at_le16(buf, 2); op->src[0] = c166_new_reg_value(analysis, buf[1], byte); - op->dst = c166_new_mem_value(analysis, instr, rz_read_at_le16(buf, 2)); - if (op->src[0]) - op->mmio_address = op->src[0]->base; + op->src[1] = c166_new_mem_value(analysis, instr, mem); + if (op->src[0]) { + op->mmios[op->mmios_count] = op->src[0]->base; + op->mmios_count++; + } + if (op->src[1]) { + const st32 i = (mem >> 14) & 0b11; + const ut16 addr = BASE_SFR_ADDR + (i * 2); + op->mmios[op->mmios_count] = addr; + op->mmios_count++; + } +} + +static void c166_op_src_reg_src_mem(const RzAnalysis *analysis, RzAnalysisOp *op, const C166_Inst *instr, const ut8 *buf, const bool byte) { + const ut16 mem = rz_read_at_le16(buf, 2); + op->src[0] = c166_new_mem_value(analysis, instr, mem); + op->src[1] = c166_new_reg_value(analysis, buf[1], byte); + if (op->src[1]) { + op->mmios[op->mmios_count] = op->src[1]->base; + op->mmios_count++; + } + if (op->src[0]) { + const st32 i = (mem >> 14) & 0b11; + const ut16 addr = BASE_SFR_ADDR + (i * 2); + op->mmios[op->mmios_count] = addr; + op->mmios_count++; + } } static void c166_op_bfld(const RzAnalysis *analysis, RzAnalysisOp *op, const C166_Inst *instr, const ut8 *buf) { op->type = RZ_ANALYSIS_OP_TYPE_STORE; op->dst = c166_new_bitaddr_value(analysis, instr, buf[1]); if (op->dst != NULL) { - op->mmio_address = op->dst->base; + op->mmios[op->mmios_count] = op->dst->base; + op->mmios_count++; } } @@ -832,7 +870,8 @@ static void c166_op_jmp_bitoff(const RzAnalysis *analysis, RzAnalysisOp *op, con op->fail = op->addr + op->size; op->src[0] = c166_new_bitaddr_value(analysis, instr, buf[1]); if (op->src[0]) { - op->mmio_address = op->src[0]->base; + op->mmios[op->mmios_count] = op->src[0]->base; + op->mmios_count++; } } @@ -855,17 +894,29 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, case C166_ADDCB_Rbn_x: c166_op_rn_x(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_ADD, true); break; - case C166_ADD_mem_reg: - case C166_ADD_reg_mem: - case C166_ADDB_mem_reg: - case C166_ADDB_reg_mem: - case C166_ADDC_mem_reg: - case C166_ADDC_reg_mem: + case C166_ADD_mem_reg: /// + case C166_ADDC_mem_reg: { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + const bool byte = buf[0] != C166_ADDB_mem_reg; + c166_op_src_mem_src_reg(analysis, op, instr, buf, byte); + break; + } case C166_ADDCB_mem_reg: + case C166_ADDB_mem_reg: { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + const bool byte = buf[0] != C166_ADDB_mem_reg; + c166_op_src_mem_src_reg(analysis, op, instr, buf, byte); + break; + } + case C166_ADDC_reg_mem: case C166_ADDCB_reg_mem: + case C166_ADDB_reg_mem: + case C166_ADD_reg_mem: { op->type = RZ_ANALYSIS_OP_TYPE_ADD; - c166_set_mimo_addr_from_reg(op, operand1); + const bool byte = buf[0] != C166_ADDB_mem_reg; + c166_op_src_reg_src_mem(analysis, op, instr, buf, byte); break; + } case C166_ADD_reg_data16: case C166_ADDC_reg_data16: op->type = RZ_ANALYSIS_OP_TYPE_ADD; @@ -873,7 +924,11 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, op->reg = c166_rb[buf[1] & 0xF]; } op->val = rz_read_at_le16(buf, 2); - c166_set_mimo_addr_from_reg(op, buf[1]); + const ut8 reg = buf[1]; + const ut16 base_addr = instr->ext.esfr ? BASE_ESFR_ADDR : BASE_SFR_ADDR; + const ut16 addr = base_addr + (2 * reg); + op->mmios[op->mmios_count] = addr; + op->mmios_count++; break; case C166_ADDB_reg_data8: case C166_ADDCB_reg_data8: @@ -882,7 +937,6 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, op->reg = c166_rb[operand1 & 0xF]; } op->val = get_operand(instr, 2); - c166_set_mimo_addr_from_reg(op, operand1); break; case C166_SUB_Rwn_Rwm: @@ -901,20 +955,19 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, case C166_SUBCB_Rbn_x: c166_op_rn_x(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_SUB, true); break; - case C166_SUB_mem_reg: case C166_SUB_reg_data16: - case C166_SUB_reg_mem: - case C166_SUBC_mem_reg: case C166_SUBC_reg_data16: - case C166_SUBC_reg_mem: - case C166_SUBB_mem_reg: case C166_SUBB_reg_data8: - case C166_SUBB_reg_mem: - case C166_SUBCB_mem_reg: case C166_SUBCB_reg_data8: + case C166_SUB_mem_reg: + case C166_SUBC_mem_reg: + case C166_SUBB_mem_reg: + case C166_SUBCB_mem_reg: + case C166_SUB_reg_mem: + case C166_SUBC_reg_mem: + case C166_SUBB_reg_mem: case C166_SUBCB_reg_mem: op->type = RZ_ANALYSIS_OP_TYPE_SUB; - c166_set_mimo_addr_from_reg(op, operand1); break; case C166_MUL_Rwn_Rwm: case C166_MULU_Rwn_Rwm: @@ -938,36 +991,41 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, case C166_ANDB_Rbn_x: c166_op_rn_x(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_AND, true); break; - case C166_AND_mem_reg: case C166_AND_reg_data16: - case C166_AND_reg_mem: - case C166_ANDB_mem_reg: case C166_ANDB_reg_data8: + case C166_AND_mem_reg: + case C166_ANDB_mem_reg: + case C166_AND_reg_mem: case C166_ANDB_reg_mem: op->type = RZ_ANALYSIS_OP_TYPE_AND; - c166_set_mimo_addr_from_reg(op, operand1); break; case C166_OR_Rwn_Rwm: + op->type = RZ_ANALYSIS_OP_TYPE_OR; c166_op_rn_rm(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_OR, false); break; case C166_OR_Rwn_x: + op->type = RZ_ANALYSIS_OP_TYPE_OR; c166_op_rn_x(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_OR, false); break; case C166_ORB_Rbn_Rbm: + op->type = RZ_ANALYSIS_OP_TYPE_OR; c166_op_rn_rm(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_OR, true); break; case C166_ORB_Rbn_x: + op->type = RZ_ANALYSIS_OP_TYPE_OR; c166_op_rn_x(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_OR, true); break; - case C166_OR_mem_reg: case C166_OR_reg_data16: - case C166_OR_reg_mem: - case C166_ORB_mem_reg: case C166_ORB_reg_data8: - case C166_ORB_reg_mem: + case C166_OR_mem_reg: + case C166_ORB_mem_reg: + case C166_OR_reg_mem: + case C166_ORB_reg_mem: { op->type = RZ_ANALYSIS_OP_TYPE_OR; - c166_set_mimo_addr_from_reg(op, operand1); + const bool byte = buf[0] != C166_ADDB_mem_reg; + c166_op_src_mem_src_reg(analysis, op, instr, buf, byte); break; + } case C166_XOR_Rwn_Rwm: c166_op_rn_rm(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_XOR, false); break; @@ -980,15 +1038,19 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, case C166_XORB_Rbn_x: c166_op_rn_x(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_XOR, true); break; - case C166_XOR_mem_reg: + case C166_XORB_reg_data8: case C166_XOR_reg_data16: - case C166_XOR_reg_mem: + op->type = RZ_ANALYSIS_OP_TYPE_XOR; + break; + case C166_XOR_mem_reg: case C166_XORB_mem_reg: - case C166_XORB_reg_data8: - case C166_XORB_reg_mem: + case C166_XOR_reg_mem: + case C166_XORB_reg_mem: { op->type = RZ_ANALYSIS_OP_TYPE_XOR; - c166_set_mimo_addr_from_reg(op, operand1); + const bool byte = buf[0] != C166_ADDB_mem_reg; + c166_op_src_mem_src_reg(analysis, op, instr, buf, byte); break; + } case C166_NOP: op->type = RZ_ANALYSIS_OP_TYPE_NOP; break; @@ -1026,8 +1088,10 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, case C166_BSET_bitoff15: op->type = RZ_ANALYSIS_OP_TYPE_STORE; op->dst = c166_new_bitaddr_value(analysis, instr, operand1); - if (op->dst) - op->mmio_address = op->dst->base; + if (op->dst) { + op->mmios[op->mmios_count] = op->dst->base; + op->mmios_count++; + } break; case C166_BFLDH_bitoff_x: case C166_BFLDL_bitoff_x: @@ -1038,8 +1102,10 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, op->type = RZ_ANALYSIS_OP_TYPE_MOV; op->dst = c166_new_bitaddr_value(analysis, instr, operand1); op->src[0] = c166_new_bitaddr_value(analysis, instr, get_operand(instr, 2)); - if (op->dst) - op->mmio_address = op->dst->base; + if (op->dst) { + op->mmios[op->mmios_count] = op->dst->base; + op->mmios_count++; + } break; case C166_BCMP_bitaddr_bitaddr: op->type = RZ_ANALYSIS_OP_TYPE_CMP; @@ -1058,11 +1124,9 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, break; case C166_POP_reg: op->type = RZ_ANALYSIS_OP_TYPE_POP; - c166_set_mimo_addr_from_reg(op, operand1); break; case C166_PUSH_reg: op->type = RZ_ANALYSIS_OP_TYPE_PUSH; - c166_set_mimo_addr_from_reg(op, operand1); break; case C166_SHL_Rwn_Rwm: c166_op_rn_rm(analysis, op, operand1, RZ_ANALYSIS_OP_TYPE_SHL, false); @@ -1122,32 +1186,41 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, break; case C166_MOV_reg_data16: case C166_MOVB_reg_data8: - c166_op_mov_reg_data(analysis, op, buf); + c166_op_mov_reg_data(analysis, op, instr, buf); break; case C166_MOV_reg_mem: - case C166_MOVB_reg_mem: - c166_op_mov_reg_mem(analysis, op, instr, buf); + case C166_MOVB_reg_mem: { + op->type = RZ_ANALYSIS_OP_TYPE_MOV; + const bool byte = buf[0] != C166_MOV_reg_mem; + c166_op_dst_reg_src_mem(analysis, op, instr, buf, byte); break; + } case C166_MOV_mem_reg: case C166_MOVB_mem_reg: case C166_MOVBS_mem_reg: - case C166_MOVBZ_mem_reg: - c166_op_mov_mem_reg(analysis, op, instr, buf); + case C166_MOVBZ_mem_reg: { + op->type = RZ_ANALYSIS_OP_TYPE_MOV; + const bool byte = buf[0] != C166_MOV_reg_mem; + c166_op_dst_reg_src_mem(analysis, op, instr, buf, byte); break; + } case C166_MOV_mem_oRwn: case C166_MOVB_mem_oRwn: op->type = RZ_ANALYSIS_OP_TYPE_MOV; op->dst = c166_new_mem_value(analysis, instr, rz_read_at_le16(buf, 2)); if (op->dst) { - op->mmio_address = op->dst->base; + op->mmios[op->mmios_count] = op->dst->base; + op->mmios_count++; } break; case C166_MOV_oRwn_mem: case C166_MOVB_oRwn_mem: { op->type = RZ_ANALYSIS_OP_TYPE_MOV; op->src[0] = c166_new_mem_value(analysis, instr, rz_read_at_le16(buf, 2)); - if (op->src[0]) - op->mmio_address = op->src[0]->base; + if (op->src[0]) { + op->mmios[op->mmios_count] = op->src[0]->base; + op->mmios_count++; + } break; } case C166_NEG_Rwn: @@ -1190,14 +1263,14 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, case C166_CMPI2_Rwn_mem: op->type = RZ_ANALYSIS_OP_TYPE_CMP; op->reg = c166_rw[operand1 & 0xF]; - op->mmio_address = rz_read_at_le16(buf, 2); + op->mmios[op->mmios_count] = rz_read_at_le16(buf, 2); + op->mmios_count++; break; case C166_CMP_reg_data16: case C166_CMP_reg_mem: case C166_CMPB_reg_data8: case C166_CMPB_reg_mem: op->type = RZ_ANALYSIS_OP_TYPE_CMP; - c166_set_mimo_addr_from_reg(op, operand1); break; case C166_TRAP_trap7: c166_op_trap7(analysis, op, buf); @@ -1288,15 +1361,41 @@ static void c166_op_set_type(RZ_NONNULL C166_Inst *instr, RzAnalysis *analysis, op->type = RZ_ANALYSIS_OP_TYPE_UNK; break; case C166_BXOR_bitaddr_bitaddr: + op->type = RZ_ANALYSIS_OP_TYPE_XOR; + const ut8 qz = buf[3]; + + const ut8 q = H_NIB(qz); + const ut8 z = L_NIB(qz); + + if (IS_RAM(z)) { + op->mmios[op->mmios_count] = BASE_RAM_B_ADDR + (2 * z); + op->mmios_count++; + } + if (IS_RAM(q)) { + op->mmios[op->mmios_count] = BASE_RAM_B_ADDR + (2 * q); + op->mmios_count++; + } + break; case C166_BAND_bitaddr_bitaddr: + op->type = RZ_ANALYSIS_OP_TYPE_AND; + break; case C166_BOR_bitaddr_bitaddr: + op->type = RZ_ANALYSIS_OP_TYPE_XOR; break; case C166_CoXXX_83: - case C166_CoMOV: case C166_CoXXX_93: case C166_CoXXX_A3: + break; + case C166_CoMOV: + op->type = RZ_ANALYSIS_OP_TYPE_MOV; + break; case C166_CoSTORE_C3: case C166_CoSTORE_B3: + op->type = RZ_ANALYSIS_OP_TYPE_STORE; + const ut8 extID = get_operand(instr, 2); + const ut8 wwwww = (extID >> 3); + op->mmios[op->mmios_count] = CoREG(wwwww); + op->mmios_count++; break; default: RZ_LOG_DEBUG("c166_op_set_type 0x%02x\n", instr->id); @@ -1321,6 +1420,17 @@ static int c166_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 if (!state) { RZ_LOG_FATAL("C166State was NULL."); } + if (!state->inited) { + // rz_reg_setv(analysis->reg, "DPP0", 0x0); + // rz_reg_setv(analysis->reg, "DPP1", 0x1); + // rz_reg_setv(analysis->reg, "DPP2", 0x2); + // rz_reg_setv(analysis->reg, "DPP3", 0x3); + // rz_reg_setv(analysis->reg, "SP", 0xFC00); + // rz_reg_setv(analysis->reg, "CP", 0xFC00); + // rz_reg_setv(analysis->reg, "STKOV", 0xFA00); + // rz_reg_setv(analysis->reg, "STKUN", 0xFC00); + state->inited = true; + } C166_Inst instr = { 0 }; instr.addr = (ut32)addr; @@ -1347,32 +1457,47 @@ static int c166_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 return op->size; } if (RZ_STR_ISEMPTY(instr.instr)) + if (RZ_STR_ISEMPTY(instr.instr)) { RZ_LOG_DEBUG("instr.addr: 0x%04x [0x%02x]\n", instr.addr, instr.id); + } rz_warn_if_fail(RZ_STR_ISNOTEMPTY(instr.instr)); rz_warn_if_fail(ret == 1 || ret == 2 || ret == 4); op->size = ret; + // op->jump = op->addr + op->size; + // SET_A_IP(op->jump); + // SET_A_IP(op->addr); + c166_op_set_type(&instr, analysis, op, buf); if (mask & RZ_ANALYSIS_OP_MASK_DISASM) { op->mnemonic = rz_str_newf("%s%s%s", instr.instr, RZ_STR_ISNOTEMPTY(instr.operands) ? " " : "", instr.operands); } - c166_op_set_type(&instr, analysis, op, buf); + // set RzIL + if (mask & RZ_ANALYSIS_OP_MASK_IL) { + rz_c166_il_opcode(analysis, op, addr, buf); + if (addr == 0x9a) exit(0); + } + c166_maybe_deactivate_ext(state, instr.addr); + return op->size; } static char *get_reg_profile(RzAnalysis *analysis) { const char *p = "=PC IP\n" + // "=IP PC\n" "=SP SP\n" "=A0 r8\n" "=A1 r9\n" "=A2 r10\n" "=A3 r11\n" + // "gpr PC .32 0 0\n" "gpr IP .32 0 0\n" + "gpr r0 .16 65040 0\n" // FE10 == CP "gpr r1 .16 65042 0\n" "gpr r2 .16 65044 0\n" @@ -1408,13 +1533,13 @@ static char *get_reg_profile(RzAnalysis *analysis) { "gpr rl7 .8 65054 0\n" "gpr rh7 .8 65055 0\n" - "seg DPP0 .10 65024 0\n" ///< FE00; CPU Data Page Pointer 0 Register (10 bits) - "seg DPP1 .10 65026 0\n" ///< FE02; CPU Data Page Pointer 1 Register (10 bits) - "seg DPP2 .10 65028 0\n" ///< FE04; CPU Data Page Pointer 2 Register (10 bits) - "seg DPP3 .10 65030 0\n" ///< FE06; CPU Data Page Pointer 3 Register (10 bits) + "gpr DPP0 .10 65024 0\n" ///< FE00; CPU Data Page Pointer 0 Register (10 bits) + "gpr DPP1 .10 65026 0\n" ///< FE02; CPU Data Page Pointer 1 Register (10 bits) + "gpr DPP2 .10 65028 0\n" ///< FE04; CPU Data Page Pointer 2 Register (10 bits) + "gpr DPP3 .10 65030 0\n" ///< FE06; CPU Data Page Pointer 3 Register (10 bits) "gpr CSP .8 65032 0\n" ///< FE08; CPU Code Segment Pointer Register (8 bits, read only) - "gpr r_FE0A .16 65034 0\n" ///< FE0A; RESERVED + // "gpr r_FE0A .16 65034 0\n" ///< FE0A; RESERVED "gpr MDH .16 65036 0\n" ///< FE0C; CPU Multiply Divide Register - High Word "gpr MDL .16 65038 0\n" ///< FE0E; CPU Multiply Divide Register - Low Word "gpr CP .16 65040 0\n" ///< FE10; CPU Context Pointer Register @@ -1429,129 +1554,129 @@ static char *get_reg_profile(RzAnalysis *analysis) { "flg BP .1 65048.1 0\n" ///< CPU Core: Enable Branch Prediction Unit "flg ZCJ .1 65048.0 0\n" ///< CPU Core: Enable Zero Cycle Jump function "gpr CPUCON2 .16 65050 0\n" ///< FE1A; CPU Core Control Register 2 - "gpr r_FE1C .16 65052 0\n" ///< FE1C; RESERVED - "gpr r_FE1E .16 65054 0\n" ///< FE1E; RESERVED - "gpr r_FE20 .16 65056 0\n" ///< FE20; RESERVED - "gpr r_FE22 .16 65058 0\n" ///< FE22; RESERVED - "gpr r_FE24 .16 65060 0\n" ///< FE24; RESERVED - "gpr r_FE26 .16 65062 0\n" ///< FE26; RESERVED - "gpr r_FE28 .16 65064 0\n" ///< FE28; RESERVED - "gpr r_FE2A .16 65066 0\n" ///< FE2A; RESERVED - "gpr r_FE2C .16 65068 0\n" ///< FE2C; RESERVED - "gpr r_FE2E .16 65070 0\n" ///< FE2E; RESERVED - "gpr r_FE30 .16 65072 0\n" ///< FE30; RESERVED - "gpr r_FE32 .16 65074 0\n" ///< FE32; RESERVED - "gpr r_FE34 .16 65076 0\n" ///< FE34; RESERVED - "gpr r_FE36 .16 65078 0\n" ///< FE36; RESERVED - "gpr r_FE38 .16 65080 0\n" ///< FE38; RESERVED - "gpr r_FE3A .16 65082 0\n" ///< FE3A; RESERVED - "gpr r_FE3C .16 65084 0\n" ///< FE3C; RESERVED - "gpr r_FE3E .16 65086 0\n" ///< FE3E; RESERVED + // "gpr r_FE1C .16 65052 0\n" ///< FE1C; RESERVED + // "gpr r_FE1E .16 65054 0\n" ///< FE1E; RESERVED + // "gpr r_FE20 .16 65056 0\n" ///< FE20; RESERVED + // "gpr r_FE22 .16 65058 0\n" ///< FE22; RESERVED + // "gpr r_FE24 .16 65060 0\n" ///< FE24; RESERVED + // "gpr r_FE26 .16 65062 0\n" ///< FE26; RESERVED + // "gpr r_FE28 .16 65064 0\n" ///< FE28; RESERVED + // "gpr r_FE2A .16 65066 0\n" ///< FE2A; RESERVED + // "gpr r_FE2C .16 65068 0\n" ///< FE2C; RESERVED + // "gpr r_FE2E .16 65070 0\n" ///< FE2E; RESERVED + // "gpr r_FE30 .16 65072 0\n" ///< FE30; RESERVED + // "gpr r_FE32 .16 65074 0\n" ///< FE32; RESERVED + // "gpr r_FE34 .16 65076 0\n" ///< FE34; RESERVED + // "gpr r_FE36 .16 65078 0\n" ///< FE36; RESERVED + // "gpr r_FE38 .16 65080 0\n" ///< FE38; RESERVED + // "gpr r_FE3A .16 65082 0\n" ///< FE3A; RESERVED + // "gpr r_FE3C .16 65084 0\n" ///< FE3C; RESERVED + // "gpr r_FE3E .16 65086 0\n" ///< FE3E; RESERVED "gpr T2 .16 65088 0\n" ///< FE40; GPT1 Timer 2 Register "gpr T3 .16 65090 0\n" ///< FE42; GPT1 Timer 3 Register "gpr T4 .16 65092 0\n" ///< FE44; GPT1 Timer 4 Register "gpr T5 .16 65094 0\n" ///< FE46; GPT2 Timer 5 Register "gpr T6 .16 65096 0\n" ///< FE48; GPT2 Timer 6 Register "gpr CAPREL .16 65098 0\n" ///< FE4A; GPT2 Capture/Reload Register - "gpr r_FE4C .16 65100 0\n" ///< FE4C; RESERVED - "gpr r_FE4E .16 65102 0\n" ///< FE4E; RESERVED + // "gpr r_FE4C .16 65100 0\n" ///< FE4C; RESERVED + // "gpr r_FE4E .16 65102 0\n" ///< FE4E; RESERVED "gpr T0 .16 65104 0\n" ///< FE50; CAPCOM Timer 0 Register "gpr T1 .16 65106 0\n" ///< FE52; CAPCOM Timer 1 Register "gpr T0REL .16 65108 0\n" ///< FE54; CAPCOM Timer 0 Reload Register "gpr T1REL .16 65110 0\n" ///< FE56; CAPCOM Timer 1 Reload Register - "gpr r_FE58 .16 65112 0\n" ///< FE58; RESERVED - "gpr r_FE5A .16 65114 0\n" ///< FE5A; RESERVED - "gpr r_FE5C .16 65116 0\n" ///< FE5C; RESERVED - "gpr r_FE5E .16 65118 0\n" ///< FE5E; RESERVED - "gpr r_FE60 .16 65120 0\n" ///< FE60; RESERVED - "gpr r_FE62 .16 65122 0\n" ///< FE62; RESERVED - "gpr r_FE64 .16 65124 0\n" ///< FE64; RESERVED - "gpr r_FE66 .16 65126 0\n" ///< FE66; RESERVED - "gpr r_FE68 .16 65128 0\n" ///< FE68; RESERVED - "gpr r_FE6A .16 65130 0\n" ///< FE6A; RESERVED - "gpr r_FE6C .16 65132 0\n" ///< FE6C; RESERVED - "gpr r_FE6E .16 65134 0\n" ///< FE6E; RESERVED - "gpr r_FE70 .16 65136 0\n" ///< FE70; RESERVED - "gpr r_FE72 .16 65138 0\n" ///< FE72; RESERVED - "gpr r_FE74 .16 65140 0\n" ///< FE74; RESERVED - "gpr r_FE76 .16 65142 0\n" ///< FE76; RESERVED - "gpr r_FE78 .16 65144 0\n" ///< FE78; RESERVED - "gpr r_FE7A .16 65146 0\n" ///< FE7A; RESERVED - "gpr r_FE7C .16 65148 0\n" ///< FE7C; RESERVED - "gpr CC31 .16 65150 0\n" ///< FE7E; CAPCOM 2 Register 31 - "gpr CC0 .16 65152 0\n" ///< FE80; CAPCOM Register 0 - "gpr CC1 .16 65154 0\n" ///< FE82; CAPCOM Register 1 - "gpr CC2 .16 65156 0\n" ///< FE84; CAPCOM Register 2 - "gpr CC3 .16 65158 0\n" ///< FE86; CAPCOM Register 3 - "gpr CC4 .16 65160 0\n" ///< FE88; CAPCOM Register 4 - "gpr CC5 .16 65162 0\n" ///< FE8A; CAPCOM Register 5 - "gpr CC6 .16 65164 0\n" ///< FE8C; CAPCOM Register 6 - "gpr CC7 .16 65166 0\n" ///< FE8E; CAPCOM Register 7 - "gpr CC8 .16 65168 0\n" ///< FE90; CAPCOM Register 8 - "gpr CC9 .16 65170 0\n" ///< FE92; CAPCOM Register 9 - "gpr CC10 .16 65172 0\n" ///< FE94; CAPCOM Register 10 - "gpr CC11 .16 65174 0\n" ///< FE96; CAPCOM Register 11 - "gpr CC12 .16 65176 0\n" ///< FE98; CAPCOM Register 12 - "gpr CC13 .16 65178 0\n" ///< FE9A; CAPCOM Register 13 - "gpr CC14 .16 65180 0\n" ///< FE9C; CAPCOM Register 14 - "gpr CC15 .16 65182 0\n" ///< FE9E; CAPCOM Register 15 + // "gpr r_FE58 .16 65112 0\n" ///< FE58; RESERVED + // "gpr r_FE5A .16 65114 0\n" ///< FE5A; RESERVED + // "gpr r_FE5C .16 65116 0\n" ///< FE5C; RESERVED + // "gpr r_FE5E .16 65118 0\n" ///< FE5E; RESERVED + // "gpr r_FE60 .16 65120 0\n" ///< FE60; RESERVED + // "gpr r_FE62 .16 65122 0\n" ///< FE62; RESERVED + // "gpr r_FE64 .16 65124 0\n" ///< FE64; RESERVED + // "gpr r_FE66 .16 65126 0\n" ///< FE66; RESERVED + // "gpr r_FE68 .16 65128 0\n" ///< FE68; RESERVED + // "gpr r_FE6A .16 65130 0\n" ///< FE6A; RESERVED + // "gpr r_FE6C .16 65132 0\n" ///< FE6C; RESERVED + // "gpr r_FE6E .16 65134 0\n" ///< FE6E; RESERVED + // "gpr r_FE70 .16 65136 0\n" ///< FE70; RESERVED + // "gpr r_FE72 .16 65138 0\n" ///< FE72; RESERVED + // "gpr r_FE74 .16 65140 0\n" ///< FE74; RESERVED + // "gpr r_FE76 .16 65142 0\n" ///< FE76; RESERVED + // "gpr r_FE78 .16 65144 0\n" ///< FE78; RESERVED + // "gpr r_FE7A .16 65146 0\n" ///< FE7A; RESERVED + // "gpr r_FE7C .16 65148 0\n" ///< FE7C; RESERVED + // "gpr CC31 .16 65150 0\n" ///< FE7E; CAPCOM 2 Register 31 + // "gpr CC0 .16 65152 0\n" ///< FE80; CAPCOM Register 0 + // "gpr CC1 .16 65154 0\n" ///< FE82; CAPCOM Register 1 + // "gpr CC2 .16 65156 0\n" ///< FE84; CAPCOM Register 2 + // "gpr CC3 .16 65158 0\n" ///< FE86; CAPCOM Register 3 + // "gpr CC4 .16 65160 0\n" ///< FE88; CAPCOM Register 4 + // "gpr CC5 .16 65162 0\n" ///< FE8A; CAPCOM Register 5 + // "gpr CC6 .16 65164 0\n" ///< FE8C; CAPCOM Register 6 + // "gpr CC7 .16 65166 0\n" ///< FE8E; CAPCOM Register 7 + // "gpr CC8 .16 65168 0\n" ///< FE90; CAPCOM Register 8 + // "gpr CC9 .16 65170 0\n" ///< FE92; CAPCOM Register 9 + // "gpr CC10 .16 65172 0\n" ///< FE94; CAPCOM Register 10 + // "gpr CC11 .16 65174 0\n" ///< FE96; CAPCOM Register 11 + // "gpr CC12 .16 65176 0\n" ///< FE98; CAPCOM Register 12 + // "gpr CC13 .16 65178 0\n" ///< FE9A; CAPCOM Register 13 + // "gpr CC14 .16 65180 0\n" ///< FE9C; CAPCOM Register 14 + // "gpr CC15 .16 65182 0\n" ///< FE9E; CAPCOM Register 15 "gpr ADDAT .16 65184 0\n" ///< FEA0; A/D Converter Result Register - "gpr r_FEA2 .16 65186 0\n" ///< FEA2; RESERVED - "gpr r_FEA4 .16 65188 0\n" ///< FEA4; RESERVED - "gpr r_FEA6 .16 65190 0\n" ///< FEA6; RESERVED - "gpr r_FEA8 .16 65192 0\n" ///< FEA8; RESERVED - "gpr r_FEAA .16 65194 0\n" ///< FEAA; RESERVED - "gpr r_FEAC .16 65196 0\n" ///< FEAC; RESERVED + // "gpr r_FEA2 .16 65186 0\n" ///< FEA2; RESERVED + // "gpr r_FEA4 .16 65188 0\n" ///< FEA4; RESERVED + // "gpr r_FEA6 .16 65190 0\n" ///< FEA6; RESERVED + // "gpr r_FEA8 .16 65192 0\n" ///< FEA8; RESERVED + // "gpr r_FEAA .16 65194 0\n" ///< FEAA; RESERVED + // "gpr r_FEAC .16 65196 0\n" ///< FEAC; RESERVED "gpr WDT .16 65198 0\n" ///< FEAE; Watchdog Timer Register (read only) - "gpr S0TBUF .16 65200 0\n" ///< FEB0; Serial Channel 0 Transmit Buffer Register - "gpr S0RBUF .16 65202 0\n" ///< FEB2; Serial Channel 0 Receive Buffer Register (read only) - "gpr S0BG .16 65204 0\n" ///< FEB4; Serial Channel 0 Baud Rate Generator Reload Register + // "gpr S0TBUF .16 65200 0\n" ///< FEB0; Serial Channel 0 Transmit Buffer Register + // "gpr S0RBUF .16 65202 0\n" ///< FEB2; Serial Channel 0 Receive Buffer Register (read only) + // "gpr S0BG .16 65204 0\n" ///< FEB4; Serial Channel 0 Baud Rate Generator Reload Register // "gpr .8 65206 0\n" // FEB6; // "gpr .8 65207 0\n" // FEB7; - "gpr S1TBUF .16 65208 0\n" ///< FEB8; Serial Channel 1 Transmit Buffer Register - "gpr S1RBUF .16 65210 0\n" ///< FEBA; Serial Channel 1 Receive Buffer Register - "gpr S1BG .16 65212 0\n" ///< FEBC; Serial Channel 1 Baud Rate Generator/Reload Register - "gpr r_FEBE .16 65214 0\n" ///< FEBE; RESERVED - "gpr PECC0 .16 65216 0\n" ///< FEC0; PEC Channel 0 Control Register - "gpr PECC1 .16 65218 0\n" ///< FEC2; PEC Channel 1 Control Register - "gpr PECC2 .16 65220 0\n" ///< FEC4; PEC Channel 2 Control Register - "gpr PECC3 .16 65222 0\n" ///< FEC6; PEC Channel 3 Control Register - "gpr PECC4 .16 65224 0\n" ///< FEC8; PEC Channel 4 Control Register - "gpr PECC5 .16 65226 0\n" ///< FECA; PEC Channel 5 Control Register - "gpr PECC6 .16 65228 0\n" ///< FECC; PEC Channel 6 Control Register - "gpr PECC7 .16 65230 0\n" ///< FECE; PEC Channel 7 Control Register - "gpr r_FED0 .16 65232 0\n" ///< FED0; RESERVED - "gpr r_FED2 .16 65234 0\n" ///< FED2; RESERVED - "gpr r_FED4 .16 65236 0\n" ///< FED4; RESERVED - "gpr r_FED6 .16 65238 0\n" ///< FED6; RESERVED - "gpr r_FED8 .16 65240 0\n" ///< FED8; RESERVED - "gpr r_FEDA .16 65242 0\n" ///< FEDA; RESERVED - "gpr r_FEDC .16 65244 0\n" ///< FEDC; RESERVED - "gpr r_FEDE .16 65246 0\n" ///< FEDE; RESERVED - "gpr r_FEE0 .16 65248 0\n" ///< FEE0; RESERVED - "gpr r_FEE2 .16 65250 0\n" ///< FEE2; RESERVED - "gpr r_FEE4 .16 65252 0\n" ///< FEE4; RESERVED - "gpr r_FEE6 .16 65254 0\n" ///< FEE6; RESERVED - "gpr r_FEE8 .16 65256 0\n" ///< FEE8; RESERVED - "gpr r_FEEA .16 65258 0\n" ///< FEEA; RESERVED - "gpr r_FEEC .16 65260 0\n" ///< FEEC; RESERVED - "gpr r_FEEE .16 65262 0\n" ///< FEEE; RESERVED - "gpr r_FEF0 .16 65264 0\n" ///< FEF0; RESERVED - "gpr r_FEF2 .16 65266 0\n" ///< FEF2; RESERVED - "gpr r_FEF4 .16 65268 0\n" ///< FEF4; RESERVED - "gpr r_FEF6 .16 65270 0\n" ///< FEF6; RESERVED - "gpr r_FEF8 .16 65272 0\n" ///< FEF8; RESERVED - "gpr r_FEFA .16 65274 0\n" ///< FEFA; RESERVED - "gpr r_FEFC .16 65276 0\n" ///< FEFC; RESERVED - "gpr r_FEFE .16 65278 0\n" ///< FEFE; RESERVED - "gpr P0 .16 65280 0\n" ///< FF00; Port 0 Register - "gpr DP0 .16 65282 0\n" ///< FF02; Port 0 Direction Control Register - "gpr P1 .16 65284 0\n" ///< FF04; Port 1 Register - "gpr DP1 .16 65286 0\n" ///< FF06; Port 1 Direction Control Register - "gpr P4 .16 65288 0\n" ///< FF08; Port 4 Register (7 bits) - "gpr DP4 .16 65290 0\n" ///< FF0A; Port 4 Direction Control Register + // "gpr S1TBUF .16 65208 0\n" ///< FEB8; Serial Channel 1 Transmit Buffer Register + // "gpr S1RBUF .16 65210 0\n" ///< FEBA; Serial Channel 1 Receive Buffer Register + // "gpr S1BG .16 65212 0\n" ///< FEBC; Serial Channel 1 Baud Rate Generator/Reload Register + // "gpr r_FEBE .16 65214 0\n" ///< FEBE; RESERVED + // "gpr PECC0 .16 65216 0\n" ///< FEC0; PEC Channel 0 Control Register + // "gpr PECC1 .16 65218 0\n" ///< FEC2; PEC Channel 1 Control Register + // "gpr PECC2 .16 65220 0\n" ///< FEC4; PEC Channel 2 Control Register + // "gpr PECC3 .16 65222 0\n" ///< FEC6; PEC Channel 3 Control Register + // "gpr PECC4 .16 65224 0\n" ///< FEC8; PEC Channel 4 Control Register + // "gpr PECC5 .16 65226 0\n" ///< FECA; PEC Channel 5 Control Register + // "gpr PECC6 .16 65228 0\n" ///< FECC; PEC Channel 6 Control Register + // "gpr PECC7 .16 65230 0\n" ///< FECE; PEC Channel 7 Control Register + // "gpr r_FED0 .16 65232 0\n" ///< FED0; RESERVED + // "gpr r_FED2 .16 65234 0\n" ///< FED2; RESERVED + // "gpr r_FED4 .16 65236 0\n" ///< FED4; RESERVED + // "gpr r_FED6 .16 65238 0\n" ///< FED6; RESERVED + // "gpr r_FED8 .16 65240 0\n" ///< FED8; RESERVED + // "gpr r_FEDA .16 65242 0\n" ///< FEDA; RESERVED + // "gpr r_FEDC .16 65244 0\n" ///< FEDC; RESERVED + // "gpr r_FEDE .16 65246 0\n" ///< FEDE; RESERVED + // "gpr r_FEE0 .16 65248 0\n" ///< FEE0; RESERVED + // "gpr r_FEE2 .16 65250 0\n" ///< FEE2; RESERVED + // "gpr r_FEE4 .16 65252 0\n" ///< FEE4; RESERVED + // "gpr r_FEE6 .16 65254 0\n" ///< FEE6; RESERVED + // "gpr r_FEE8 .16 65256 0\n" ///< FEE8; RESERVED + // "gpr r_FEEA .16 65258 0\n" ///< FEEA; RESERVED + // "gpr r_FEEC .16 65260 0\n" ///< FEEC; RESERVED + // "gpr r_FEEE .16 65262 0\n" ///< FEEE; RESERVED + // "gpr r_FEF0 .16 65264 0\n" ///< FEF0; RESERVED + // "gpr r_FEF2 .16 65266 0\n" ///< FEF2; RESERVED + // "gpr r_FEF4 .16 65268 0\n" ///< FEF4; RESERVED + // "gpr r_FEF6 .16 65270 0\n" ///< FEF6; RESERVED + // "gpr r_FEF8 .16 65272 0\n" ///< FEF8; RESERVED + // "gpr r_FEFA .16 65274 0\n" ///< FEFA; RESERVED + // "gpr r_FEFC .16 65276 0\n" ///< FEFC; RESERVED + // "gpr r_FEFE .16 65278 0\n" ///< FEFE; RESERVED + // "gpr P0 .16 65280 0\n" ///< FF00; Port 0 Register + // "gpr DP0 .16 65282 0\n" ///< FF02; Port 0 Direction Control Register + // "gpr P1 .16 65284 0\n" ///< FF04; Port 1 Register + // "gpr DP1 .16 65286 0\n" ///< FF06; Port 1 Direction Control Register + // "gpr P4 .16 65288 0\n" ///< FF08; Port 4 Register (7 bits) + // "gpr DP4 .16 65290 0\n" ///< FF0A; Port 4 Direction Control Register "gpr SYSCON .16 65292 0\n" ///< FF0C; CPU System Configuration Register "gpr MDC .16 65294 0\n" ///< FF0E; CPU Multiply/ Divide Control Register "gpr PSW .16 65296 0\n" ///< FF10; CPU Program Status Word @@ -1560,108 +1685,108 @@ static char *get_reg_profile(RzAnalysis *analysis) { "flg v .1 65296.2 0\n" "flg c .1 65296.1 0\n" "flg n .1 65296.0 0\n" - "gpr r_FF12 .16 65298 0\n" ///< FF12; RESERVED - "gpr r_FF14 .16 65300 0\n" ///< FF14; RESERVED - "gpr r_FF16 .16 65302 0\n" ///< FF16; RESERVED - "gpr r_FF18 .16 65304 0\n" ///< FF18; RESERVED - "gpr r_FF1A .16 65306 0\n" ///< FF1A; RESERVED + "gpr BUSCON0 .16 65298 0\n" ///< FF12; RESERVED + "gpr BUSCON1 .16 65300 0\n" ///< FF14; RESERVED + "gpr BUSCON2 .16 65302 0\n" ///< FF16; RESERVED + "gpr BUSCON3 .16 65304 0\n" ///< FF18; RESERVED + "gpr BUSCON4 .16 65306 0\n" ///< FF1A; RESERVED "gpr ZEROS .16 65308 0\n" ///< FF1C; Constant Value 0's Register (read only) "gpr ONES .16 65310 0\n" ///< FF1E; Constant Value 1's Register (read only) - "gpr r_FF20 .16 65312 0\n" ///< FF20; RESERVED - "gpr r_FF22 .16 65314 0\n" ///< FF22; RESERVED - "gpr r_FF24 .16 65316 0\n" ///< FF24; RESERVED - "gpr r_FF26 .16 65318 0\n" ///< FF26; RESERVED - "gpr r_FF28 .16 65320 0\n" ///< FF28; RESERVED - "gpr r_FF2A .16 65322 0\n" ///< FF2A; RESERVED - "gpr r_FF2C .16 65324 0\n" ///< FF2C; RESERVED - "gpr r_FF2E .16 65326 0\n" ///< FF2E; RESERVED - "gpr r_FF30 .16 65328 0\n" ///< FF30; RESERVED - "gpr r_FF32 .16 65330 0\n" ///< FF32; RESERVED - "gpr r_FF34 .16 65332 0\n" ///< FF34; RESERVED - "gpr r_FF36 .16 65334 0\n" ///< FF36; RESERVED - "gpr r_FF38 .16 65336 0\n" ///< FF38; RESERVED - "gpr r_FF3A .16 65338 0\n" ///< FF3A; RESERVED - "gpr r_FF3C .16 65340 0\n" ///< FF3C; RESERVED - "gpr r_FF3E .16 65342 0\n" ///< FF3E; RESERVED - "gpr T2CON .16 65344 0\n" ///< FF40; GPT1 Timer 2 Control Register - "gpr T3CON .16 65346 0\n" ///< FF42; GPT1 Timer 3 Control Register - "gpr T4CON .16 65348 0\n" ///< FF44; GPT1 Timer 4 Control Register - "gpr T5CON .16 65350 0\n" ///< FF46; GPT2 Timer 5 Control Register - "gpr T6CON .16 65352 0\n" ///< FF48; GPT2 Timer 6 Control Register - "gpr r_FF4A .16 65354 0\n" ///< FF4A; RESERVED - "gpr r_FF4C .16 65356 0\n" ///< FF4C; RESERVED - "gpr r_FF4E .16 65358 0\n" ///< FF4E; RESERVED - "gpr T01CON .16 65360 0\n" ///< FF50; CAPCOM Timer 0 and Timer 1 Ctrl. Reg. - "gpr CCM0 .16 65362 0\n" ///< FF52; CAPCOM Mode Control Register 0 - "gpr CCM1 .16 65364 0\n" ///< FF54; CAPCOM Mode Control Register 1 - "gpr CCM2 .16 65366 0\n" ///< FF56; CAPCOM Mode Control Register 2 - "gpr CCM3 .16 65368 0\n" ///< FF58; CAPCOM Mode Control Register 3 - "gpr r_FF5A .16 65370 0\n" ///< FF5A; RESERVED - "gpr r_FF5C .16 65372 0\n" ///< FF5C; RESERVED - "gpr r_FF5E .16 65374 0\n" ///< FF5E; RESERVED - - "gpr T2IC .16 65376 0\n" ///< FF60; GPT1 Timer 2 Interrupt Control Register - "gpr T3IC .16 65378 0\n" ///< FF62; GPT1 Timer 3 Interrupt Control Register - "gpr T4IC .16 65380 0\n" ///< FF64; GPT1 Timer 4 Interrupt Control Register - "gpr T5IC .16 65382 0\n" ///< FF66; GPT2 Timer 5 Interrupt Control Register - "gpr T6IC .16 65384 0\n" ///< FF68; GPT2 Timer 6 Interrupt Control Register - "gpr CRIC .16 65386 0\n" ///< FF6A; GPT2 CAPREL Interrupt Control Register - "gpr S0TIC .16 65388 0\n" ///< FF6C; Serial Channel 0 Transmit Interrupt Control Register - "gpr S0RIC .16 65390 0\n" ///< FF6E; Serial Channel 0 Receive Interrupt Control Register - "gpr S0EIC .16 65392 0\n" ///< FF70; Serial Channel 0 Error Interrupt Ctrl. Reg. - "gpr S1TIC .16 65394 0\n" ///< FF72; Serial Channel 1 Transmit Interrupt Control - "gpr S1RIC .16 65396 0\n" ///< FF74; Serial Channel 1 Receive Interrupt Control - "gpr S1EIC .16 65398 0\n" ///< FF76; Serial Channel 1 Error Interrupt control - "gpr CC0IC .16 65400 0\n" ///< FF78; CAPCOM Register 0 Interrupt Ctrl. Reg. - "gpr CC1IC .16 65402 0\n" ///< FF7A; CAPCOM Register 1 Interrupt Ctrl. Reg. - "gpr CC2IC .16 65404 0\n" ///< FF7C; CAPCOM Register 2 Interrupt Ctrl. Reg. - "gpr CC3IC .16 65406 0\n" ///< FF7E; CAPCOM Register 3 Interrupt Ctrl. Reg. - "gpr CC4IC .16 65408 0\n" ///< FF80; CAPCOM Register 4 Interrupt Ctrl. Reg. - "gpr CC5IC .16 65410 0\n" ///< FF82; CAPCOM Register 5 Interrupt Ctrl. Reg. - "gpr CC6IC .16 65412 0\n" ///< FF84; CAPCOM Register 6Interrupt Ctrl. Reg. - "gpr CC7IC .16 65414 0\n" ///< FF86; CAPCOM Register 7 Interrupt Ctrl. Reg. - "gpr CC8IC .16 65416 0\n" ///< FF88; CAPCOM Register 8 Interrupt Ctrl. Reg. - "gpr CC9IC .16 65418 0\n" ///< FF8A; CAPCOM Register 9 Interrupt Ctrl. Reg. - "gpr CC10IC .16 65420 0\n" ///< FF8C; CAPCOM Register 10 Interrupt Ctrl. Reg. - "gpr CC11IC .16 65422 0\n" ///< FF8E; CAPCOM Register 11 Interrupt Ctrl. Reg. - "gpr CC12IC .16 65424 0\n" ///< FF90; CAPCOM Register 12 Interrupt Ctrl. Reg. - "gpr CC13IC .16 65426 0\n" ///< FF92; CAPCOM Register 13 Interrupt Ctrl. Reg. - "gpr CC14IC .16 65428 0\n" ///< FF94; CAPCOM Register 14 Interrupt Ctrl. Reg. - "gpr CC15IC .16 65430 0\n" ///< FF96; CAPCOM Register 15 Interrupt Ctrl. Reg. - "gpr ADCIC .16 65432 0\n" ///< FF98; A/D Converter End of Conversion Interrupt Control Register - "gpr ADEIC .16 65434 0\n" ///< FF9A; A/D Converter Overrun Error Interrupt Control Register - "gpr T0IC .16 65436 0\n" ///< FF9C; CAPCOM Timer 0 Interrupt Ctrl. Reg. - "gpr T1IC .16 65438 0\n" ///< FF9E; CAPCOM Timer 1 Interrupt Ctrl. Reg. - "gpr ADCON .16 65440 0\n" ///< FFA0; A/D Converter Control Register - "gpr P5 .16 65442 0\n" ///< FFA2; Port 5 Register (read only) - "gpr r_FFA4 .16 65444 0\n" ///< FFA4; RESERVED - "gpr r_FFA6 .16 65446 0\n" ///< FFA6; RESERVED - "gpr r_FFA8 .16 65448 0\n" ///< FFA8; RESERVED - "gpr r_FFAA .16 65450 0\n" ///< FFAA; RESERVED + // "gpr r_FF20 .16 65312 0\n" ///< FF20; RESERVED + // "gpr r_FF22 .16 65314 0\n" ///< FF22; RESERVED + // "gpr r_FF24 .16 65316 0\n" ///< FF24; RESERVED + // "gpr r_FF26 .16 65318 0\n" ///< FF26; RESERVED + // "gpr r_FF28 .16 65320 0\n" ///< FF28; RESERVED + // "gpr r_FF2A .16 65322 0\n" ///< FF2A; RESERVED + // "gpr r_FF2C .16 65324 0\n" ///< FF2C; RESERVED + // "gpr r_FF2E .16 65326 0\n" ///< FF2E; RESERVED + // "gpr r_FF30 .16 65328 0\n" ///< FF30; RESERVED + // "gpr r_FF32 .16 65330 0\n" ///< FF32; RESERVED + // "gpr r_FF34 .16 65332 0\n" ///< FF34; RESERVED + // "gpr r_FF36 .16 65334 0\n" ///< FF36; RESERVED + // "gpr r_FF38 .16 65336 0\n" ///< FF38; RESERVED + // "gpr r_FF3A .16 65338 0\n" ///< FF3A; RESERVED + // "gpr r_FF3C .16 65340 0\n" ///< FF3C; RESERVED + // "gpr r_FF3E .16 65342 0\n" ///< FF3E; RESERVED + // "gpr T2CON .16 65344 0\n" ///< FF40; GPT1 Timer 2 Control Register + // "gpr T3CON .16 65346 0\n" ///< FF42; GPT1 Timer 3 Control Register + // "gpr T4CON .16 65348 0\n" ///< FF44; GPT1 Timer 4 Control Register + // "gpr T5CON .16 65350 0\n" ///< FF46; GPT2 Timer 5 Control Register + // "gpr T6CON .16 65352 0\n" ///< FF48; GPT2 Timer 6 Control Register + // "gpr r_FF4A .16 65354 0\n" ///< FF4A; RESERVED + // "gpr r_FF4C .16 65356 0\n" ///< FF4C; RESERVED + // "gpr r_FF4E .16 65358 0\n" ///< FF4E; RESERVED + // "gpr T01CON .16 65360 0\n" ///< FF50; CAPCOM Timer 0 and Timer 1 Ctrl. Reg. + // "gpr CCM0 .16 65362 0\n" ///< FF52; CAPCOM Mode Control Register 0 + // "gpr CCM1 .16 65364 0\n" ///< FF54; CAPCOM Mode Control Register 1 + // "gpr CCM2 .16 65366 0\n" ///< FF56; CAPCOM Mode Control Register 2 + // "gpr CCM3 .16 65368 0\n" ///< FF58; CAPCOM Mode Control Register 3 + // "gpr r_FF5A .16 65370 0\n" ///< FF5A; RESERVED + // "gpr r_FF5C .16 65372 0\n" ///< FF5C; RESERVED + // "gpr r_FF5E .16 65374 0\n" ///< FF5E; RESERVED + + // "gpr T2IC .16 65376 0\n" ///< FF60; GPT1 Timer 2 Interrupt Control Register + // "gpr T3IC .16 65378 0\n" ///< FF62; GPT1 Timer 3 Interrupt Control Register + // "gpr T4IC .16 65380 0\n" ///< FF64; GPT1 Timer 4 Interrupt Control Register + // "gpr T5IC .16 65382 0\n" ///< FF66; GPT2 Timer 5 Interrupt Control Register + // "gpr T6IC .16 65384 0\n" ///< FF68; GPT2 Timer 6 Interrupt Control Register + // "gpr CRIC .16 65386 0\n" ///< FF6A; GPT2 CAPREL Interrupt Control Register + // "gpr S0TIC .16 65388 0\n" ///< FF6C; Serial Channel 0 Transmit Interrupt Control Register + // "gpr S0RIC .16 65390 0\n" ///< FF6E; Serial Channel 0 Receive Interrupt Control Register + // "gpr S0EIC .16 65392 0\n" ///< FF70; Serial Channel 0 Error Interrupt Ctrl. Reg. + // "gpr S1TIC .16 65394 0\n" ///< FF72; Serial Channel 1 Transmit Interrupt Control + // "gpr S1RIC .16 65396 0\n" ///< FF74; Serial Channel 1 Receive Interrupt Control + // "gpr S1EIC .16 65398 0\n" ///< FF76; Serial Channel 1 Error Interrupt control + // "gpr CC0IC .16 65400 0\n" ///< FF78; CAPCOM Register 0 Interrupt Ctrl. Reg. + // "gpr CC1IC .16 65402 0\n" ///< FF7A; CAPCOM Register 1 Interrupt Ctrl. Reg. + // "gpr CC2IC .16 65404 0\n" ///< FF7C; CAPCOM Register 2 Interrupt Ctrl. Reg. + // "gpr CC3IC .16 65406 0\n" ///< FF7E; CAPCOM Register 3 Interrupt Ctrl. Reg. + // "gpr CC4IC .16 65408 0\n" ///< FF80; CAPCOM Register 4 Interrupt Ctrl. Reg. + // "gpr CC5IC .16 65410 0\n" ///< FF82; CAPCOM Register 5 Interrupt Ctrl. Reg. + // "gpr CC6IC .16 65412 0\n" ///< FF84; CAPCOM Register 6Interrupt Ctrl. Reg. + // "gpr CC7IC .16 65414 0\n" ///< FF86; CAPCOM Register 7 Interrupt Ctrl. Reg. + // "gpr CC8IC .16 65416 0\n" ///< FF88; CAPCOM Register 8 Interrupt Ctrl. Reg. + // "gpr CC9IC .16 65418 0\n" ///< FF8A; CAPCOM Register 9 Interrupt Ctrl. Reg. + // "gpr CC10IC .16 65420 0\n" ///< FF8C; CAPCOM Register 10 Interrupt Ctrl. Reg. + // "gpr CC11IC .16 65422 0\n" ///< FF8E; CAPCOM Register 11 Interrupt Ctrl. Reg. + // "gpr CC12IC .16 65424 0\n" ///< FF90; CAPCOM Register 12 Interrupt Ctrl. Reg. + // "gpr CC13IC .16 65426 0\n" ///< FF92; CAPCOM Register 13 Interrupt Ctrl. Reg. + // "gpr CC14IC .16 65428 0\n" ///< FF94; CAPCOM Register 14 Interrupt Ctrl. Reg. + // "gpr CC15IC .16 65430 0\n" ///< FF96; CAPCOM Register 15 Interrupt Ctrl. Reg. + // "gpr ADCIC .16 65432 0\n" ///< FF98; A/D Converter End of Conversion Interrupt Control Register + // "gpr ADEIC .16 65434 0\n" ///< FF9A; A/D Converter Overrun Error Interrupt Control Register + // "gpr T0IC .16 65436 0\n" ///< FF9C; CAPCOM Timer 0 Interrupt Ctrl. Reg. + // "gpr T1IC .16 65438 0\n" ///< FF9E; CAPCOM Timer 1 Interrupt Ctrl. Reg. + // "gpr ADCON .16 65440 0\n" ///< FFA0; A/D Converter Control Register + // "gpr P5 .16 65442 0\n" ///< FFA2; Port 5 Register (read only) + // "gpr r_FFA4 .16 65444 0\n" ///< FFA4; RESERVED + // "gpr r_FFA6 .16 65446 0\n" ///< FFA6; RESERVED + // "gpr r_FFA8 .16 65448 0\n" ///< FFA8; RESERVED + // "gpr r_FFAA .16 65450 0\n" ///< FFAA; RESERVED "gpr TFR .16 65452 0\n" ///< FFAC; Trap Flag Register "gpr WDTCON .16 65454 0\n" ///< FFAE; Watchdog Timer Control Register "gpr S0CON .16 65456 0\n" ///< FFB0; Serial Channel 0 Control Register - "gpr r_FFB2 .16 65458 0\n" ///< FFB2; RESERVED - "gpr r_FFB4 .16 65460 0\n" ///< FFB4; RESERVED - "gpr r_FFB6 .16 65462 0\n" ///< FFB6; RESERVED - "gpr S1CON .16 65464 0\n" ///< FFB8; Serial Channel 1 Control Register - "gpr r_FFBA .16 65466 0\n" ///< FFBA; RESERVED - "gpr r_FFBC .16 65468 0\n" ///< FFBC; RESERVED - "gpr r_FFBE .16 65470 0\n" ///< FFBE; RESERVED - "gpr P2 .16 65472 0\n" ///< FFC0; Port 2 Register - "gpr DP2 .16 65474 0\n" ///< FFC2; Port 2 Direction Control Register - "gpr P3 .16 65476 0\n" ///< FFC4; Port 3 Register - "gpr DP3 .16 65478 0\n" ///< FFC6; Port 3 Direction Control Register - - "gpr r_FFC8 .16 65480 0\n" ///< FFC8; RESERVED - "gpr r_FFCA .16 65482 0\n" ///< FFCA; RESERVED - "gpr r_FFCC .16 65484 0\n" ///< FFCC; RESERVED - "gpr r_FFCE .16 65486 0\n" ///< FFCE; RESERVED - "gpr r_FFD0 .16 65488 0\n" ///< FFD0; RESERVED - "gpr r_FFD2 .16 65490 0\n" ///< FFD2; RESERVED - "gpr r_FFD4 .16 65492 0\n" ///< FFD4; RESERVED - "gpr r_FFD6 .16 65494 0\n" ///< FFD6; RESERVED - "gpr r_FFD8 .16 65496 0\n" ///< FFD8; RESERVED + // "gpr r_FFB2 .16 65458 0\n" ///< FFB2; RESERVED + // "gpr r_FFB4 .16 65460 0\n" ///< FFB4; RESERVED + // "gpr r_FFB6 .16 65462 0\n" ///< FFB6; RESERVED + // "gpr S1CON .16 65464 0\n" ///< FFB8; Serial Channel 1 Control Register + // "gpr r_FFBA .16 65466 0\n" ///< FFBA; RESERVED + // "gpr r_FFBC .16 65468 0\n" ///< FFBC; RESERVED + // "gpr r_FFBE .16 65470 0\n" ///< FFBE; RESERVED + // "gpr P2 .16 65472 0\n" ///< FFC0; Port 2 Register + // "gpr DP2 .16 65474 0\n" ///< FFC2; Port 2 Direction Control Register + // "gpr P3 .16 65476 0\n" ///< FFC4; Port 3 Register + // "gpr DP3 .16 65478 0\n" ///< FFC6; Port 3 Direction Control Register + + // "gpr r_FFC8 .16 65480 0\n" ///< FFC8; RESERVED + // "gpr r_FFCA .16 65482 0\n" ///< FFCA; RESERVED + // "gpr r_FFCC .16 65484 0\n" ///< FFCC; RESERVED + // "gpr r_FFCE .16 65486 0\n" ///< FFCE; RESERVED + // "gpr r_FFD0 .16 65488 0\n" ///< FFD0; RESERVED + // "gpr r_FFD2 .16 65490 0\n" ///< FFD2; RESERVED + // "gpr r_FFD4 .16 65492 0\n" ///< FFD4; RESERVED + // "gpr r_FFD6 .16 65494 0\n" ///< FFD6; RESERVED + // "gpr r_FFD8 .16 65496 0\n" ///< FFD8; RESERVED "gpr MRW .16 65498 0\n" ///< FFDA; MAC Repeat Word "gpr MCW .16 65500 0\n" ///< FFDC; MAC Control Word "gpr MSW .16 65502 0"; ///< FFDE; MAC Status Word @@ -1691,6 +1816,7 @@ RzAnalysisPlugin rz_analysis_plugin_c166 = { .op = &c166_op, .archinfo = &archinfo, .get_reg_profile = &get_reg_profile, + .il_config = rz_c166_il_config, .init = &c16x_init, .fini = &c16x_fini, }; diff --git a/librz/arch/p/asm/asm_c166.c b/librz/arch/p/asm/asm_c166.c index e0bb99ad589..7b248dd2000 100644 --- a/librz/arch/p/asm/asm_c166.c +++ b/librz/arch/p/asm/asm_c166.c @@ -363,10 +363,11 @@ static st32 disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, st32 len) { } else if (op->size == 2 && len == 1) { rz_asm_op_setf_asm(op, FMT_WORD, buf[0], 0x00); } else if (RZ_STR_EQ(inst.instr, "invalid")) { - if (op->size == 2) + if (op->size == 2) { rz_asm_op_setf_asm(op, FMT_WORD, buf[0], buf[1]); - else + } else { rz_asm_op_setf_asm(op, FMT_2WORD, buf[0], buf[1], buf[2], buf[3]); + } } else { if (RZ_STR_ISNOTEMPTY(inst.operands)) { rz_asm_op_setf_asm(op, FMT7, inst.instr, inst.operands); @@ -396,8 +397,12 @@ static RZ_OWN RzPVector /**/ *get_token_patterns() { return NULL; } TOKEN(META, "^(.word.*)"); - TOKEN(SEPARATOR, "([\\s.,:]+)"); - TOKEN(REGISTER, "\\b0x([fF][eEfF][0-9a-fA-F]{2})\\b"); + // TOKEN(NUMBER, "#(0x[0-9a-f]{1,8})"); + TOKEN(REGISTER, "(0xf[a-f][0-9a-f]{2})"); ///< 0xfe00:0x0246 + // Hexadecimal numbers + TOKEN(SEPARATOR, "([\\s.,:#]+)"); + TOKEN(NUMBER, "(0x[f][0-9a-f]{1,3})"); + TOKEN(NUMBER, "(0x[^f][0-9a-f]+)"); TOKEN(MNEMONIC, "^(jmpa[+-]?)"); ///< jmpa+ jmpa- mnemonics TOKEN(MNEMONIC, "^(calla[+-]?)"); ///< calla+ calla- mnemonics TOKEN(META, "^([\\- USR]+[012]?)"); @@ -405,8 +410,6 @@ static RZ_OWN RzPVector /**/ *get_token_patterns() { TOKEN(META, "([\\[\\]\\-#])"); // TOKEN(META, "(cc_\\w+)"); TOKEN(META, "(cc_[\\w\\/]+)"); - // Hexadecimal numbers - TOKEN(NUMBER, "(0x[0-9a-f]+)"); /** * Match normal registers which start with small r, optional h or l * and a number. @@ -415,7 +418,6 @@ static RZ_OWN RzPVector /**/ *get_token_patterns() { */ TOKEN(REGISTER, "\\b(r[hl]?[0-9]{1,2}|[A-Z]+[A-Z0-9]*)\\b"); TOKEN(MNEMONIC, "^([\\w]+[12]?)"); - // TOKEN(SEPARATOR, "([\\s.,:+]+)"); TOKEN(SEPARATOR, "(\\+)"); // Decimal numbers TOKEN(NUMBER, "(data[2,3,4,5,8])"); @@ -465,8 +467,8 @@ static bool c16x_fini(void *user) { static char **c166_cpu_descriptions() { static char *cpu_desc[] = { "c166-generic", "Siemens/Infineon C166 family", - "c166v1", "Siemens/Infineon C16x v1 family", - "c166v2", "Siemens/Infineon C16x v2 family", + // "c166v1", "Siemens/Infineon C16x v1 family", + // "c166v2", "Siemens/Infineon C16x v2 family", NULL }; return cpu_desc; @@ -483,9 +485,9 @@ RzAsmPlugin rz_asm_plugin_c166 = { .init = &c16x_init, .fini = &c16x_fini, .cpus = - "c166-generic," - "c166v1," - "c166v2", + "c166-generic,", + // "c166v1," + // "c166v2" .get_cpu_desc = c166_cpu_descriptions, }; diff --git a/librz/bin/format/omf/omf.h b/librz/bin/format/omf/omf.h index a7dd5f33e4d..15a334a9a99 100644 --- a/librz/bin/format/omf/omf.h +++ b/librz/bin/format/omf/omf.h @@ -719,6 +719,7 @@ typedef struct { typedef struct { ut8 bits; + ut64 base_addr; ut8 modinfo; int TI_INDEX; int SEC_INDEX; diff --git a/librz/bin/format/omf/omf166.c b/librz/bin/format/omf/omf166.c index 3a12e080d10..23757cf7bf3 100644 --- a/librz/bin/format/omf/omf166.c +++ b/librz/bin/format/omf/omf166.c @@ -597,7 +597,7 @@ static int load_linnum_data(const rz_bin_omf166_obj *obj, const ut8 *buf, const return true; } -static int load_omf_pedata(const rz_bin_omf166_obj *obj, const ut8 *buf, const OMF_record *record, const ut64 global_ct) { +static int load_omf_pedata(rz_bin_omf166_obj *obj, const ut8 *buf, const OMF_record *record, const ut64 global_ct) { if (!(obj && obj->pe_vec)) { return false; } @@ -622,6 +622,13 @@ static int load_omf_pedata(const rz_bin_omf166_obj *obj, const ut8 *buf, const O */ pe->size = pe->psize = record->size - 1 - (ct - 3); pe->paddr = global_ct + ct; + + // if (pe->isVector && rz_pvector_empty(obj->pe_vec)) { + if (pe->isVector) { + // const ut8 c = rz_read_le8(buf + pe->paddr + 1); + const ut8 c = pe->SegmentNumber8; + obj->base_addr = c << 16 | 0x000000; + } rz_pvector_push(obj->pe_vec, pe); return true; } @@ -1049,6 +1056,11 @@ static int rz_bin_format_omf166_load_content(rz_bin_omf166_obj *obj, OMF_record case OMF166_UNKNOWN4: { return load_omf_unk4(buf, buf_size, record, global_ct); } + case OMF166_SSKDEF: { + RZ_LOG_DEBUG("load_omf: [%05d] [0x%08" PFMT64x "] 0x%02x (%" PFMTSZu ")\n", + record->size, global_ct, record->type, buf_size); + return true; + } default: { RZ_LOG_DEBUG("load_omf: [%05d] [0x%08" PFMT64x "] 0x%02x (%" PFMTSZu ")\t", record->size, global_ct, record->type, buf_size); diff --git a/librz/bin/p/bin_c166.c b/librz/bin/p/bin_c166.c index 1bc0f60aae6..14ca7a8b10b 100644 --- a/librz/bin/p/bin_c166.c +++ b/librz/bin/p/bin_c166.c @@ -78,6 +78,7 @@ static RzBinInfo *info(RzBinFile *bf) { ret->bits = 16; ret->dbg_info = 0; ret->has_nx = false; + ret->lang = rz_str_dup("C"); return ret; } @@ -158,6 +159,10 @@ static RzBinAddr *binsym(RzBinFile *bf, RzBinSpecialSymbol type) { } } +static ut64 baddr(RzBinFile *bf) { + return 0; +} + struct rz_bin_plugin_t rz_bin_plugin_c166 = { .name = "c166", .desc = "Siemens/Infineon C166 family microcontroller binary", @@ -171,6 +176,7 @@ struct rz_bin_plugin_t rz_bin_plugin_c166 = { .info = &info, .binsym = &binsym, .strings = &strings, + .baddr = baddr }; #ifndef RZ_PLUGIN_INCORE diff --git a/librz/bin/p/bin_omf166.c b/librz/bin/p/bin_omf166.c index d45ce8470c9..000bb383de4 100644 --- a/librz/bin/p/bin_omf166.c +++ b/librz/bin/p/bin_omf166.c @@ -100,6 +100,8 @@ static bool check_buffer(RzBuffer *b) { static RzPVector /**/ *entries(RzBinFile *bf) { RzPVector *ret; RzBinAddr *addr; + rz_bin_omf166_obj *obj = (rz_bin_omf166_obj *)bf->o->bin_obj; + if (!((ret = rz_pvector_new(free)))) { return NULL; } @@ -108,7 +110,7 @@ static RzPVector /**/ *entries(RzBinFile *bf) { return NULL; } addr->type = RZ_BIN_SPECIAL_SYMBOL_ENTRY; - addr->vaddr = 0xC00000; + addr->vaddr = obj->base_addr; rz_pvector_push(ret, addr); return ret; } @@ -180,8 +182,8 @@ static RzPVector /**/ *sections(RzBinFile *bf) { new->name = rz_str_newf("%s_%s", name, class_name); new->size = new->vsize = section->Seclen; new->vaddr = (section->SegmentNumber8 << 16) + section->offset; - new->has_strings = (section->Type == 1) ? true : false; - new->is_data = (section->Type == 1) ? true : false; + new->has_strings = (section->Type == 2) ? false : true; + new->is_data = (section->Type == 2) ? false : true; new->is_segment = 0; new->perm = c166_get_perms_from_class(section->class_index); rz_pvector_push(ret, new); @@ -217,6 +219,9 @@ static RzPVector /**/ *symbols(RzBinFile *bf) { } RzPVector *ret = rz_pvector_new((RzPVectorFree)rz_bin_symbol_free); + if (!ret) { + return NULL; + } rz_pvector_sort(obj->symbols_vec, offset_cmp, NULL); void **it; rz_pvector_foreach (obj->symbols_vec, it) { @@ -371,6 +376,7 @@ static RzBinInfo *info(RzBinFile *bf) { ret->rclass = rz_str_dup("OMF166"); ret->compiler = rz_str_dup("keil"); ret->os = rz_str_dup("c166"); + ret->cpu = rz_str_dup("c166-generic"); ret->machine = rz_str_dup("Siemens/Infineon C166 family microcontroller"); ret->arch = rz_str_dup("c166"); ret->big_endian = false; @@ -378,6 +384,7 @@ static RzBinInfo *info(RzBinFile *bf) { ret->bits = 16; ret->dbg_info = 0; ret->has_nx = false; + ret->lang = rz_str_dup("C"); return ret; } @@ -395,6 +402,7 @@ static RzPVector /**/ *strings(RzBinFile *bf) { static RzBinAddr *binsym(RzBinFile *bf, RzBinSpecialSymbol type) { RzBinAddr *ptr = NULL; + rz_bin_omf166_obj *obj = (rz_bin_omf166_obj *)bf->o->bin_obj; switch (type) { case RZ_BIN_SPECIAL_SYMBOL_ENTRY: @@ -404,7 +412,7 @@ static RzBinAddr *binsym(RzBinFile *bf, RzBinSpecialSymbol type) { return NULL; } ptr->type = RZ_BIN_SPECIAL_SYMBOL_ENTRY; - ptr->vaddr = 0xC00000; + ptr->vaddr = obj->base_addr; return ptr; case RZ_BIN_SPECIAL_SYMBOL_MAIN: if (!((ptr = RZ_NEW0(RzBinAddr)))) { @@ -421,6 +429,10 @@ static RzBinAddr *binsym(RzBinFile *bf, RzBinSpecialSymbol type) { } } +static ut64 baddr(RzBinFile *bf) { + return 0; +} + RzBinPlugin rz_bin_plugin_omf166 = { .name = "omf166", .desc = "OMF166 (Object Module Format by Siemens)", @@ -438,6 +450,7 @@ RzBinPlugin rz_bin_plugin_omf166 = { .info = &info, .strings = &strings, .get_vaddr = &get_vaddr, + .baddr = baddr }; #ifndef RZ_PLUGIN_INCORE diff --git a/librz/core/disasm.c b/librz/core/disasm.c index 3aa21d18d9c..9e87b70a45b 100644 --- a/librz/core/disasm.c +++ b/librz/core/disasm.c @@ -1020,17 +1020,6 @@ static void ds_build_op_str(RzDisasmState *ds, bool print_color) { } } - if (ds->analysis_op.mmio_address != UT64_MAX) { - char number[32]; - rz_strf(number, "0x%" PFMT64x, ds->analysis_op.mmio_address); - - RzPlatformTarget *arch_target = rz_analysis_get_arch_target(core->analysis); - const char *resolved = rz_platform_profile_resolve_mmio(arch_target->profile, ds->analysis_op.mmio_address); - if (resolved) { - ds->opstr = rz_str_replace(ds->opstr, number, resolved, 0); - } - } - if (ds->analysis_op.ptr != UT64_MAX) { char number[32]; rz_strf(number, "0x%" PFMT64x, ds->analysis_op.ptr); @@ -1142,6 +1131,18 @@ static void ds_build_op_str(RzDisasmState *ds, bool print_color) { } else { ds_opstr_try_colorize(ds, print_color); } + for (int i = 0; i < RZ_ARRAY_SIZE(ds->analysis_op.mmios); i++) { + if (ds->analysis_op.mmios[i] != UT64_MAX) { + char number[32]; + rz_strf(number, "0x%" PFMT64x, ds->analysis_op.mmios[i]); + + RzPlatformTarget *arch_target = rz_analysis_get_arch_target(core->analysis); + const char *resolved = rz_platform_profile_resolve_mmio(arch_target->profile, ds->analysis_op.mmios[i]); + if (resolved) { + ds->opstr = rz_str_replace(ds->opstr, number, resolved, 0); + } + } + } rz_str_trim_char(ds->opstr, '\n'); // updates ds->opstr __replaceImports(ds); diff --git a/librz/include/rz_analysis.h b/librz/include/rz_analysis.h index 30fa0d125a9..6e18c494627 100644 --- a/librz/include/rz_analysis.h +++ b/librz/include/rz_analysis.h @@ -874,7 +874,8 @@ typedef struct rz_analysis_op_t { int ptrsize; /* f.ex: zero extends for 8, 16 or 32 bits only */ st64 stackptr; /* stack pointer */ int refptr; /* if (0) ptr = "reference" else ptr = "load memory of refptr bytes" */ - ut64 mmio_address; // mmio address + ut8 mmios_count; ///< used mmio count + ut64 mmios[4]; ///< mmio address RzAnalysisValue *src[8]; RzAnalysisValue *dst; RzList /**/ *access; /* RzAnalysisValue access information */ diff --git a/test/db/asm/c166 b/test/db/asm/c166 index 48477cea554..83a8d60409c 100644 --- a/test/db/asm/c166 +++ b/test/db/asm/c166 @@ -88,9 +88,9 @@ d "extr #2" D190 d "extr #3" D1A0 d "extr #4" D1B0 -d "band r0.1, r0.2" 6AF0F012 -d "band r1.14, r0.7" 6AF1F0E7 -d "band r1.14, r0.7" 6AF1F0E7 +d "band r0.2, r0.1" 6af0f012 +d "band r0.7, r1.14" 6af1f0e7 +d "band r0.7, r1.14" 6af1f0e7 d "bclr r2.0" 0EF2 d "bclr r2.1" 1EF2 @@ -105,8 +105,10 @@ d "bclr r2.9" 9EF2 d "bclr r2.10" AEF2 d "bclr r2.11" BEF2 d "bclr r2.12" CEF2 +d "bclr r3.0" 0EF3 +d "bclr 0xfd98.11" be4c -d "bcmp r1.14, r0.7" 2AF1F0E7 +d "bcmp r0.7, r1.14" 2af1f0e7 d "bfldh r1, #0x80, #0xff" 1AF1FF80 d "bfldh r1, #0xff, #0x80" 1AF180FF @@ -114,12 +116,13 @@ d "bfldl r1, #0x80, #0xff" 0AF180FF d "bfldl r1, #0xff, #0x80" 0AF1FF80 d "bfldl 0xfd00, #0x20, #0x20" 0A002020 -d "bmov r1.14, r0.7" 4AF1F0E7 -d "bmovn r1.14, r0.7" 3AF1F0E7 +d "bmov r0.7, r1.14" 4af1f0e7 +d "bmov r2.0, r2.8" 4af2f280 +d "bmovn r0.7, r1.14" 3af1f0e7 -d "bor r0.1, r0.2" 5AF0F012 -d "bor r2.1, r0.7" 5AF2F017 -d "bor r1.14, 0xfd00.7" 5AF100E7 +d "bor r0.2, r0.1" 5af0f012 +d "bor r0.7, r2.1" 5af2f017 +d "bor 0xfd00.7, r1.14" 5af100e7 d "bset r0.13" DFF0 d "bset r0.14" EFF0 @@ -130,8 +133,10 @@ d "bset 0xfd04.7" 7F02 d "bset 0xff02.15" FF81 -d "bxor r2.1, r0.7" 7AF2F017 -d "bxor 0xfd00.7, r1.14" 7A00F17E +d "bxor r0.7, r2.1" 7af2f017 +d "bxor r1.14, 0xfd00.7" 7a00f17e + +d "bxor 0xfd00.0, 0xfd88.4" 7a440040 d "calla+ cc_Z/EQ, 0x0660" CA206006 d "calli cc_Z/EQ, [r3]" AB23 @@ -225,6 +230,7 @@ d "mov 0xfe00:0x0660, [r2]" 94026006 d "mov r0, 0xfe00:0x2211" F2F01122 d "mov 0xfe00:0x2211, r0" F6F01122 d "mov 0xfe06:0x3eb0, r8" F6F8B0FE +d "mov 0xfe06:0x2e10, r0" f6f010ee d "movb rh1, rh0" F131 d "movb rh7, #0x0003" E13F @@ -354,6 +360,7 @@ d "xorb rl2, [rh1+]" 594F d "xorb rh7, #0x0001" 57FF0100 d "xorb rl7, 0xfe00:0x0201" 53FE0102 d "xorb 0xfe00:0x0201, rl7" 55FE0102 +d "xorb 0xfece, 0xfe06:0x05ae" 5367aec5 # The following are from keil's c166 user guide # PWS=0xff10, MDL=0xfe0e @@ -363,6 +370,7 @@ d "bfldh 0xff10, #0xf0, #0xf0" 1A88F0F0 d "mul r8, r9" 0B89 d "mov r4, 0xfe06:0x3e0e" F2F40EFE d "bfldh 0xff10, #0xf0, #0x00" 1A8800F0 +d "bfldh 0xff10, #0x03, #0x02" 1A880203 d "ret" CB00 # from Directives/Reference/without NOALIAS @@ -412,7 +420,7 @@ d "mov r4, #0xfea0" E6F4A0FE d "bfldh 0xff10, #0xf0, #0xf0" 1A88F0F0 d "mov 0xfe00:0x0000, 0xff1c" F68E0000 -d "exts #0x0004, #1;mov 0x043de2, r4;mov 0xfe06:0x3de2, r4" D7000400F6F4E2FDF6F4E2FD +d "exts #0x0004, #1;mov 0xfe06:0x3de2, r4;mov 0xfe06:0x3de2, r4" D7000400F6F4E2FDF6F4E2FD d "exts r9, #1" DC09 d "or 0xffc4, #0x0400" 76E20004 @@ -423,315 +431,321 @@ d "subcb 0xfe00:0x3020, 0xfe40" 35202030 d "jmpr cc_UC, 0x000000" 0dff -d "- USR0 CoMULu r3, [r4]" 83340056 -d "- USR1 CoMULu r3, [r4]" 83340066 -d "CoMULu r3, [r4]" 83340006 -d "- USR0 CoMACu [0xff0a], [r4]" 93941056 -d "- USR1 CoMACu [0xff0a], [r4]" 93941066 -d "CoMACu [0xff0a], [r4]" 93941006 -d "- USR0 CoMACu [0xff08], [r4]" 93141056 -d "- USR1 CoMACu [0xff08], [r4]" 93141066 -d "CoMACu [0xff08], [r4]" 93141006 +d "- USR0 CoMULu r3, [r4+QR1]" 83340056 +d "- USR1 CoMULu r3, [r4+QR1]" 83340066 +d "CoMULu r3, [r4+QR1]" 83340006 +d "- USR0 CoMACu [0xff0a], [r4+QR1]" 93941056 +d "- USR1 CoMACM [0xff08+], [r0+]" 9320d862 +d "- USR1 CoMACM [0xff08+], [r0+QR0]" 9320D864 +d "- USR1 CoMACM [0xff08-], [r0+]" 9330D862 +d "- USR0 CoMACM [0xff08+QX0], [r0-]" 9340D843 +d "- USR0 CoMACM [0xff08-], [r2+]" 9332d842 +d "- USR0 CoMACM [0xff08+QX0], [r0+]" 9340D842 +d "- USR1 CoMACu [0xff0a], [r4+QR1]" 93941066 +d "CoMACu [0xff0a], [r4+QR1]" 93941006 +d "- USR0 CoMACu [0xff08], [r4+QR1]" 93141056 +d "- USR1 CoMACu [0xff08], [r4+QR1]" 93141066 +d "CoMACu [0xff08], [r4+QR1]" 93141006 d "- USR0 CoMULu r3, r4" A3340056 d "- USR1 CoMULu r3, r4" A3340066 d "CoMULu r3, r4" A3340006 -d "- USR0 CoMULu r5, [r4], rnd" 83540156 -d "- USR1 CoMULu r5, [r4], rnd" 83540166 -d "CoMULu r5, [r4], rnd" 83540106 -d "- USR0 CoMULu [0xff08], [r4], rnd" 93140156 -d "- USR1 CoMULu [0xff08], [r4], rnd" 93140166 -d "CoMULu [0xff08], [r4], rnd" 93140106 -d "- USR0 CoMULu [0xff0a], [r4], rnd" 93940156 -d "- USR1 CoMULu [0xff0a], [r4], rnd" 93940166 -d "CoMULu [0xff0a], [r4], rnd" 93940106 -d "- USR0 CoMULu r3, r4, rnd" A3340156 -d "- USR1 CoMULu r3, r4, rnd" A3340166 -d "CoMULu r3, r4, rnd" A3340106 - -d "- USR0 CoMACu [0xff08], [r4], rnd" 93141156 -d "- USR1 CoMACu [0xff08], [r4], rnd" 93141166 -d "CoMACu [0xff08], [r4], rnd" 93141106 -d "- USR0 CoMACu [0xff0a], [r4], rnd" 93941156 -d "- USR1 CoMACu [0xff0a], [r4], rnd" 93941166 -d "CoMACu [0xff0a], [r4], rnd" 93941106 -d "- USR0 CoMACu r3, [r4], rnd" 83341156 -d "- USR1 CoMACu r3, [r4], rnd" 83341166 -d "CoMACu r3, [r4], rnd" 83341106 -d "- USR0 CoMACu r3, r4, rnd" A3341156 -d "- USR1 CoMACu r3, r4, rnd" A3341166 -d "CoMACu r3, r4, rnd" A3341106 +d "- USR0 CoMULu r5, [r4+QR1], rnd" 83540156 +d "- USR1 CoMULu r5, [r4+QR1], rnd" 83540166 +d "CoMULu r5, [r4+QR1], rnd" 83540106 +d "- USR0 CoMULu [0xff08], [r4+QR1], rnd" 93140156 +d "- USR1 CoMULu [0xff08], [r4+QR1], rnd" 93140166 +d "CoMULu [0xff08], [r4+QR1], rnd" 93140106 +d "- USR0 CoMULu [0xff0a], [r4+QR1], rnd" 93940156 +d "- USR1 CoMULu [0xff0a], [r4+QR1], rnd" 93940166 +d "CoMULu [0xff0a], [r4+QR1], rnd" 93940106 +d "- USR0 CoMULu r3, [r4+QR1], rnd" a3340156 +d "- USR1 CoMULu r3, [r4+QR1], rnd" a3340166 +d "CoMULu r3, [r4+QR1], rnd" a3340106 + +d "- USR0 CoMACu [0xff08], [r4+QR1], rnd" 93141156 +d "- USR1 CoMACu [0xff08], [r4+QR1], rnd" 93141166 +d "CoMACu [0xff08], [r4+QR1], rnd" 93141106 +d "- USR0 CoMACu [0xff0a], [r4+QR1], rnd" 93941156 +d "- USR1 CoMACu [0xff0a], [r4+QR1], rnd" 93941166 +d "CoMACu [0xff0a], [r4+QR1], rnd" 93941106 +d "- USR0 CoMACu r3, [r4+QR1], rnd" 83341156 +d "- USR1 CoMACu r3, [r4+QR1], rnd" 83341166 +d "CoMACu r3, [r4+QR1], rnd" 83341106 +d "- USR0 CoMACu r3, [r4+QR1], rnd" a3341156 +d "- USR1 CoMACu r3, [r4+QR1], rnd" a3341166 +d "CoMACu r3, [r4+QR1], rnd" a3341106 d ".word 0xa334 .word 0x2156" A3342156 -d "- USR0 CoMULus r3, [r4]" 83348056 -d "- USR1 CoMULus r3, [r4]" 83348066 -d "CoMULus r3, [r4]" 83348006 -d "- USR0 CoMULus [0xff08], [r4]" 93048056 -d "- USR1 CoMULus [0xff08], [r4]" 93048066 -d "CoMULus [0xff08], [r4]" 93048006 +d "- USR0 CoMULus r3, [r4+QR1]" 83348056 +d "- USR1 CoMULus r3, [r4+QR1]" 83348066 +d "CoMULus r3, [r4+QR1]" 83348006 +d "- USR0 CoMULus [0xff08], [r4+QR1]" 93048056 +d "- USR1 CoMULus [0xff08], [r4+QR1]" 93048066 +d "CoMULus [0xff08], [r4+QR1]" 93048006 d "- USR0 CoMULus r3, r4" A3348056 d "- USR1 CoMULus r3, r4" A3348066 d "CoMULus r3, r4" A3348006 -d "- USR0 CoMULus r3, [r4], rnd" 83348156 -d "- USR1 CoMULus r3, [r4], rnd" 83348166 -d "CoMULus r3, [r4], rnd" 83348106 -d "- USR0 CoMULus [0xff08], [r4], rnd" 93048156 -d "- USR1 CoMULus [0xff08], [r4], rnd" 93048166 -d "CoMULus [0xff08], [r4], rnd" 93048106 -d "- USR0 CoMULus r3, r4, rnd" A3348156 -d "- USR1 CoMULus r3, r4, rnd" A3348166 -d "CoMULus r3, r4, rnd" A3348106 - -d "- USR0 CoMULu- r3, [r4]" 83340856 -d "- USR1 CoMULu- r3, [r4]" 83340866 -d "CoMULu- r3, [r4]" 83340806 -d "- USR0 CoMULu- [0xff08], [r4]" 93040856 -d "- USR1 CoMULu- [0xff08], [r4]" 93040866 -d "CoMULu- [0xff08], [r4]" 93040806 +d "- USR0 CoMULus r3, [r4+QR1], rnd" 83348156 +d "- USR1 CoMULus r3, [r4+QR1], rnd" 83348166 +d "CoMULus r3, [r4+QR1], rnd" 83348106 +d "- USR0 CoMULus [0xff08], [r4+QR1], rnd" 93048156 +d "- USR1 CoMULus [0xff08], [r4+QR1], rnd" 93048166 +d "CoMULus [0xff08], [r4+QR1], rnd" 93048106 +d "- USR0 CoMULus r3, [r4+QR1], rnd" a3348156 +d "- USR1 CoMULus r3, [r4+QR1], rnd" a3348166 +d "CoMULus r3, [r4+QR1], rnd" a3348106 + +d "- USR0 CoMULu- r3, [r4+QR1]" 83340856 +d "- USR1 CoMULu- r3, [r4+QR1]" 83340866 +d "CoMULu- r3, [r4+QR1]" 83340806 +d "- USR0 CoMULu- [0xff08], [r4+QR1]" 93040856 +d "- USR1 CoMULu- [0xff08], [r4+QR1]" 93040866 +d "CoMULu- [0xff08], [r4+QR1]" 93040806 d "- USR0 CoMULu- r3, r4" A3340856 d "- USR1 CoMULu- r3, r4" A3340866 d "CoMULu- r3, r4" A3340806 -d "- USR0 CoMULus- r3, [r4]" 83348856 -d "- USR1 CoMULus- r3, [r4]" 83348866 -d "CoMULus- r3, [r4]" 83348806 -d "- USR0 CoMULus- [0xff08 -2], [r4]" 93348856 -d "- USR1 CoMULus- [0xff08 -2], [r4]" 93348866 -d "CoMULus- [0xff08 -2], [r4]" 93348806 -d "- USR0 CoMULus- [0xff0a -2], [r4]" 93B48856 -d "- USR1 CoMULus- [0xff0a -2], [r4]" 93B48866 -d "CoMULus- [0xff0a -2], [r4]" 93B48806 +d "- USR0 CoMULus- r3, [r4+QR1]" 83348856 +d "- USR1 CoMULus- r3, [r4+QR1]" 83348866 +d "CoMULus- r3, [r4+QR1]" 83348806 +d "- USR0 CoMULus- [0xff08-], [r4+QR1]" 93348856 +d "- USR1 CoMULus- [0xff08-], [r4+QR1]" 93348866 +d "CoMULus- [0xff08-], [r4+QR1]" 93348806 +d "- USR0 CoMULus- [0xff0a-], [r4+QR1]" 93b48856 +d "- USR1 CoMULus- [0xff0a-], [r4+QR1]" 93b48866 +d "CoMULus- [0xff0a-], [r4+QR1]" 93b48806 d "- USR0 CoMULus- r3, r4" A3348856 d "- USR1 CoMULus- r3, r4" A3348866 d "CoMULus- r3, r4" A3348806 -d "- USR0 CoMACsu- r3, [r4]" 83346056 -d "- USR1 CoMACsu- r3, [r4]" 83346066 -d "CoMACsu- r3, [r4]" 83346006 -d "- USR0 CoMACsu- [0xff08 - QX1], [r4]" 93746056 -d "- USR1 CoMACsu- [0xff08 - QX1], [r4]" 93746066 -d "CoMACsu- [0xff08 - QX1], [r4]" 93746006 -d "- USR0 CoMACsu- [0xff08 - QX1], [r15]" 937F6056 -d "- USR1 CoMACsu- [0xff08 - QX1], [r15]" 937F6066 -d "CoMACsu- [0xff08 - QX1], [r15]" 937F6006 -d "- USR0 CoMACsu- [0xff0a - QX1], [r4]" 93F46056 -d "- USR1 CoMACsu- [0xff0a - QX1], [r4]" 93F46066 -d "CoMACsu- [0xff0a - QX1], [r4]" 93F46006 +d "- USR0 CoMACsu- r3, [r4+QR1]" 83346056 +d "- USR1 CoMACsu- r3, [r4+QR1]" 83346066 +d "CoMACsu- r3, [r4+QR1]" 83346006 +d "- USR0 CoMACsu- [0xff08-QX1], [r4+QR1]" 93746056 +d "- USR1 CoMACsu- [0xff08-QX1], [r4+QR1]" 93746066 +d "CoMACsu- [0xff08-QX1], [r4+QR1]" 93746006 +d "- USR0 CoMACsu- [0xff08-QX1], [r15+QR1]" 937f6056 +d "- USR1 CoMACsu- [0xff08-QX1], [r15+QR1]" 937f6066 +d "CoMACsu- [0xff08-QX1], [r15+QR1]" 937f6006 +d "- USR0 CoMACsu- [0xff0a-QX1], [r4+QR1]" 93f46056 +d "- USR1 CoMACsu- [0xff0a-QX1], [r4+QR1]" 93f46066 +d "CoMACsu- [0xff0a-QX1], [r4+QR1]" 93f46006 d "- USR0 CoMACsu- r3, r4" A3346056 d "- USR1 CoMACsu- r3, r4" A3346066 d "CoMACsu- r3, r4" A3346006 -d "- USR0 CoMACRsu r3, [r4]" 83347056 -d "- USR1 CoMACRsu r3, [r4]" 83347066 -d "CoMACRsu r3, [r4]" 83347006 -d "- USR0 CoMACRsu [0xff08], [r4]" 93047056 -d "- USR1 CoMACRsu [0xff08], [r4]" 93047066 -d "CoMACRsu [0xff08], [r4]" 93047006 +d "- USR0 CoMACRsu r3, [r4+QR1]" 83347056 +d "- USR1 CoMACRsu r3, [r4+QR1]" 83347066 +d "CoMACRsu r3, [r4+QR1]" 83347006 +d "- USR0 CoMACRsu [0xff08], [r4+QR1]" 93047056 +d "- USR1 CoMACRsu [0xff08], [r4+QR1]" 93047066 +d "CoMACRsu [0xff08], [r4+QR1]" 93047006 d "- USR0 CoMACRsu r3, r4" A3347056 d "- USR1 CoMACRsu r3, r4" A3347066 d "CoMACRsu r3, r4" A3347006 -d "- USR0 CoMACRsu r3, [r4], rnd" 83347156 -d "- USR1 CoMACRsu r3, [r4], rnd" 83347166 -d "CoMACRsu r3, [r4], rnd" 83347106 -d "- USR0 CoMACRsu [0xff08], [r4], rnd" 93047156 -d "- USR1 CoMACRsu [0xff08], [r4], rnd" 93047166 -d "CoMACRsu [0xff08], [r4], rnd" 93047106 -d "- USR0 CoMACRsu r3, r4, rnd" A3347156 -d "- USR1 CoMACRsu r3, r4, rnd" A3347166 -d "CoMACRsu r3, r4, rnd" A3347106 - -d "- USR0 CoMACRus r3, [r4]" 8334B056 -d "- USR1 CoMACRus r3, [r4]" 8334B066 -d "CoMACRus r3, [r4]" 8334B006 -d "- USR0 CoMACRus [0xff08], [r4]" 9304B056 -d "- USR1 CoMACRus [0xff08], [r4]" 9304B066 -d "CoMACRus [0xff08], [r4]" 9304B006 +d "- USR0 CoMACRsu r3, [r4+QR1], rnd" 83347156 +d "- USR1 CoMACRsu r3, [r4+QR1], rnd" 83347166 +d "CoMACRsu r3, [r4+QR1], rnd" 83347106 +d "- USR0 CoMACRsu [0xff08], [r4+QR1], rnd" 93047156 +d "- USR1 CoMACRsu [0xff08], [r4+QR1], rnd" 93047166 +d "CoMACRsu [0xff08], [r4+QR1], rnd" 93047106 +d "- USR0 CoMACRsu r3, [r4+QR1], rnd" a3347156 +d "- USR1 CoMACRsu r3, [r4+QR1], rnd" a3347166 +d "CoMACRsu r3, [r4+QR1], rnd" a3347106 + +d "- USR0 CoMACRus r3, [r4+QR1]" 8334b056 +d "- USR1 CoMACRus r3, [r4+QR1]" 8334b066 +d "CoMACRus r3, [r4+QR1]" 8334b006 +d "- USR0 CoMACRus [0xff08], [r4+QR1]" 9304b056 +d "- USR1 CoMACRus [0xff08], [r4+QR1]" 9304b066 +d "CoMACRus [0xff08], [r4+QR1]" 9304b006 d "- USR0 CoMACRus r3, r4" A334B056 d "- USR1 CoMACRus r3, r4" A334B066 d "CoMACRus r3, r4" A334B006 -d "- USR0 CoMACRus r3, [r4], rnd" 8334B156 -d "- USR1 CoMACRus r3, [r4], rnd" 8334B166 -d "CoMACRus r3, [r4], rnd" 8334B106 -d "- USR0 CoMACRus [0xff08], [r4], rnd" 9304B156 -d "- USR1 CoMACRus [0xff08], [r4], rnd" 9304B166 -d "CoMACRus [0xff08], [r4], rnd" 9304B106 -d "- USR0 CoMACRus r3, r4, rnd" A334B156 -d "- USR1 CoMACRus r3, r4, rnd" A334B166 -d "CoMACRus r3, r4, rnd" A334B106 - -d "- USR0 CoMACus- r3, [r4]" 8334A056 -d "- USR1 CoMACus- r3, [r4]" 8334A066 -d "CoMACus- r3, [r4]" 8334A006 -d "- USR0 CoMACus- [0xff08], [r4]" 9304A056 -d "- USR1 CoMACus- [0xff08], [r4]" 9304A066 -d "CoMACus- [0xff08], [r4]" 9304A006 +d "- USR0 CoMACRus r3, [r4+QR1], rnd" 8334b156 +d "- USR1 CoMACRus r3, [r4+QR1], rnd" 8334b166 +d "CoMACRus r3, [r4+QR1], rnd" 8334b106 +d "- USR0 CoMACRus [0xff08], [r4+QR1], rnd" 9304b156 +d "- USR1 CoMACRus [0xff08], [r4+QR1], rnd" 9304b166 +d "CoMACRus [0xff08], [r4+QR1], rnd" 9304b106 +d "- USR0 CoMACRus r3, [r4+QR1], rnd" a334b156 +d "- USR1 CoMACRus r3, [r4+QR1], rnd" a334b166 +d "CoMACRus r3, [r4+QR1], rnd" a334b106 + +d "- USR0 CoMACus- r3, [r4+QR1]" 8334a056 +d "- USR1 CoMACus- r3, [r4+QR1]" 8334a066 +d "CoMACus- r3, [r4+QR1]" 8334a006 +d "- USR0 CoMACus- [0xff08], [r4+QR1]" 9304a056 +d "- USR1 CoMACus- [0xff08], [r4+QR1]" 9304a066 +d "CoMACus- [0xff08], [r4+QR1]" 9304a006 d "- USR0 CoMACus- r3, r4" A334A056 d "- USR1 CoMACus- r3, r4" A334A066 d "CoMACus- r3, r4" A334A006 -d "- USR0 CoMACus r3, [r4]" 83349056 -d "- USR1 CoMACus r3, [r4]" 83349066 -d "CoMACus r3, [r4]" 83349006 -d "- USR0 CoMACus [0xff08], [r4]" 93049056 -d "- USR1 CoMACus [0xff08], [r4]" 93049066 -d "CoMACus [0xff08], [r4]" 93049006 +d "- USR0 CoMACus r3, [r4+QR1]" 83349056 +d "- USR1 CoMACus r3, [r4+QR1]" 83349066 +d "CoMACus r3, [r4+QR1]" 83349006 +d "- USR0 CoMACus [0xff08], [r4+QR1]" 93049056 +d "- USR1 CoMACus [0xff08], [r4+QR1]" 93049066 +d "CoMACus [0xff08], [r4+QR1]" 93049006 d "- USR0 CoMACus r3, r4" A3349056 d "- USR1 CoMACus r3, r4" A3349066 d "CoMACus r3, r4" A3349006 -d "- USR0 CoMACus r3, [r4], rnd" 83349156 -d "- USR1 CoMACus r3, [r4], rnd" 83349166 -d "CoMACus r3, [r4], rnd" 83349106 -d "- USR0 CoMACus [0xff08], [r4], rnd" 93049156 -d "- USR1 CoMACus [0xff08], [r4], rnd" 93049166 -d "CoMACus [0xff08], [r4], rnd" 93049106 -d "- USR0 CoMACus r3, r4, rnd" A3349156 -d "- USR1 CoMACus r3, r4, rnd" A3349166 -d "CoMACus r3, r4, rnd" A3349106 - -d "- USR0 CoMACRu r3, [r4]" 83343056 -d "- USR1 CoMACRu r3, [r4]" 83343066 -d "CoMACRu r3, [r4]" 83343006 -d "- USR0 CoMACRu [0xff08], [r4]" 93043056 -d "- USR1 CoMACRu [0xff08], [r4]" 93043066 -d "CoMACRu [0xff08], [r4]" 93043006 +d "- USR0 CoMACus r3, [r4+QR1], rnd" 83349156 +d "- USR1 CoMACus r3, [r4+QR1], rnd" 83349166 +d "CoMACus r3, [r4+QR1], rnd" 83349106 +d "- USR0 CoMACus [0xff08], [r4+QR1], rnd" 93049156 +d "- USR1 CoMACus [0xff08], [r4+QR1], rnd" 93049166 +d "CoMACus [0xff08], [r4+QR1], rnd" 93049106 +d "- USR0 CoMACus r3, [r4+QR1], rnd" a3349156 +d "- USR1 CoMACus r3, [r4+QR1], rnd" a3349166 +d "CoMACus r3, [r4+QR1], rnd" a3349106 + +d "- USR0 CoMACRu r3, [r4+QR1]" 83343056 +d "- USR1 CoMACRu r3, [r4+QR1]" 83343066 +d "CoMACRu r3, [r4+QR1]" 83343006 +d "- USR0 CoMACRu [0xff08], [r4+QR1]" 93043056 +d "- USR1 CoMACRu [0xff08], [r4+QR1]" 93043066 +d "CoMACRu [0xff08], [r4+QR1]" 93043006 d "- USR0 CoMACRu r3, r4" A3343056 d "- USR1 CoMACRu r3, r4" A3343066 d "CoMACRu r3, r4" A3343006 -d "- USR0 CoMACRu r3, [r4], rnd" 83343156 -d "- USR1 CoMACRu r3, [r4], rnd" 83343166 -d "CoMACRu r3, [r4], rnd" 83343106 -d "- USR0 CoMACRu [0xff08], [r4], rnd" 93043156 -d "- USR1 CoMACRu [0xff08], [r4], rnd" 93043166 -d "CoMACRu [0xff08], [r4], rnd" 93043106 -d "- USR0 CoMACRu r3, r4, rnd" A3343156 -d "- USR1 CoMACRu r3, r4, rnd" A3343166 -d "CoMACRu r3, r4, rnd" A3343106 - -d "- USR0 CoMACu r3, [r4]" 83341056 -d "- USR1 CoMACu r3, [r4]" 83341066 -d "CoMACu r3, [r4]" 83341006 -d "- USR0 CoMACu [0xff08], [r4]" 93041056 -d "- USR1 CoMACu [0xff08], [r4]" 93041066 -d "CoMACu [0xff08], [r4]" 93041006 +d "- USR0 CoMACRu r3, [r4+QR1], rnd" 83343156 +d "- USR1 CoMACRu r3, [r4+QR1], rnd" 83343166 +d "CoMACRu r3, [r4+QR1], rnd" 83343106 +d "- USR0 CoMACRu [0xff08], [r4+QR1], rnd" 93043156 +d "- USR1 CoMACRu [0xff08], [r4+QR1], rnd" 93043166 +d "CoMACRu [0xff08], [r4+QR1], rnd" 93043106 +d "- USR0 CoMACRu r3, [r4+QR1], rnd" a3343156 +d "- USR1 CoMACRu r3, [r4+QR1], rnd" a3343166 +d "CoMACRu r3, [r4+QR1], rnd" a3343106 + +d "- USR0 CoMACu r3, [r4+QR1]" 83341056 +d "- USR1 CoMACu r3, [r4+QR1]" 83341066 +d "CoMACu r3, [r4+QR1]" 83341006 +d "- USR0 CoMACu [0xff08], [r4+QR1]" 93041056 +d "- USR1 CoMACu [0xff08], [r4+QR1]" 93041066 +d "CoMACu [0xff08], [r4+QR1]" 93041006 d "- USR0 CoMACu r3, r4" A3341056 d "- USR1 CoMACu r3, r4" A3341066 d "CoMACu r3, r4" A3341006 -d "- USR0 CoMACu- r3, [r4]" 83342056 -d "- USR1 CoMACu- r3, [r4]" 83342066 -d "CoMACu- r3, [r4]" 83342006 -d "- USR0 CoMACu- [0xff08], [r4]" 93042056 -d "- USR1 CoMACu- [0xff08], [r4]" 93042066 -d "CoMACu- [0xff08], [r4]" 93042006 +d "- USR0 CoMACu- r3, [r4+QR1]" 83342056 +d "- USR1 CoMACu- r3, [r4+QR1]" 83342066 +d "CoMACu- r3, [r4+QR1]" 83342006 +d "- USR0 CoMACu- [0xff08], [r4+QR1]" 93042056 +d "- USR1 CoMACu- [0xff08], [r4+QR1]" 93042066 +d "CoMACu- [0xff08], [r4+QR1]" 93042006 d "- USR0 CoMACu- r3, r4" A3342056 d "- USR1 CoMACu- r3, r4" A3342066 d "CoMACu- r3, r4" A3342006 -d "- USR0 CoMULsu r3, [r4]" 83344056 -d "- USR1 CoMULsu r3, [r4]" 83344066 -d "CoMULsu r3, [r4]" 83344006 -d "- USR0 CoMULsu [0xff08], [r4]" 93044056 -d "- USR1 CoMULsu [0xff08], [r4]" 93044066 -d "CoMULsu [0xff08], [r4]" 93044006 +d "- USR0 CoMULsu r3, [r4+QR1]" 83344056 +d "- USR1 CoMULsu r3, [r4+QR1]" 83344066 +d "CoMULsu r3, [r4+QR1]" 83344006 +d "- USR0 CoMULsu [0xff08], [r4+QR1]" 93044056 +d "- USR1 CoMULsu [0xff08], [r4+QR1]" 93044066 +d "CoMULsu [0xff08], [r4+QR1]" 93044006 d "- USR0 CoMULsu r3, r4" A3344056 d "- USR1 CoMULsu r3, r4" A3344066 d "CoMULsu r3, r4" A3344006 -d "- USR0 CoMULsu r3, [r4], rnd" 83344156 -d "- USR1 CoMULsu r3, [r4], rnd" 83344166 -d "CoMULsu r3, [r4], rnd" 83344106 -d "- USR0 CoMULsu [0xff08], [r4], rnd" 93044156 -d "- USR1 CoMULsu [0xff08], [r4], rnd" 93044166 -d "CoMULsu [0xff08], [r4], rnd" 93044106 -d "- USR0 CoMULsu r3, r4, rnd" A3344156 -d "- USR1 CoMULsu r3, r4, rnd" A3344166 -d "CoMULsu r3, r4, rnd" A3344106 - -d "- USR0 CoMACsu r3, [r4]" 83345056 -d "- USR1 CoMACsu r3, [r4]" 83345066 -d "CoMACsu r3, [r4]" 83345006 -d "- USR0 CoMACsu [0xff08], [r4]" 93045056 -d "- USR1 CoMACsu [0xff08], [r4]" 93045066 -d "CoMACsu [0xff08], [r4]" 93045006 +d "- USR0 CoMULsu r3, [r4+QR1], rnd" 83344156 +d "- USR1 CoMULsu r3, [r4+QR1], rnd" 83344166 +d "CoMULsu r3, [r4+QR1], rnd" 83344106 +d "- USR0 CoMULsu [0xff08], [r4+QR1], rnd" 93044156 +d "- USR1 CoMULsu [0xff08], [r4+QR1], rnd" 93044166 +d "CoMULsu [0xff08], [r4+QR1], rnd" 93044106 +d "- USR0 CoMULsu r3, [r4+QR1], rnd" a3344156 +d "- USR1 CoMULsu r3, [r4+QR1], rnd" a3344166 +d "CoMULsu r3, [r4+QR1], rnd" a3344106 + +d "- USR0 CoMACsu r3, [r4+QR1]" 83345056 +d "- USR1 CoMACsu r3, [r4+QR1]" 83345066 +d "CoMACsu r3, [r4+QR1]" 83345006 +d "- USR0 CoMACsu [0xff08], [r4+QR1]" 93045056 +d "- USR1 CoMACsu [0xff08], [r4+QR1]" 93045066 +d "CoMACsu [0xff08], [r4+QR1]" 93045006 d "- USR0 CoMACsu r3, r4" A3345056 d "- USR1 CoMACsu r3, r4" A3345066 d "CoMACsu r3, r4" A3345006 -d "- USR0 CoMACsu r3, [r4], rnd" 83345156 -d "- USR1 CoMACsu r3, [r4], rnd" 83345166 -d "CoMACsu r3, [r4], rnd" 83345106 -d "- USR0 CoMACsu [0xff08], [r4], rnd" 93045156 -d "- USR1 CoMACsu [0xff08], [r4], rnd" 93045166 -d "CoMACsu [0xff08], [r4], rnd" 93045106 -d "- USR0 CoMACsu r3, r4, rnd" A3345156 -d "- USR1 CoMACsu r3, r4, rnd" A3345166 -d "CoMACsu r3, r4, rnd" A3345106 +d "- USR0 CoMACsu r3, [r4+QR1], rnd" 83345156 +d "- USR1 CoMACsu r3, [r4+QR1], rnd" 83345166 +d "CoMACsu r3, [r4+QR1], rnd" 83345106 +d "- USR0 CoMACsu [0xff08], [r4+QR1], rnd" 93045156 +d "- USR1 CoMACsu [0xff08], [r4+QR1], rnd" 93045166 +d "CoMACsu [0xff08], [r4+QR1], rnd" 93045106 +d "- USR0 CoMACsu r3, [r4+QR1], rnd" a3345156 +d "- USR1 CoMACsu r3, [r4+QR1], rnd" a3345166 +d "CoMACsu r3, [r4+QR1], rnd" a3345106 d ".word 0xa334 .word 0x6156" A3346156 d ".word 0xa334 .word 0xa156" A334A156 d ".word 0xa334 .word 0xe156" A334E156 -d "- USR0 CoMUL r3, [r4]" 8334C056 -d "- USR1 CoMUL r3, [r4]" 8334C066 -d "CoMUL r3, [r4]" 8334C006 -d "- USR0 CoMUL [0xff08], [r4]" 9304C056 -d "- USR1 CoMUL [0xff08], [r4]" 9304C066 -d "CoMUL [0xff08], [r4]" 9304C006 +d "- USR0 CoMUL r3, [r4+QR1]" 8334c056 +d "- USR1 CoMUL r3, [r4+QR1]" 8334c066 +d "CoMUL r3, [r4+QR1]" 8334c006 +d "- USR0 CoMUL [0xff08], [r4+QR1]" 9304c056 +d "- USR1 CoMUL [0xff08], [r4+QR1]" 9304c066 +d "CoMUL [0xff08], [r4+QR1]" 9304c006 d "- USR0 CoMUL r3, r4" A334C056 d "- USR1 CoMUL r3, r4" A334C066 d "CoMUL r3, r4" A334C006 -d "- USR0 CoMUL r3, [r4], rnd" 8334C156 -d "- USR1 CoMUL r3, [r4], rnd" 8334C166 -d "CoMUL r3, [r4], rnd" 8334C106 -d "- USR0 CoMUL [0xff08], [r4], rnd" 9304C156 -d "- USR1 CoMUL [0xff08], [r4], rnd" 9304C166 -d "CoMUL [0xff08], [r4], rnd" 9304C106 -d "- USR0 CoMUL r3, r4, rnd" A334C156 -d "- USR1 CoMUL r3, r4, rnd" A334C166 -d "CoMUL r3, r4, rnd" A334C106 - -d "- USR0 CoMAC r3, [r4]" 8334D056 -d "- USR1 CoMAC r3, [r4]" 8334D066 -d "CoMAC r3, [r4]" 8334D006 -d "- USR0 CoMAC [0xff08], [r4]" 9304D056 -d "- USR1 CoMAC [0xff08], [r4]" 9304D066 -d "CoMAC [0xff08], [r4]" 9304D006 +d "- USR0 CoMUL r3, [r4+QR1], rnd" 8334c156 +d "- USR1 CoMUL r3, [r4+QR1], rnd" 8334c166 +d "CoMUL r3, [r4+QR1], rnd" 8334c106 +d "- USR0 CoMUL [0xff08], [r4+QR1], rnd" 9304c156 +d "- USR1 CoMUL [0xff08], [r4+QR1], rnd" 9304c166 +d "CoMUL [0xff08], [r4+QR1], rnd" 9304c106 +d "- USR0 CoMUL r3, [r4+QR1], rnd" a334c156 +d "- USR1 CoMUL r3, [r4+QR1], rnd" a334c166 +d "CoMUL r3, [r4+QR1], rnd" a334c106 + +d "- USR0 CoMAC r3, [r4+QR1]" 8334d056 +d "- USR1 CoMAC r3, [r4+QR1]" 8334d066 +d "CoMAC r3, [r4+QR1]" 8334d006 +d "- USR0 CoMAC [0xff08], [r4+QR1]" 9304d056 +d "- USR1 CoMAC [0xff08], [r4+QR1]" 9304d066 +d "CoMAC [0xff08], [r4+QR1]" 9304d006 d "- USR0 CoMAC r3, r4" A334D056 d "- USR1 CoMAC r3, r4" A334D066 d "CoMAC r3, r4" A334D006 -d "- USR0 CoMAC r3, [r4], rnd" 8334D156 -d "- USR1 CoMAC r3, [r4], rnd" 8334D166 -d "CoMAC r3, [r4], rnd" 8334D106 -d "- USR0 CoMAC [0xff08], [r4], rnd" 9304D156 -d "- USR1 CoMAC [0xff08], [r4], rnd" 9304D166 -d "CoMAC [0xff08], [r4], rnd" 9304D106 -d "- USR0 CoMAC r3, r4, rnd" A334D156 -d "- USR1 CoMAC r3, r4, rnd" A334D166 -d "CoMAC r3, r4, rnd" A334D106 - -d "- USR0 CoMAC- r3, [r4]" 8334E056 -d "- USR1 CoMAC- r3, [r4]" 8334E066 -d "CoMAC- r3, [r4]" 8334E006 -d "- USR0 CoMAC- [0xff08], [r4]" 9304E056 -d "- USR1 CoMAC- [0xff08], [r4]" 9304E066 -d "CoMAC- [0xff08], [r4]" 9304E006 +d "- USR0 CoMAC r3, [r4+QR1], rnd" 8334d156 +d "- USR1 CoMAC r3, [r4+QR1], rnd" 8334d166 +d "CoMAC r3, [r4+QR1], rnd" 8334d106 +d "- USR0 CoMAC [0xff08], [r4+QR1], rnd" 9304d156 +d "- USR1 CoMAC [0xff08], [r4+QR1], rnd" 9304d166 +d "CoMAC [0xff08], [r4+QR1], rnd" 9304d106 +d "- USR0 CoMAC r3, [r4+QR1], rnd" a334d156 +d "- USR1 CoMAC r3, [r4+QR1], rnd" a334d166 +d "CoMAC r3, [r4+QR1], rnd" a334d106 + +d "- USR0 CoMAC- r3, [r4+QR1]" 8334e056 +d "- USR1 CoMAC- r3, [r4+QR1]" 8334e066 +d "CoMAC- r3, [r4+QR1]" 8334e006 +d "- USR0 CoMAC- [0xff08], [r4+QR1]" 9304e056 +d "- USR1 CoMAC- [0xff08], [r4+QR1]" 9304e066 +d "CoMAC- [0xff08], [r4+QR1]" 9304e006 d "- USR0 CoMAC- r3, r4" A334E056 d "- USR1 CoMAC- r3, r4" A334E066 d "CoMAC- r3, r4" A334E006 -d "- USR0 CoMACR r3, [r4]" 8334F056 -d "- USR1 CoMACR r3, [r4]" 8334F066 -d "CoMACR r3, [r4]" 8334F006 -d "- USR0 CoMACR [0xff08], [r4]" 9304F056 -d "- USR1 CoMACR [0xff08], [r4]" 9304F066 -d "CoMACR [0xff08], [r4]" 9304F006 +d "- USR0 CoMACR r3, [r4+QR1]" 8334f056 +d "- USR1 CoMACR r3, [r4+QR1]" 8334f066 +d "CoMACR r3, [r4+QR1]" 8334f006 +d "- USR0 CoMACR [0xff08], [r4+QR1]" 9304f056 +d "- USR1 CoMACR [0xff08], [r4+QR1]" 9304f066 +d "CoMACR [0xff08], [r4+QR1]" 9304f006 d "- USR0 CoMACR r3, r4" A334F056 d "- USR1 CoMACR r3, r4" A334F066 d "CoMACR r3, r4" A334F006 @@ -741,79 +755,79 @@ d "CoMACR r3, r4" A334F006 #d "CoMACR r3, [r4], rnd ???" 8334A156 #d "CoMACR r3, [r4], rnd ???" 8334E156 -d "- USR0 CoMACR r3, [r4], rnd" 8334F156 -d "- USR1 CoMACR r3, [r4], rnd" 8334F166 -d "CoMACR r3, [r4], rnd" 8334F106 -d "- USR0 CoMACR [0xff08], [r4], rnd" 9304F156 -d "- USR1 CoMACR [0xff08], [r4], rnd" 9304F166 -d "CoMACR [0xff08], [r4], rnd" 9304F106 -d "- USR0 CoMACR r3, r4, rnd" A334F156 -d "- USR1 CoMACR r3, r4, rnd" A334F166 -d "CoMACR r3, r4, rnd" A334F106 +d "- USR0 CoMACR r3, [r4+QR1], rnd" 8334f156 +d "- USR1 CoMACR r3, [r4+QR1], rnd" 8334f166 +d "CoMACR r3, [r4+QR1], rnd" 8334f106 +d "- USR0 CoMACR [0xff08], [r4+QR1], rnd" 9304f156 +d "- USR1 CoMACR [0xff08], [r4+QR1], rnd" 9304f166 +d "CoMACR [0xff08], [r4+QR1], rnd" 9304f106 +d "- USR0 CoMACR r3, [r4+QR1], rnd" a334f156 +d "- USR1 CoMACR r3, [r4+QR1], rnd" a334f166 +d "CoMACR r3, [r4+QR1], rnd" a334f106 d ".word 0x9334 .word 0x2156" 93342156 d ".word 0x9334 .word 0x6156" 93346156 d ".word 0x9334 .word 0xa156" 9334A156 d ".word 0x9334 .word 0xe156" 9334E156 -d "- USR0 CoADD r3, [r4]" 83340256 -d "- USR1 CoADD r3, [r4]" 83340266 -d "CoADD r3, [r4]" 83340206 -d "- USR0 CoADD [0xff08], [r4]" 93040256 -d "- USR1 CoADD [0xff08], [r4]" 93040266 -d "CoADD [0xff08], [r4]" 93040206 +d "- USR0 CoADD r3, [r4+QR1]]" 83340256 +d "- USR1 CoADD r3, [r4+QR1]]" 83340266 +d "CoADD r3, [r4+QR1]]" 83340206 +d "- USR0 CoADD [0xff08], [r4+QR1]" 93040256 +d "- USR1 CoADD [0xff08], [r4+QR1]" 93040266 +d "CoADD [0xff08], [r4+QR1]" 93040206 d "- USR0 CoADD r3, r4" A3340256 d "- USR1 CoADD r3, r4" A3340266 d "CoADD r3, r4" A3340206 -d "- USR0 CoSUBR r3, [r4]" 83341256 -d "- USR1 CoSUBR r3, [r4]" 83341266 -d "CoSUBR r3, [r4]" 83341206 -d "- USR0 CoSUBR [0xff08], [r4]" 93041256 -d "- USR1 CoSUBR [0xff08], [r4]" 93041266 -d "CoSUBR [0xff08], [r4]" 93041206 +d "- USR0 CoSUBR r3, [r4+QR1]]" 83341256 +d "- USR1 CoSUBR r3, [r4+QR1]]" 83341266 +d "CoSUBR r3, [r4+QR1]]" 83341206 +d "- USR0 CoSUBR [0xff08], [r4+QR1]" 93041256 +d "- USR1 CoSUBR [0xff08], [r4+QR1]" 93041266 +d "CoSUBR [0xff08], [r4+QR1]" 93041206 d "- USR0 CoSUBR r3, r4" A3341256 d "- USR1 CoSUBR r3, r4" A3341266 d "CoSUBR r3, r4" A3341206 -d "- USR0 CoLOAD r3, [r4]" 83342256 -d "- USR1 CoLOAD r3, [r4]" 83342266 -d "CoLOAD r3, [r4]" 83342206 -d "- USR0 CoLOAD [0xff08], [r4]" 93042256 -d "- USR1 CoLOAD [0xff08], [r4]" 93042266 -d "CoLOAD [0xff08], [r4]" 93042206 +d "- USR0 CoLOAD r3, [r4+QR1]]" 83342256 +d "- USR1 CoLOAD r3, [r4+QR1]]" 83342266 +d "CoLOAD r3, [r4+QR1]]" 83342206 +d "- USR0 CoLOAD [0xff08], [r4+QR1]" 93042256 +d "- USR1 CoLOAD [0xff08], [r4+QR1]" 93042266 +d "CoLOAD [0xff08], [r4+QR1]" 93042206 d "- USR0 CoLOAD r3, r4" A3342256 d "- USR1 CoLOAD r3, r4" A3342266 d "CoLOAD r3, r4" A3342206 d ".word 0x8334 .word 0x3256" 83343256 -d "- USR0 CoADD2 r3, [r4]" 83344256 -d "- USR1 CoADD2 r3, [r4]" 83344266 -d "CoADD2 r3, [r4]" 83344206 -d "- USR0 CoADD2 [0xff08], [r4]" 93044256 -d "- USR1 CoADD2 [0xff08], [r4]" 93044266 -d "CoADD2 [0xff08], [r4]" 93044206 +d "- USR0 CoADD2 r3, [r4+QR1]]" 83344256 +d "- USR1 CoADD2 r3, [r4+QR1]]" 83344266 +d "CoADD2 r3, [r4+QR1]]" 83344206 +d "- USR0 CoADD2 [0xff08], [r4+QR1]" 93044256 +d "- USR1 CoADD2 [0xff08], [r4+QR1]" 93044266 +d "CoADD2 [0xff08], [r4+QR1]" 93044206 d "- USR0 CoADD2 r3, r4" A3344256 d "- USR1 CoADD2 r3, r4" A3344266 d "CoADD2 r3, r4" A3344206 -d "- USR0 CoSUB2R r3, [r4]" 83345256 -d "- USR1 CoSUB2R r3, [r4]" 83345266 -d "CoSUB2R r3, [r4]" 83345206 -d "- USR0 CoSUB2R [0xff08], [r4]" 93045256 -d "- USR1 CoSUB2R [0xff08], [r4]" 93045266 -d "CoSUB2R [0xff08], [r4]" 93045206 +d "- USR0 CoSUB2R r3, [r4+QR1]]" 83345256 +d "- USR1 CoSUB2R r3, [r4+QR1]]" 83345266 +d "CoSUB2R r3, [r4+QR1]]" 83345206 +d "- USR0 CoSUB2R [0xff08], [r4+QR1]" 93045256 +d "- USR1 CoSUB2R [0xff08], [r4+QR1]" 93045266 +d "CoSUB2R [0xff08], [r4+QR1]" 93045206 d "- USR0 CoSUB2R r3, r4" A3345256 d "- USR1 CoSUB2R r3, r4" A3345266 d "CoSUB2R r3, r4" A3345206 -d "- USR0 CoLOAD2 r3, [r4]" 83346256 -d "- USR1 CoLOAD2 r3, [r4]" 83346266 -d "CoLOAD2 r3, [r4]" 83346206 -d "- USR0 CoLOAD2 [0xff08], [r4]" 93046256 -d "- USR1 CoLOAD2 [0xff08], [r4]" 93046266 -d "CoLOAD2 [0xff08], [r4]" 93046206 +d "- USR0 CoLOAD2 r3, [r4+QR1]]" 83346256 +d "- USR1 CoLOAD2 r3, [r4+QR1]]" 83346266 +d "CoLOAD2 r3, [r4+QR1]]" 83346206 +d "- USR0 CoLOAD2 [0xff08], [r4+QR1]" 93046256 +d "- USR1 CoLOAD2 [0xff08], [r4+QR1]" 93046266 +d "CoLOAD2 [0xff08], [r4+QR1]" 93046206 d "- USR0 CoLOAD2 r3, r4" A3346256 d "- USR1 CoLOAD2 r3, r4" A3346266 d "CoLOAD2 r3, r4" A3346206 @@ -825,74 +839,74 @@ d ".word 0xa334 .word 0xd256" A334D256 d ".word 0xa334 .word 0xe256" A334E256 d ".word 0xa334 .word 0xf256" A334F256 -d "- USR0 CoCMP r3, [r4]" 8334C256 -d "- USR1 CoCMP r3, [r4]" 8334C266 -d "CoCMP r3, [r4]" 8334C206 -d "- USR0 CoCMP [0xff08], [r4]" 9304C256 -d "- USR1 CoCMP [0xff08], [r4]" 9304C266 -d "CoCMP [0xff08], [r4]" 9304C206 +d "- USR0 CoCMP r3, [r4+QR1]]" 8334c256 +d "- USR1 CoCMP r3, [r4+QR1]]" 8334c266 +d "CoCMP r3, [r4+QR1]]" 8334c206 +d "- USR0 CoCMP [0xff08], [r4+QR1]" 9304c256 +d "- USR1 CoCMP [0xff08], [r4+QR1]" 9304c266 +d "CoCMP [0xff08], [r4+QR1]" 9304c206 d "- USR0 CoCMP r3, r4" A334C256 d "- USR1 CoCMP r3, r4" A334C266 d "CoCMP r3, r4" A334C206 -d "- USR0 CoSUB r3, [r4]" 83340A56 -d "- USR1 CoSUB r3, [r4]" 83340A66 -d "CoSUB r3, [r4]" 83340A06 -d "- USR0 CoSUB [0xff08], [r4]" 93040A56 -d "- USR1 CoSUB [0xff08], [r4]" 93040A66 -d "CoSUB [0xff08], [r4]" 93040A06 +d "- USR0 CoSUB r3, [r4+QR1]" 83340a56 +d "- USR1 CoSUB r3, [r4+QR1]" 83340a66 +d "CoSUB r3, [r4+QR1]" 83340a06 +d "- USR0 CoSUB [0xff08], [r4+QR1]" 93040a56 +d "- USR1 CoSUB [0xff08], [r4+QR1]" 93040a66 +d "CoSUB [0xff08], [r4+QR1]" 93040a06 d "- USR0 CoSUB r3, r4" A3340A56 d "- USR1 CoSUB r3, r4" A3340A66 d "CoSUB r3, r4" A3340A06 -d "- USR0 CoLOAD- r3, [r4]" 83342A56 -d "- USR1 CoLOAD- r3, [r4]" 83342A66 -d "CoLOAD- r3, [r4]" 83342A06 -d "- USR0 CoLOAD- [0xff08], [r4]" 93042A56 -d "- USR1 CoLOAD- [0xff08], [r4]" 93042A66 -d "CoLOAD- [0xff08], [r4]" 93042A06 +d "- USR0 CoLOAD- r3, [r4+QR1]" 83342a56 +d "- USR1 CoLOAD- r3, [r4+QR1]" 83342a66 +d "CoLOAD- r3, [r4+QR1]" 83342a06 +d "- USR0 CoLOAD- [0xff08], [r4+QR1]" 93042a56 +d "- USR1 CoLOAD- [0xff08], [r4+QR1]" 93042a66 +d "CoLOAD- [0xff08], [r4+QR1]" 93042a06 d "- USR0 CoLOAD- r3, r4" A3342A56 d "- USR1 CoLOAD- r3, r4" A3342A66 d "CoLOAD- r3, r4" A3342A06 -d "- USR0 CoMAX r3, [r4]" 83343A56 -d "- USR1 CoMAX r3, [r4]" 83343A66 -d "CoMAX r3, [r4]" 83343A06 -d "- USR0 CoMAX [0xff08], [r4]" 93043A56 -d "- USR1 CoMAX [0xff08], [r4]" 93043A66 -d "CoMAX [0xff08], [r4]" 93043A06 +d "- USR0 CoMAX r3, [r4+QR1]" 83343a56 +d "- USR1 CoMAX r3, [r4+QR1]" 83343a66 +d "CoMAX r3, [r4+QR1]" 83343a06 +d "- USR0 CoMAX [0xff08], [r4+QR1]" 93043a56 +d "- USR1 CoMAX [0xff08], [r4+QR1]" 93043a66 +d "CoMAX [0xff08], [r4+QR1]" 93043a06 d "- USR0 CoMAX r3, r4" A3343A56 d "- USR1 CoMAX r3, r4" A3343A66 d "CoMAX r3, r4" A3343A06 -d "- USR0 CoSUB2 r3, [r4]" 83344A56 -d "- USR1 CoSUB2 r3, [r4]" 83344A66 -d "CoSUB2 r3, [r4]" 83344A06 -d "- USR0 CoSUB2 [0xff08], [r4]" 93044A56 -d "- USR1 CoSUB2 [0xff08], [r4]" 93044A66 -d "CoSUB2 [0xff08], [r4]" 93044A06 +d "- USR0 CoSUB2 r3, [r4+QR1]" 83344a56 +d "- USR1 CoSUB2 r3, [r4+QR1]" 83344a66 +d "CoSUB2 r3, [r4+QR1]" 83344a06 +d "- USR0 CoSUB2 [0xff08], [r4+QR1]" 93044a56 +d "- USR1 CoSUB2 [0xff08], [r4+QR1]" 93044a66 +d "CoSUB2 [0xff08], [r4+QR1]" 93044a06 d "- USR0 CoSUB2 r3, r4" A3344A56 d "- USR1 CoSUB2 r3, r4" A3344A66 d "CoSUB2 r3, r4" A3344A06 d ".word 0x8334 .word 0x5a56" 83345A56 -d "- USR0 CoLOAD2- r3, [r4]" 83346A56 -d "- USR1 CoLOAD2- r3, [r4]" 83346A66 -d "CoLOAD2- r3, [r4]" 83346A06 -d "- USR0 CoLOAD2- [0xff08], [r4]" 93046A56 -d "- USR1 CoLOAD2- [0xff08], [r4]" 93046A66 -d "CoLOAD2- [0xff08], [r4]" 93046A06 +d "- USR0 CoLOAD2- r3, [r4+QR1]" 83346a56 +d "- USR1 CoLOAD2- r3, [r4+QR1]" 83346a66 +d "CoLOAD2- r3, [r4+QR1]" 83346a06 +d "- USR0 CoLOAD2- [0xff08], [r4+QR1]" 93046a56 +d "- USR1 CoLOAD2- [0xff08], [r4+QR1]" 93046a66 +d "CoLOAD2- [0xff08], [r4+QR1]" 93046a06 d ".word 0xa334 .word 0x5a56" A3345A56 d "- USR0 CoLOAD2- r3, r4" A3346A56 d "- USR1 CoLOAD2- r3, r4" A3346A66 d "CoLOAD2- r3, r4" A3346A06 -d "- USR0 CoMIN r3, [r4]" 83347A56 -d "- USR1 CoMIN r3, [r4]" 83347A66 -d "CoMIN r3, [r4]" 83347A06 -d "- USR0 CoMIN [0xff08], [r4]" 93047A56 -d "- USR1 CoMIN [0xff08], [r4]" 93047A66 -d "CoMIN [0xff08], [r4]" 93047A06 +d "- USR0 CoMIN r3, [r4+QR1]" 83347a56 +d "- USR1 CoMIN r3, [r4+QR1]" 83347a66 +d "CoMIN r3, [r4+QR1]" 83347a06 +d "- USR0 CoMIN [0xff08], [r4+QR1]" 93047a56 +d "- USR1 CoMIN [0xff08], [r4+QR1]" 93047a66 +d "CoMIN [0xff08], [r4+QR1]" 93047a06 d "- USR0 CoMIN r3, r4" A3347A56 d "- USR1 CoMIN r3, r4" A3347A66 d "CoMIN r3, r4" A3347A06 @@ -900,21 +914,21 @@ d "- USR0 CoMIN r3, r4" A3347A56 d "- USR1 CoMIN r3, r4" A3347A66 d "CoMIN r3, r4" A3347A06 -d "- USR0 CoSHL [r8]" 83888A56 -d "- USR1 CoSHL [r8]" 83888A66 -d "CoSHL [r8]" 83888A06 -d "- USR0 CoSHR [r0]" 83009A56 -d "- USR1 CoSHR [r0]" 83009A66 -d "CoSHR [r0]" 83009A06 -d "- USR0 CoABS r3, [r4]" 8334CA56 -d "- USR1 CoABS r3, [r4]" 8334CA66 -d "CoABS r3, [r4]" 8334CA06 +d "- USR0 CoSHL [r8+QR1]" 83888a56 +d "- USR1 CoSHL [r8+QR1]" 83888a66 +d "CoSHL [r8+QR1]" 83888a06 +d "- USR0 CoSHR [r0+QR1]" 83009a56 +d "- USR1 CoSHR [r0+QR1]" 83009a66 +d "CoSHR [r0+QR1]" 83009a06 +d "- USR0 CoABS r3, [r4+QR1]" 8334ca56 +d "- USR1 CoABS r3, [r4+QR1]" 8334ca66 +d "CoABS r3, [r4+QR1]" 8334ca06 d ".word 0x8334 .word 0xda56" 8334DA56 d ".word 0x8334 .word 0xea56" 8334EA56 d ".word 0x8334 .word 0xfa56" 8334FA56 -d "- USR0 CoABS [0xff08], [r4]" 9304CA56 -d "- USR1 CoABS [0xff08], [r4]" 9304CA66 -d "CoABS [0xff08], [r4]" 9304CA06 +d "- USR0 CoABS [0xff08], [r4+QR1]" 9304ca56 +d "- USR1 CoABS [0xff08], [r4+QR1]" 9304ca66 +d "CoABS [0xff08], [r4+QR1]" 9304ca06 d "- USR0 CoASHR r3, rnd" A334BA56 d "- USR1 CoASHR r3, rnd" A334BA66 d "CoASHR r3, rnd" A334BA06 @@ -922,22 +936,22 @@ d ".word 0xa334 .word 0xda56" A334DA56 d ".word 0xa334 .word 0xea56" A334EA56 d ".word 0xa334 .word 0xfa56" A334FA56 -d "- USR0 CoMULsu- r3, [r4]" 83344856 -d "- USR1 CoMULsu- r3, [r4]" 83344866 -d "CoMULsu- r3, [r4]" 83344806 -d "- USR0 CoMULsu- [0xff08], [r4]" 93044856 -d "- USR1 CoMULsu- [0xff08], [r4]" 93044866 -d "CoMULsu- [0xff08], [r4]" 93044806 +d "- USR0 CoMULsu- r3, [r4+QR1]" 83344856 +d "- USR1 CoMULsu- r3, [r4+QR1]" 83344866 +d "CoMULsu- r3, [r4+QR1]" 83344806 +d "- USR0 CoMULsu- [0xff08], [r4+QR1]" 93044856 +d "- USR1 CoMULsu- [0xff08], [r4+QR1]" 93044866 +d "CoMULsu- [0xff08], [r4+QR1]" 93044806 d "- USR0 CoMULsu- r3, r4" A3344856 d "- USR1 CoMULsu- r3, r4" A3344866 d "CoMULsu- r3, r4" A3344806 -d "- USR0 CoMUL- r3, [r4]" 8334C856 -d "- USR1 CoMUL- r3, [r4]" 8334C866 -d "CoMUL- r3, [r4]" 8334C806 -d "- USR0 CoMUL- [0xff08], [r4]" 9304C856 -d "- USR1 CoMUL- [0xff08], [r4]" 9304C866 -d "CoMUL- [0xff08], [r4]" 9304C806 +d "- USR0 CoMUL- r3, [r4+QR1]" 8334c856 +d "- USR1 CoMUL- r3, [r4+QR1]" 8334c866 +d "CoMUL- r3, [r4+QR1]" 8334c806 +d "- USR0 CoMUL- [0xff08], [r4+QR1]" 9304c856 +d "- USR1 CoMUL- [0xff08], [r4+QR1]" 9304c866 +d "CoMUL- [0xff08], [r4+QR1]" 9304c806 d "- USR0 CoMUL- r3, r4" A334C856 d "- USR1 CoMUL- r3, r4" A334C866 d "CoMUL- r3, r4" A334C806 @@ -951,14 +965,14 @@ d ".word 0x9334 .word 0xfa56" 9334FA56 d ".word 0xa334 .word 0x1856" A3341856 d ".word 0x8334 .word 0x1856" 83341856 -d "- USR0 CoMACMu [0xff08], [r4]" 93041856 -d "- USR1 CoMACMu [0xff08], [r4]" 93041866 -d "CoMACMu [0xff08], [r4]" 93041806 +d "- USR0 CoMACMu [0xff08], [r4+QR1]" 93041856 +d "- USR1 CoMACMu [0xff08], [r4+QR1]" 93041866 +d "CoMACMu [0xff08], [r4+QR1]" 93041806 d ".word 0xa334 .word 0x1956" A3341956 d ".word 0x8334 .word 0x1956" 83341956 -d "- USR0 CoMACMu [0xff08], [r4], rnd" 93041956 -d "- USR1 CoMACMu [0xff08], [r4], rnd" 93041966 -d "CoMACMu [0xff08], [r4], rnd" 93041906 +d "- USR0 CoMACMu [0xff08], [r4+QR1], rnd" 93041956 +d "- USR1 CoMACMu [0xff08], [r4+QR1], rnd" 93041966 +d "CoMACMu [0xff08], [r4+QR1], rnd" 93041906 d ".word 0x9334 .word 0x0956" 93340956 d ".word 0x9334 .word 0x2956" 93342956 @@ -971,140 +985,136 @@ d ".word 0x9334 .word 0xe956" 9334e956 d ".word 0xa334 .word 0x3856" A3343856 d ".word 0x8334 .word 0x3856" 83343856 -d "- USR0 CoMACMRu [0xff08], [r4]" 93043856 -d "- USR1 CoMACMRu [0xff08], [r4]" 93043866 -d "CoMACMRu [0xff08], [r4]" 93043806 +d "- USR0 CoMACMRu [0xff08], [r4+QR1]" 93043856 +d "- USR1 CoMACMRu [0xff08], [r4+QR1]" 93043866 +d "CoMACMRu [0xff08], [r4+QR1]" 93043806 d ".word 0xa334 .word 0x3956" A3343956 d ".word 0x8334 .word 0x3956" 83343956 -d "- USR0 CoMACMRu [0xff08], [r4], rnd" 93043956 -d "- USR1 CoMACMRu [0xff08], [r4], rnd" 93043966 -d "CoMACMRu [0xff08], [r4], rnd" 93043906 +d "- USR0 CoMACMRu [0xff08], [r4+QR1], rnd" 93043956 +d "- USR1 CoMACMRu [0xff08], [r4+QR1], rnd" 93043966 +d "CoMACMRu [0xff08], [r4+QR1], rnd" 93043906 d ".word 0xa334 .word 0x5856" A3345856 d ".word 0x8334 .word 0x5856" 83345856 -d "- USR0 CoMACMsu [0xff08], [r4]" 93045856 -d "- USR1 CoMACMsu [0xff08], [r4]" 93045866 -d "CoMACMsu [0xff08], [r4]" 93045806 +d "- USR0 CoMACMsu [0xff08], [r4+QR1]" 93045856 +d "- USR1 CoMACMsu [0xff08], [r4+QR1]" 93045866 +d "CoMACMsu [0xff08], [r4+QR1]" 93045806 d ".word 0xa334 .word 0x5956" A3345956 d ".word 0x8334 .word 0x5956" 83345956 -d "- USR0 CoMACMsu [0xff08], [r4], rnd" 93045956 -d "- USR1 CoMACMsu [0xff08], [r4], rnd" 93045966 -d "CoMACMsu [0xff08], [r4], rnd" 93045906 +d "- USR0 CoMACMsu [0xff08], [r4+QR1], rnd" 93045956 +d "- USR1 CoMACMsu [0xff08], [r4+QR1], rnd" 93045966 +d "CoMACMsu [0xff08], [r4+QR1], rnd" 93045906 d ".word 0xa334 .word 0x7856" A3347856 d ".word 0x8334 .word 0x7856" 83347856 -d "- USR0 CoMACMRsu [0xff08], [r4]" 93047856 -d "- USR1 CoMACMRsu [0xff08], [r4]" 93047866 -d "CoMACMRsu [0xff08], [r4]" 93047806 +d "- USR0 CoMACMRsu [0xff08], [r4+QR1]" 93047856 +d "- USR1 CoMACMRsu [0xff08], [r4+QR1]" 93047866 +d "CoMACMRsu [0xff08], [r4+QR1]" 93047806 d ".word 0xa334 .word 0x7956" A3347956 d ".word 0x8334 .word 0x7956" 83347956 -d "- USR0 CoMACMRsu [0xff08], [r4], rnd" 93047956 -d "- USR1 CoMACMRsu [0xff08], [r4], rnd" 93047966 -d "CoMACMRsu [0xff08], [r4], rnd" 93047906 +d "- USR0 CoMACMRsu [0xff08], [r4+QR1], rnd" 93047956 +d "- USR1 CoMACMRsu [0xff08], [r4+QR1], rnd" 93047966 +d "CoMACMRsu [0xff08], [r4+QR1], rnd" 93047906 d ".word 0xa334 .word 0x9856" A3349856 d ".word 0x8334 .word 0x9856" 83349856 -d "- USR0 CoMACMus [0xff08], [r4]" 93049856 -d "- USR1 CoMACMus [0xff08], [r4]" 93049866 -d "CoMACMus [0xff08], [r4]" 93049806 +d "- USR0 CoMACMus [0xff08], [r4+QR1]" 93049856 +d "- USR1 CoMACMus [0xff08], [r4+QR1]" 93049866 +d "CoMACMus [0xff08], [r4+QR1]" 93049806 d ".word 0xa334 .word 0x9956" A3349956 d ".word 0x8334 .word 0x9956" 83349956 -d "- USR0 CoMACMus [0xff08], [r4], rnd" 93049956 -d "- USR1 CoMACMus [0xff08], [r4], rnd" 93049966 -d "CoMACMus [0xff08], [r4], rnd" 93049906 +d "- USR0 CoMACMus [0xff08], [r4+QR1], rnd" 93049956 +d "- USR1 CoMACMus [0xff08], [r4+QR1], rnd" 93049966 +d "CoMACMus [0xff08], [r4+QR1], rnd" 93049906 d ".word 0xa334 .word 0xb856" A334B856 d ".word 0x8334 .word 0xb856" 8334B856 -d "- USR0 CoMACMRus [0xff08], [r4]" 9314B856 -d "- USR1 CoMACMRus [0xff08], [r4]" 9314B866 -d "CoMACMRus [0xff08], [r4]" 9314B806 -d "- USR0 CoMACMRus [0xff0a], [r4]" 9394B856 -d "- USR1 CoMACMRus [0xff0a], [r4]" 9394B866 -d "CoMACMRus [0xff0a], [r4]" 9394B806 +d "- USR0 CoMACMRus [0xff08], [r4+QR1]" 9314b856 +d "- USR1 CoMACMRus [0xff08], [r4+QR1]" 9314b866 +d "CoMACMRus [0xff08], [r4+QR1]" 9314b806 +d "- USR0 CoMACMRus [0xff0a], [r4+QR1]" 9394b856 +d "- USR1 CoMACMRus [0xff0a], [r4+QR1]" 9394b866 +d "CoMACMRus [0xff0a], [r4+QR1]" 9394b806 d ".word 0xa334 .word 0xb956" A334B956 d ".word 0x8334 .word 0xb956" 8334B956 -d "- USR0 CoMACMRus [0xff0a], [r4], rnd" 9394B956 -d "- USR1 CoMACMRus [0xff0a], [r4], rnd" 9394B966 -d "CoMACMRus [0xff0a], [r4], rnd" 9394B906 -d "- USR0 CoMACMRus [0xff08], [r4], rnd" 9314B956 -d "- USR1 CoMACMRus [0xff08], [r4], rnd" 9314B966 -d "CoMACMRus [0xff08], [r4], rnd" 9314B906 +d "- USR0 CoMACMRus [0xff0a], [r4+QR1], rnd" 9394b956 +d "- USR1 CoMACMRus [0xff0a], [r4+QR1], rnd" 9394b966 +d "CoMACMRus [0xff0a], [r4+QR1], rnd" 9394b906 +d "- USR0 CoMACMRus [0xff08], [r4+QR1], rnd" 9314b956 +d "- USR1 CoMACMRus [0xff08], [r4+QR1], rnd" 9314b966 +d "CoMACMRus [0xff08], [r4+QR1], rnd" 9314b906 d ".word 0xa334 .word 0xd856" A334D856 d ".word 0x8334 .word 0xd856" 8334D856 -d "- USR0 CoMACM [0xff08], [r4]" 9314D856 -d "- USR1 CoMACM [0xff08], [r4]" 9314D866 -d "CoMACM [0xff08], [r4]" 9314D806 -d "- USR0 CoMACM [0xff0a], [r4]" 9394D856 -d "- USR1 CoMACM [0xff0a], [r4]" 9394D866 -d "CoMACM [0xff0a], [r4]" 9394D806 +d "- USR0 CoMACM [0xff08], [r4+QR1]" 9314d856 +d "- USR1 CoMACM [0xff08], [r4+QR1]" 9314d866 +d "CoMACM [0xff08], [r4+QR1]" 9314d806 +d "- USR0 CoMACM [0xff0a], [r4+QR1]" 9394d856 +d "- USR1 CoMACM [0xff0a], [r4+QR1]" 9394d866 +d "CoMACM [0xff0a], [r4+QR1]" 9394d806 d ".word 0xa334 .word 0xd956" A334D956 d ".word 0x8334 .word 0xd956" 8334D956 -d "- USR0 CoMACM [0xff08], [r4], rnd" 9314D956 -d "- USR1 CoMACM [0xff08], [r4], rnd" 9314D966 -d "CoMACM [0xff08], [r4], rnd" 9314D906 -d "- USR0 CoMACM [0xff0a], [r4], rnd" 9394D956 -d "- USR1 CoMACM [0xff0a], [r4], rnd" 9394D966 -d "CoMACM [0xff0a], [r4], rnd" 9394D906 +d "- USR0 CoMACM [0xff08], [r4+QR1], rnd" 9314d956 +d "- USR1 CoMACM [0xff08], [r4+QR1], rnd" 9314d966 +d "CoMACM [0xff08], [r4+QR1], rnd" 9314d906 +d "- USR0 CoMACM [0xff0a], [r4+QR1], rnd" 9394d956 +d "- USR1 CoMACM [0xff0a], [r4+QR1], rnd" 9394d966 +d "CoMACM [0xff0a], [r4+QR1], rnd" 9394d906 d ".word 0xa334 .word 0xf856" A334F856 d ".word 0x8334 .word 0xf856" 8334F856 -d "- USR0 CoMACMR [0xff08], [r4]" 9304F856 -d "- USR1 CoMACMR [0xff08], [r4]" 9304F866 -d "CoMACMR [0xff08], [r4]" 9304F806 +d "- USR0 CoMACMR [0xff08], [r4+QR1]" 9304f856 +d "- USR1 CoMACMR [0xff08], [r4+QR1]" 9304f866 +d "CoMACMR [0xff08], [r4+QR1]" 9304f806 d ".word 0xa334 .word 0xf956" A334F956 d ".word 0x8334 .word 0xf956" 8334F956 -d "- USR0 CoMACMR [0xff08], [r4], rnd" 9304F956 -d "- USR1 CoMACMR [0xff08], [r4], rnd" 9304F966 -d "CoMACMR [0xff08], [r4], rnd" 9304F906 +d "- USR0 CoMACMR [0xff08], [r4+QR1], rnd" 9304f956 +d "- USR1 CoMACMR [0xff08], [r4+QR1], rnd" 9304f966 +d "CoMACMR [0xff08], [r4+QR1], rnd" 9304f906 -d "- USR0 CoNOP [0xff08 -2], [r4]" 93345A56 -d "- USR1 CoNOP [0xff08 -2], [r4]" 93345A66 -d "CoNOP [0xff08 -2], [r4]" 93345A06 +d "- USR0 CoNOP [0xff08-], [r4+QR1]" 93345a56 +d "- USR1 CoNOP [0xff08-], [r4+QR1]" 93345a66 +d "CoNOP [0xff08-], [r4+QR1]" 93345a06 d ".word 0xa334 .word 0xa856" A334A856 d ".word 0x8334 .word 0xa856" 8334A856 -d "- USR0 CoMACMus- [0xff08], [r4]" 9314A856 -d "- USR1 CoMACMus- [0xff08], [r4]" 9314A866 -d "CoMACMus- [0xff08], [r4]" 9314A806 -d "- USR0 CoMACMus- [0xff0a], [r4]" 9394A856 -d "- USR1 CoMACMus- [0xff0a], [r4]" 9394A866 -d "CoMACMus- [0xff0a], [r4]" 9394A806 +d "- USR0 CoMACMus- [0xff08], [r4+QR1]" 9314a856 +d "- USR1 CoMACMus- [0xff08], [r4+QR1]" 9314a866 +d "CoMACMus- [0xff08], [r4+QR1]" 9314a806 +d "- USR0 CoMACMus- [0xff0a], [r4+QR1]" 9394a856 +d "- USR1 CoMACMus- [0xff0a], [r4+QR1]" 9394a866 +d "CoMACMus- [0xff0a], [r4+QR1]" 9394a806 d ".word 0xa334 .word 0x2856" A3342856 d ".word 0x8334 .word 0x2856" 83342856 -d "- USR0 CoMACMu- [0xff08], [r4]" 93042856 -d "- USR1 CoMACMu- [0xff08], [r4]" 93042866 -d "CoMACMu- [0xff08], [r4]" 93042806 +d "- USR0 CoMACMu- [0xff08], [r4+QR1]" 93042856 +d "- USR1 CoMACMu- [0xff08], [r4+QR1]" 93042866 +d "CoMACMu- [0xff08], [r4+QR1]" 93042806 d ".word 0xa334 .word 0x6856" A3346856 d ".word 0x8334 .word 0x6856" 83346856 -d "- USR0 CoMACMsu- [0xff08], [r4]" 93046856 -d "- USR1 CoMACMsu- [0xff08], [r4]" 93046866 -d "CoMACMsu- [0xff08], [r4]" 93046806 +d "- USR0 CoMACMsu- [0xff08], [r4+QR1]" 93046856 +d "- USR1 CoMACMsu- [0xff08], [r4+QR1]" 93046866 +d "CoMACMsu- [0xff08], [r4+QR1]" 93046806 d ".word 0xa334 .word 0xe856" A334E856 d ".word 0x8334 .word 0xe856" 8334E856 -d "- USR0 CoMACM- [0xff08], [r4]" 9314E856 -d "- USR1 CoMACM- [0xff08], [r4]" 9314E866 -d "CoMACM- [0xff08], [r4]" 9314E806 -d "- USR0 CoMACM- [0xff0a], [r4]" 9394E856 -d "- USR1 CoMACM- [0xff0a], [r4]" 9394E866 -d "CoMACM- [0xff0a], [r4]" 9394E806 - - -d "- USR0 CoASHR [r5]" 8355AA56 -d "- USR1 CoASHR [r5]" 8355AA66 -d "CoASHR [r5]" 8355AA06 -d "- USR0 CoASHR [r3], rnd" 8333BA56 -d "- USR1 CoASHR [r3], rnd" 8333BA66 -d "CoASHR [r3], rnd" 8333BA06 -d "- USR0 CoASHR [r4], rnd" 8344BA56 -d "- USR1 CoASHR [r4], rnd" 8344BA66 -d "CoASHR [r4], rnd" 8344BA06 - - - +d "- USR0 CoMACM- [0xff08], [r4+QR1]" 9314e856 +d "- USR1 CoMACM- [0xff08], [r4+QR1]" 9314e866 +d "CoMACM- [0xff08], [r4+QR1]" 9314e806 +d "- USR0 CoMACM- [0xff0a], [r4+QR1]" 9394e856 +d "- USR1 CoMACM- [0xff0a], [r4+QR1]" 9394e866 +d "CoMACM- [0xff0a], [r4+QR1]" 9394e806 + +d "- USR0 CoASHR [r5+QR1]" 8355aa56 +d "- USR1 CoASHR [r5+QR1]" 8355aa66 +d "CoASHR [r5+QR1]" 8355aa06 +d "- USR0 CoASHR [r3+QR1], rnd" 8333ba56 +d "- USR1 CoASHR [r3+QR1], rnd" 8333ba66 +d "CoASHR [r3+QR1], rnd" 8333ba06 +d "- USR0 CoASHR [r4+QR1], rnd" 8344ba56 +d "- USR1 CoASHR [r4+QR1], rnd" 8344ba66 +d "CoASHR [r4+QR1], rnd" 8344ba06 d ".word 0x8334 .word 0x1a56" 83341A56 d ".word 0x9334 .word 0x1a56" 93341A56 @@ -1175,66 +1185,68 @@ d ".word 0xa334 .word 0xda56" A334DA56 d ".word 0xa334 .word 0xea56" A334EA56 d ".word 0xa334 .word 0xfa56" A334FA56 - -d "- USR0 CoSTORE [r3], (null)" B334FA56 -d "- USR1 CoSTORE [r3], (null)" B334FA66 -d "CoSTORE [r3], (null)" B334FA06 -d "- USR0 CoSTORE [r3], 0xffde" B3340056 -d "- USR1 CoSTORE [r3], 0xffde" B3340066 -d "CoSTORE [r3], 0xffde" B3340006 -d "- USR0 CoSTORE [r3], 0xfe5c" B3342056 -d "- USR1 CoSTORE [r3], 0xfe5c" B3342066 -d "CoSTORE [r3], 0xfe5c" B3342006 -d "- USR0 CoSTORE [r3], 0xffdc" B3342856 -d "- USR1 CoSTORE [r3], 0xffdc" B3342866 -d "CoSTORE [r3], 0xffdc" B3342806 -d "- USR0 CoSTORE [r3], (null)" B3346056 -d "- USR1 CoSTORE [r3], (null)" B3346066 -d "CoSTORE [r3], (null)" B3346006 -d "- USR0 CoSTORE [r3], 0xffda" B3343056 -d "- USR1 CoSTORE [r3], 0xffda" B3343066 -d "CoSTORE [r3], 0xffda" B3343006 -d "- USR0 CoSTORE r3, (null)" C334FA56 -d "- USR1 CoSTORE r3, (null)" C334FA66 -d "CoSTORE r3, (null)" C334FA06 -d "- USR0 CoSTORE r3, MAS" C3341056 -d "- USR1 CoSTORE r3, MAS" C3341066 -d "CoSTORE r3, MAS" C3341006 +d "- USR0 CoSTORE [r3], 0xffde" B3330041 # MSW +d "- USR0 CoSTORE [r3], 0xfe5e" B3330841 # MAH +d "- USR0 CoSTORE [r3], 0xffff" B3331041 # MAS +d "- USR0 CoSTORE [r3], 0xfe5c" B3332041 # MAL +d "- USR0 CoSTORE [r3], 0xffdc" B3332841 # MCW +d "- USR0 CoSTORE [r3], 0xffda" B3333041 # MRW + + + + +d "- USR0 CoSTORE [r3+QR1], 0xffff" b334fa56 +d "- USR1 CoSTORE [r3+QR1], 0xffff" b334fa66 +d "CoSTORE [r3+QR1], 0xffff" b334fa06 +d "- USR0 CoSTORE [r3+QR1], 0xffde" b3340056 +d "- USR1 CoSTORE [r3+QR1], 0xffde" b3340066 +d "CoSTORE [r3+QR1], 0xffde" b3340006 +d "- USR0 CoSTORE [r3+QR1], 0xfe5c" b3342056 +d "- USR1 CoSTORE [r3+QR1], 0xfe5c" b3342066 +d "CoSTORE [r3+QR1], 0xfe5c" b3342006 +d "- USR0 CoSTORE [r3+QR1], 0xffdc" b3342856 +d "- USR1 CoSTORE [r3+QR1], 0xffdc" b3342866 +d "CoSTORE [r3+QR1], 0xffdc" b3342806 +d "- USR0 CoSTORE [r3+QR1], 0xffff" b3346056 +d "- USR1 CoSTORE [r3+QR1], 0xffff" b3346066 +d "CoSTORE [r3+QR1], 0xffff" b3346006 +d "- USR0 CoSTORE [r3+QR1], 0xffda" b3343056 +d "- USR1 CoSTORE [r3+QR1], 0xffda" b3343066 +d "CoSTORE [r3+QR1], 0xffda" b3343006 +d "- USR0 CoSTORE r3, 0xffff" c334fa56 +d "- USR1 CoSTORE r3, 0xffff" c334fa66 +d "CoSTORE r3, 0xffff" c334fa06 +d "- USR0 CoSTORE r3, 0xffff" c3341056 +d "- USR1 CoSTORE r3, 0xffff" c3341066 +d "CoSTORE r3, 0xffff" c3341006 # D3 Xm 00 d ".word 0xd339 .word 0xfa56" D339FA56 -d "- USR0 CoMOV [0xff08 +2], [r4 + QR1]" D3240056 -d "- USR0 CoMOV [0xff0a +2], [r4 + QR1]" D3A40056 -d "- USR0 CoMOV [0xff08 -2], [r4 + QR1]" D3340056 -d "- USR0 CoMOV [0xff0a -2], [r4 + QR1]" D3B40056 -d "- USR0 CoMOV [0xff08], [r4 + QR1]" D3040056 -d "- USR0 CoMOV [0xff08], [r4 + QR1]" D3140056 -d "- USR0 CoMOV [0xff0a], [r4 + QR1]" D3940056 - -# d "- USR1 CoMACM [0xff08+], [r0+]" 9320D862 # NEED UPDATE -# d "- USR1 CoMACM [0xff08 -2], [r0+]" 9330D862 # NEED UPDATE +d "- USR0 CoMOV [0xff08+], [r4+QR1]" d3240056 +d "- USR0 CoMOV [0xff0a+], [r4+QR1]" d3a40056 +d "- USR0 CoMOV [0xff08-], [r4+QR1]" d3340056 +d "- USR0 CoMOV [0xff0a-], [r4+QR1]" d3b40056 +d "- USR0 CoMOV [0xff08], [r4+QR1]" D3040056 +d "- USR0 CoMOV [0xff08], [r4+QR1]" D3140056 +d "- USR0 CoMOV [0xff0a], [r4+QR1]" D3940056 -d "- USR0 CoMOV [0xff08], [r4 + QR1]" D3040056 -d "- USR0 CoMOV [0xff08 -2], [r2]" D3320040 -d "- USR0 CoMOV [0xff0a -2], [r2]" D3B20040 -d "- USR1 CoMOV [0xff08 -2], [r2]" D3320060 -d "- USR1 CoMOV [0xff0a -2], [r2]" D3B20060 +d "- USR0 CoMOV [0xff08], [r4+QR1]" D3040056 +d "- USR0 CoMOV [0xff08-], [r2]" d3320040 +d "- USR0 CoMOV [0xff0a-], [r2]" d3b20040 +d "- USR1 CoMOV [0xff08-], [r2]" d3320060 +d "- USR1 CoMOV [0xff0a-], [r2]" d3b20060 d ".word 0xd334 .word 0xba56" D334BA56 d ".word 0xd314 .word 0xba56" D314BA56 d ".word 0xd304 .word 0xba56" D304BA56 -d "- USR0 CoMOV [0xff08 -2], [r2 + QR1]" D3320056 -d "- USR0 CoMOV [0xff0a -2], [r2 + QR1]" D3B20056 -d "CoMOV [0xff08 -2], [r2]" D3320020 -d "CoMOV [0xff0a -2], [r2]" D3B20020 -d "CoMOV [0xff08 -2], [r2]" D3320000 -d "CoMOV [0xff0a -2], [r2]" D3B20000 - - -d "- USR0 CoMACM [0xff08 + QX0], [r0]" 9340D842 -d "- USR0 CoMACM [0xff08 + QX0], [r0]" 9340D843 +d "- USR0 CoMOV [0xff08-], [r2+QR1]" d3320056 +d "- USR0 CoMOV [0xff0a-], [r2+QR1]" d3b20056 +d "CoMOV [0xff08-], [r2]" d3320020 +d "CoMOV [0xff0a-], [r2]" d3b20020 +d "CoMOV [0xff08-], [r2]" d3320000 +d "CoMOV [0xff0a-], [r2]" d3b20000 #00C00500 CA180E5A CALLA+ CC_NUSR1,0xC05A0E "" CA180E5A diff --git a/test/db/rzil/c166 b/test/db/rzil/c166 new file mode 100644 index 00000000000..b63d50aea6e --- /dev/null +++ b/test/db/rzil/c166 @@ -0,0 +1,649 @@ +NAME=Testing the decryption in emulateme 1 +#FILE=bins/c166/emulateme.c166 +FILE=bins/omf/omf166/emulateme +TIMEOUT=30 +CMDS=<> (& (var r2) (bv 16 0x4000)) (bv 16 0xe) false))))) (set v false) (set c false) (set n (! (is_zero (>> (& (var r2) (bv 16 0x4000)) (bv 16 0xe) false)))) (branch (! (is_zero (>> (& (var r2) (bv 16 0x4000)) (bv 16 0xe) false))) (set r2 (- (var r2) (bv 16 0x4000))) nop) (branch (! (is_zero (>> (& (var r2) (bv 16 0x4000)) (bv 16 0xe) false))) (jmp (bv 32 0x9c)) nop)) +pc_write(old: 0x62, new: 0x66) +var_write(name: e, old: 0x0, new: 0x0) +var_read(name: r2, value: 0x8010) +var_write(name: z, old: 0x0, new: 0x1) +var_write(name: v, old: 0x0, new: 0x0) +var_write(name: c, old: 0x0, new: 0x0) +var_read(name: r2, value: 0x8010) +var_write(name: n, old: 0x0, new: 0x0) +var_read(name: r2, value: 0x8010) +var_read(name: r2, value: 0x8010) + +0x00000066 [aaf20ef0] jbc r2.15, 0x000086 +(seq (set e false) (set z (! (! (is_zero (>> (& (var r2) (bv 16 0x8000)) (bv 16 0xf) false))))) (set v false) (set c false) (set n (! (is_zero (>> (& (var r2) (bv 16 0x8000)) (bv 16 0xf) false)))) (branch (! (is_zero (>> (& (var r2) (bv 16 0x8000)) (bv 16 0xf) false))) (jmp (bv 32 0x86)) nop) (branch (! (is_zero (>> (& (var r2) (bv 16 0x8000)) (bv 16 0xf) false))) (set r2 (- (var r2) (bv 16 0x8000))) nop)) +pc_write(old: 0x66, new: 0x6a) +var_write(name: e, old: 0x0, new: 0x0) +var_read(name: r2, value: 0x8010) +var_write(name: z, old: 0x1, new: 0x0) +var_write(name: v, old: 0x0, new: 0x0) +var_write(name: c, old: 0x0, new: 0x0) +var_read(name: r2, value: 0x8010) +var_write(name: n, old: 0x0, new: 0x1) +var_read(name: r2, value: 0x8010) +pc_write(old: 0x6a, new: 0x86) +var_read(name: r2, value: 0x8010) +var_read(name: r2, value: 0x8010) +var_write(name: r2, old: 0x8010, new: 0x10) + +0x00000086 [dc09] exts r9, #1 +nop +pc_write(old: 0x86, new: 0x88) + +0x00000088 [9838] mov r3, [r8+] +(seq (set e (ite (== (loadw 0 16 (| (<< (cast 32 false (var r9)) (bv 16 0x10) false) (cast 32 false (var r8)))) (bv 16 0x8000)) true false)) (set z (ite (is_zero (loadw 0 16 (| (<< (cast 32 false (var r9)) (bv 16 0x10) false) (cast 32 false (var r8))))) true false)) (set n (msb (loadw 0 16 (| (<< (cast 32 false (var r9)) (bv 16 0x10) false) (cast 32 false (var r8)))))) (set r3 (cast 16 false (loadw 0 16 (| (<< (cast 32 false (var r9)) (bv 16 0x10) false) (cast 32 false (var r8)))))) (set r8 (+ (var r8) (bv 16 0x2)))) +pc_write(old: 0x88, new: 0x8a) +var_read(name: r9, value: 0x1) +var_read(name: r8, value: 0x801e) +mem_read(addr: 0x1801e, value: 0xe200) +var_write(name: e, old: 0x0, new: 0x0) +var_read(name: r9, value: 0x1) +var_read(name: r8, value: 0x801e) +mem_read(addr: 0x1801e, value: 0xe200) +var_write(name: z, old: 0x0, new: 0x0) +var_read(name: r9, value: 0x1) +var_read(name: r8, value: 0x801e) +mem_read(addr: 0x1801e, value: 0xe200) +var_write(name: n, old: 0x1, new: 0x1) +var_read(name: r9, value: 0x1) +var_read(name: r8, value: 0x801e) +mem_read(addr: 0x1801e, value: 0xe200) +var_write(name: r3, old: 0x8010, new: 0xe200) +var_read(name: r8, value: 0x801e) +var_write(name: r8, old: 0x801e, new: 0x8020) + +0x0000008a [dc44] extp r4, #1 +nop +pc_write(old: 0x8a, new: 0x8c) + +IL[0xfa] - [0x000000] IP: [0x000016] c166_il_jmps_seg_caddr +IL[0xa5] - [0x000016] IP: [0x000016] c166_il_diswdt +IL[0x0a] - [0x00001a] IP: [0x000016] c166_il_bfldl_bitoff_x bSFR BUSCON0, #0x3f, #0x2e +IL[0x1a] - [0x00001e] IP: [0x000016] c166_il_bfldh_bitoff_x bSFR BUSCON0, #0xd2, #0x00 +IL[0x1a] - [0x000022] IP: [0x000016] c166_il_bfldh_bitoff_x bSFR SYSCON, #0xfb, #0x00 +IL[0x0a] - [0x000026] IP: [0x000016] c166_il_bfldl_bitoff_x bSFR SYSCON, #0x6f, #0x00 +IL[0xe6] - [0x00002a] IP: [0x000016] c166_il_mov_reg_data16 0x0a 0xfa0c +IL[0xe6] - [0x00002e] IP: [0x000016] c166_il_mov_reg_data16 0x00 0x0000 +IL[0xe6] - [0x000032] IP: [0x000016] c166_il_mov_reg_data16 0x01 0x0001 +IL[0xe6] - [0x000036] IP: [0x000016] c166_il_mov_reg_data16 0x02 0x0003 +IL[0xe6] - [0x00003a] IP: [0x000016] c166_il_mov_reg_data16 0x08 0xfc00 +IL[0xb5] - [0x00003e] IP: [0x000016] c166_il_einit +IL[0xe6] - [0x000042] IP: [0x000016] c166_il_mov_reg_data16 0xf0 0xa200 +IL[0xe6] - [0x000046] IP: [0x000016] c166_il_mov_reg_data16 0xf9 0x0001 +IL[0xe6] - [0x00004a] IP: [0x000016] c166_il_mov_reg_data16 0xf8 0x801a +IL[0xf0] - [0x00004e] IP: [0x000016] c166_il_mov_rwn_rwm r1, r8 +IL[0x70] - [0x000050] IP: [0x000016] c166_il_or_rwn_rwm r1, r9 +IL[0x2d] - [0x000052] IP: [0x0000a6] c166_il_jmpr_rel cc_Z/EQ (4) new_IP: [0x0000a6] +IL[0xe0] - [0x000054] IP: [0x0000a6] c166_il_mov_rwn_data4 r5, #0x00 +IL[0xdc] - [0x000056] IP: [0x0000a6] c166_il_exts r9, #1 (esfr: true) +IL[0x98] - [0x000058] IP: [0x0000a6] c166_il_mov_rwn_orwmp r2, [r8+] (esfr: true) +IL[0x2d] - [0x00005a] IP: [0x0000a6] c166_il_jmpr_rel cc_Z/EQ (4) new_IP: [0x0000a6] +IL[0xf0] - [0x00005c] IP: [0x0000a6] c166_il_mov_rwn_rwm r3, r2 +IL[0xdc] - [0x00005e] IP: [0x0000a6] c166_il_exts r9, #1 (esfr: true) +IL[0x98] - [0x000060] IP: [0x0000a6] c166_il_mov_rwn_orwmp r4, [r8+] (esfr: true) +IL[0xaa] - [0x000062] IP: [0x0000a6] c166_il_jbc_bitaddr_rel new_IP: [0x00009c] reg: r2 + +EOF +RUN \ No newline at end of file